1 /* --COPYRIGHT--,ESD
2 * Copyright (c) 2008 Texas Instruments. All rights reserved.
3 * This program and the accompanying materials are made available under the
4 * terms of the Eclipse Public License v1.0 and Eclipse Distribution License
5 * v. 1.0 which accompanies this distribution. The Eclipse Public License is
6 * available at http://www.eclipse.org/legal/epl-v10.html and the Eclipse
7 * Distribution License is available at
8 * http://www.eclipse.org/org/documents/edl-v10.php.
9 *
10 * Contributors:
11 * Texas Instruments - initial implementation
12 * --/COPYRIGHT--*/
13 /*
14 * ======== Cache.xdc ========
15 */
16
17 import xdc.runtime.Error;
18 import xdc.runtime.knl.ICacheSupport;
19
20 /*!
21 * ======== Cache ========
22 * Cache Module [EXPERIMENTAL]
23 *
24 * The Cache module provide APIs to allow applications to maintain cache
25 * coherency.
26 *
27 * This module will use an OS specific delegate (back-end) to manipulate the
28 * cache.
29 * This module has a module wide config parameter {@link #Proxy} which needs to
30 * be bound to an OS specific delegate before this module can be used.
31 *
32 * Here is an example showing how the proxy is bound to an BIOS 6.x specific
33 * delegate
34 * var Cache = xdc.useModule('xdc.runtime.knl.Cache');
35 * Cache.Proxy = xdc.useModule('ti.sysbios.xdcruntime.CacheSupport');
36 *
37 * Typically the package containing the delegates have a Settings module that
38 * will bind all {@link xdc.runtime.knl} proxies. The following
39 * example sets up all the xdc.runtime.knl proxies.
40 *
41 * xdc.useModule("ti.sysbios.xdcruntime.Settings");
42 *
43 */
44
45 module Cache
46 {
47 /*!
48 * ======== Proxy ========
49 * ICacheSupport proxy
50 *
51 * Cache will use this proxy to access the cache hardware using
52 * OS specific APIs.
53 */
54 proxy Proxy inherits ICacheSupport;
55
56 /*!
57 * ======== inv ========
58 * Invalidate range of memory for all cache(s)
59 *
60 * Invalidate the range of memory within the specified starting
61 * address and byte count. The range of addresses operated on
62 * gets quantized to whole cache lines in each cache. All lines
63 * in range are invalidated for all cache types.
64 *
65 * @param(blockPtr) start address of range to be invalidated
66 * @param(byteCnt) number of bytes to be invalidated
67 * @param(wait) wait until the operation is completed
68 * @param(eb) error block
69 * @a(returns) true for success; false for error.
70 */
71 Bool inv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
72
73 /*!
74 * ======== wb ========
75 * Writes back a range of memory from all cache(s)
76 *
77 * Writes back the range of memory within the specified starting
78 * address and byte count. The range of addresses operated on
79 * gets quantized to whole cache lines in each cache. All lines
80 * within the range are left valid in all caches and the data
81 * within the range will be written back to the source memory.
82 *
83 * @param(blockPtr) start address of range to be invalidated
84 * @param(byteCnt) number of bytes to be invalidated
85 * @param(wait) wait until the operation is completed
86 * @param(eb) error block
87 * @a(returns) true for success; false for error.
88 */
89 Bool wb(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
90
91 /*!
92 * ======== wbInv ========
93 * Write back and invalidate range of memory.
94 *
95 * Writes back and invalidates the range of memory within the
96 * specified starting address and byte count. The range of
97 * addresses operated on gets quantized to whole cache lines in
98 * each cache. All lines within the range are written back to the
99 * source memory and then invalidated for all cache types.
100 *
101 * @param(blockPtr) start address of range to be invalidated
102 * @param(byteCnt) number of bytes to be invalidated
103 * @param(wait) wait until the operation is completed
104 * @param(eb) error block
105 * @a(returns) true for success; false for error.
106 */
107 Bool wbInv(Ptr blockPtr, SizeT byteCnt, Bool wait, Error.Block *eb);
108
109 /*!
110 * ======== wait ========
111 * Wait for a previous cache operation to complete
112 *
113 * Wait for the cache wb/wbInv/inv operation to complete. A cache
114 * operation is not truly complete until it has worked its way
115 * through all buffering and all memory writes have landed in the
116 * source memory.
117 *
118 * @param(eb) error block
119 * @a(returns) true for success; false for error.
120 */
121 Bool wait(Error.Block *eb);
122 }
123
124 /*
125 *! Revision History
126 *! ================
127 *! 17-Apr-2009 nitya Review updates
128 */
129 /*
130 * @(#) xdc.runtime.knl; 1, 0, 0,23; 7-29-2009 14:53:48; /db/ztree/library/trees/xdc-t56x/src/packages/
131 */
132