1 /* --COPYRIGHT--,EPL
2 * Copyright (c) 2009 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * --/COPYRIGHT--*/
12
13 /*
14 * ======== ITMS320CTCI6486.xdc ========
15 *
16 */
17
18 /*!
19 * ======== ITMS320CTCI6486 ========
20 * An interface implemented by TCI6486 like devices
21 *
22 */
23 metaonly interface ITMS320CTCI6486 inherits ti.catalog.ICpuDataSheet
24 {
25 config long cacheSizeL1[string] = [
26 ["0k", 0x0000],
27 ["4k", 0x1000],
28 ["8k", 0x2000],
29 ["16k", 0x4000],
30 ["32k", 0x8000],
31 ];
32
33 config long cacheSizeL2[string] = [
34 ["0k", 0x00000],
35 ["32k", 0x08000],
36 ["64k", 0x10000],
37 ["128k", 0x20000],
38 ["256k", 0x40000]
39 ];
40
41 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =
42
43 [
44 ['l1PMode',{desc:"L1P Cache",
45 map : [["0k",0x0000],
46 ["4k",0x1000],
47 ["8k",0x2000],
48 ["16k",0x4000],
49 ["32k",0x8000]],
50 defaultValue: "0k",
51 memorySection: "L1PSRAM"}],
52
53 ['l1DMode',{desc:"L1D Cache",
54 map : [["0k",0x0000],
55 ["4k",0x1000],
56 ["8k",0x2000],
57 ["16k",0x4000],
58 ["32k",0x8000]],
59 defaultValue: "0k",
60 memorySection: "L1DSRAM"}],
61
62 ['l2Mode',{desc:"L2 Cache",
63 map : [["0k",0x0000],
64 ["32k",0x8000],
65 ["64k",0x10000],
66 ["128k",0x20000],
67 ["256k",0x40000]],
68 defaultValue: "0k",
69 memorySection: "LL2RAM"}],
70
71 ];
72
73 instance:
74
75 override config string cpuCore = "64x+";
76 override config string isa="64P";
77 override config string cpuCoreRevision = "1.0";
78
79 override config int minProgUnitSize = 1;
80 override config int minDataUnitSize = 1;
81 override config int dataWordSize = 4;
82
83 /*!
84 * ======== memMap ========
85 * The default memory map for this device
86 */
87 config xdc.platform.IPlatform.Memory memMap[string] = [
88 ["LL2RAM", {
89 comment: "608K Local L2 RAM/CACHE memory",
90 name: "LL2RAM",
91 base: 0x00800000,
92 len: 0x00098000,
93 space: "code/data",
94 access: "RWX"
95 }],
96
97 ["L1PSRAM", {
98 comment: "Internal 32KB RAM/CACHE L1 program memory",
99 name: "L1PSRAM",
100 base: 0xE00000,
101 len: 0x008000,
102 space: "code",
103 access: "RWX"
104 }],
105
106 ["L1DSRAM", {
107 comment: "Internal 32KB RAM/CACHE L1 data memory",
108 name: "L1DSRAM",
109 base: 0xF00000,
110 len: 0x008000,
111 space: "data",
112 access: "RW"
113 }],
114
115 ["SL2RAM", {
116 comment: "768K Shared L2 RAM memory",
117 name: "SL2RAM",
118 base: 0x00200000,
119 len: 0x000C0000,
120 space: "code/data",
121 access: "RWX"
122 }],
123 ];
124 };
125 /*
126 * @(#) ti.catalog.c6000; 1, 0, 0, 0,185; 7-29-2009 16:15:21; /db/ztree/library/trees/platform-k16x/src/
127 */
128