1    /* --COPYRIGHT--,EPL
     2     *  Copyright (c) 2009 by Texas Instruments and others.
     3     *  All rights reserved. This program and the accompanying materials
     4     *  are made available under the terms of the Eclipse Public License v1.0
     5     *  which accompanies this distribution, and is available at
     6     *  http://www.eclipse.org/legal/epl-v10.html
     7     *
     8     *  Contributors:
     9     *      Texas Instruments - initial implementation
    10     *
    11     * --/COPYRIGHT--*/
    12    
    13    /*
    14     *  ======== ITMS320CTCI6484.xdc ========
    15     *
    16     */
    17    package ti.catalog.c6000;
    18    
    19    /*!
    20     *  ======== ITMS320CTCI6484 ========
    21     */
    22    metaonly interface ITMS320CTCI6484 inherits ti.catalog.ICpuDataSheet
    23    {
    24    
    25        config long cacheSizeL1[string] = [
    26            ["0k",  0x0000],
    27            ["4k",  0x1000],
    28            ["8k",  0x2000],
    29            ["16k", 0x4000],
    30            ["32k", 0x8000],
    31        ];
    32    
    33        config long cacheSizeL2[string] = [
    34            ["0k",    0x000000],
    35            ["32k",   0x008000],
    36            ["64k",   0x010000],
    37            ["128k",  0x020000],
    38            ["256k",  0x040000],
    39            ["512k",  0x080000],
    40            ["1024k", 0x100000]
    41        ];
    42    
    43        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    44             ['l1PMode',{desc:"L1P Cache",
    45                         map : [["0k",0x0000],
    46                                ["4k",0x1000],
    47                                ["8k",0x2000],
    48                                ["16k",0x4000],
    49                                ["32k",0x8000]],
    50                         defaultValue: "0k",
    51                         memorySection: "L1PSRAM"}],
    52         
    53                     ['l1DMode',{desc:"L1D Cache",
    54                         map : [["0k",0x0000],
    55                                ["4k",0x1000],
    56                                ["8k",0x2000],
    57                                ["16k",0x4000],
    58                                ["32k",0x8000]],
    59                         defaultValue: "0k",
    60                         memorySection: "L1DSRAM"}],
    61                     
    62             ['l2Mode',{desc:"L2 Cache",
    63                         map : [["0k",0x0000],
    64                                ["32k",0x8000],
    65                                ["64k",0x10000],
    66                                ["128k",0x20000],
    67                                ["256k",0x40000],
    68                                                        ["512k",  0x080000],
    69                                                        ["1024k", 0x100000]],
    70                         defaultValue: "0k",
    71                         memorySection: "IRAM"}], 
    72    
    73        ];
    74    
    75    instance:
    76    
    77        override config string   cpuCore        = "64x+";
    78        override config string   isa            = "64P";
    79        override config string   cpuCoreRevision = "1.0";
    80    
    81        override config int     minProgUnitSize = 1;
    82        override config int     minDataUnitSize = 1;    
    83        override config int     dataWordSize    = 4;
    84    
    85        /*!
    86         *  ======== memMap ========
    87         *  The default memory map for this device
    88         */
    89        config xdc.platform.IPlatform.Memory memMap[string]  = [
    90            ["IRAM", {
    91                comment:    "Internal 2MB L2 memory",
    92                name:       "IRAM",
    93                base:       0x800000,
    94                len:        0x200000,
    95                space:      "code/data",
    96                access:     "RWX"
    97            }],
    98    
    99            ["L1PSRAM", {
   100                comment:    "Internal 32KB RAM/CACHE L1 program memory",
   101                name:       "L1PSRAM",
   102                base:       0xE00000,
   103                len:        0x008000,
   104                space:      "code",
   105                access:     "RWX"
   106            }],
   107    
   108            ["L1DSRAM", {
   109                comment:    "Internal 32KB RAM/CACHE L1 data memory",
   110                name:       "L1DSRAM",
   111                base:       0xF00000,
   112                len:        0x008000,
   113                space:      "data",
   114                access:     "RW"
   115            }],
   116    
   117        ];
   118    };
   119    /*
   120     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,185; 7-29-2009 16:15:21; /db/ztree/library/trees/platform-k16x/src/
   121     */
   122