1 /* --COPYRIGHT--,EPL
2 * Copyright (c) 2009 by Texas Instruments and others.
3 * All rights reserved. This program and the accompanying materials
4 * are made available under the terms of the Eclipse Public License v1.0
5 * which accompanies this distribution, and is available at
6 * http://www.eclipse.org/legal/epl-v10.html
7 *
8 * Contributors:
9 * Texas Instruments - initial implementation
10 *
11 * --/COPYRIGHT--*/
12
13 /*
14 * ======== IHimalaya.xdc ========
15 *
16 */
17 package ti.catalog.c6000;
18
19 /*!
20 * ======== IHimalaya ========
21 * An interface implemented by all Himalaya devices
22 *
23 * This interface is defined to factor common data about all Himalaya devices
24 * into a single place; they are all the same from the configuration point of
25 * view.
26 */
27 metaonly interface IHimalaya inherits ti.catalog.ICpuDataSheet
28 {
29
30 config long cacheSizeL1[string] = [
31 ["0k", 0x0000],
32 ["4k", 0x1000],
33 ["8k", 0x2000],
34 ["16k", 0x4000],
35 ["32k", 0x8000],
36 ];
37
38 config long cacheSizeL2[string] = [
39 ["0k", 0x00000],
40 ["32k", 0x08000],
41 ["64k", 0x10000],
42 ["128k", 0x20000],
43 ["256k", 0x40000]
44 ];
45
46 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
47 ['l1PMode',{desc:"L1P Cache",
48 map : [["0k",0x0000],
49 ["4k",0x1000],
50 ["8k",0x2000],
51 ["16k",0x4000],
52 ["32k",0x8000]],
53 defaultValue: "0k",
54 memorySection: "L1PSRAM"}],
55
56 ['l1DMode',{desc:"L1D Cache",
57 map : [["0k",0x0000],
58 ["4k",0x1000],
59 ["8k",0x2000],
60 ["16k",0x4000],
61 ["32k",0x8000]],
62 defaultValue: "0k",
63 memorySection: "L1DSRAM"}],
64
65 ['l2Mode',{desc:"L2 Cache",
66 map : [["0k",0x0000],
67 ["32k",0x8000],
68 ["64k",0x10000],
69 ["128k", 0x20000],
70 ["256k", 0x40000]],
71 defaultValue: "0k",
72 memorySection: "IRAM"}],
73
74 ];
75
76 instance:
77
78 override config string cpuCore = "64x+";
79 override config string isa = "64P";
80 override config string cpuCoreRevision = "1.0";
81
82 override config int minProgUnitSize = 1;
83 override config int minDataUnitSize = 1;
84 override config int dataWordSize = 4;
85
86 /*!
87 * ======== memMap ========
88 * The default memory map for this device
89 */
90 config xdc.platform.IPlatform.Memory memMap[string] = [
91 ["IRAM", {
92 comment: "Internal 2MB UMAP0 memory",
93 name: "IRAM",
94 base: 0x800000,
95 len: 0x200000,
96 space: "code/data",
97 access: "RWX"
98 }],
99
100 ["L1PSRAM", {
101 comment: "Internal 32KB RAM/CACHE L1 program memory",
102 name: "L1PSRAM",
103 base: 0xE00000,
104 len: 0x008000,
105 space: "code",
106 access: "RWX"
107 }],
108
109 ["L1DSRAM", {
110 comment: "Internal 32KB RAM/CACHE L1 data memory",
111 name: "L1DSRAM",
112 base: 0xF00000,
113 len: 0x008000,
114 space: "data",
115 access: "RW"
116 }],
117
118 ];
119 };
120 /*
121 * @(#) ti.catalog.c6000; 1, 0, 0, 0,185; 7-29-2009 16:15:20; /db/ztree/library/trees/platform-k16x/src/
122 */
123