1 /*
2 * Copyright 2009 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10 /*
11 * ======== Primus.xdc ========
12 *
13 */
14 package ti.catalog.c6000.nda;
15
16 /*!
17 * ======== Primus ========
18 * The C64P device data sheet module.
19 *
20 * This module implements the xdc.platform.ICpuDataSheet interface and is
21 * used by platforms to obtain "data sheet" information about this device.
22 */
23 metaonly module Primus inherits ti.catalog.ICpuDataSheet
24 {
25
26 config long cacheSizeL1[string] = [
27 ["0k", 0x0000],
28 ["4k", 0x1000],
29 ["8k", 0x2000],
30 ["16k", 0x4000],
31 ["32k", 0x8000],
32 ];
33
34 config long cacheSizeL2[string] = [
35 ["0k", 0x00000],
36 ["32k", 0x08000],
37 ["64k", 0x10000],
38 ["128k",0x20000],
39 ["256k",0x40000],
40 ];
41
42 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
43 ['l1PMode',{desc:"L1P Cache",
44 map : [["0k",0x0000],
45 ["4k",0x1000],
46 ["8k",0x2000],
47 ["16k",0x4000],
48 ["32k",0x8000]],
49 defaultValue: "32k",
50 memorySection: "L1PSRAM"}],
51
52 ['l1DMode',{desc:"L1D Cache",
53 map : [["0k",0x0000],
54 ["4k",0x1000],
55 ["8k",0x2000],
56 ["16k",0x4000],
57 ["32k",0x8000]],
58 defaultValue: "32k",
59 memorySection: "L1DSRAM"}],
60
61 ['l2Mode',{desc:"L2 Cache",
62 map : [["0k",0x0000],
63 ["32k",0x8000],
64 ["64k",0x10000],
65 ["128k", 0x20000],
66 ["256k", 0x40000]],
67 defaultValue: "256k",
68 memorySection: "IRAM"}],
69
70 ];
71
72 instance:
73 override config int minProgUnitSize = 1;
74 override config int minDataUnitSize = 1;
75 override config int dataWordSize = 4;
76
77 override config string cpuCore = "Primus";
78 override config string isa = "64P";
79 override config string cpuCoreRevision = "1.0";
80
81 config xdc.platform.IPlatform.Memory memMap[string] = [
82 ["L2ROM", {
83 comment: "Internal 1MB L2 ROM",
84 name: "IROM",
85 base: 0x11700000,
86 len: 0x00100000,
87 space: "code/data",
88 access: "RX"
89 }],
90
91 ["IRAM", {
92 comment: "Internal 256KB L2 memory",
93 name: "IRAM",
94 base: 0x11800000,
95 len: 0x00040000,
96 space: "code/data",
97 access: "RWX"
98 }],
99
100 ["L1PSRAM", {
101 comment: "Internal 32KB L1 program memory",
102 name: "L1PSRAM",
103 base: 0x11E00000,
104 len: 0x00008000,
105 space: "code",
106 access: "RWX"
107 }],
108
109 ["L1DSRAM", {
110 comment: "Internal 32KB L1 data memory",
111 name: "L1DSRAM",
112 base: 0x11F00000,
113 len: 0x00008000,
114 space: "data",
115 access: "RW"
116 }],
117 ["L3_CBA_RAM", {
118 comment: "128KB ARM/DSP local shared RAM",
119 name: "L3_CBA_RAM",
120 base: 0x80000000,
121 len: 0x00020000,
122 space: "code/data",
123 access: "RWX"
124 }],
125 ];
126 };
127 /*
128 * @(#) ti.catalog.c6000.nda; 1, 0, 0, 0,80; 6-4-2009 14:20:23; /db/ztree/library/trees/platform-k10x/src/
129 */
130