1 /*
2 * Copyright 2009 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10 /*
11 * ======== TMS320CF761990.xdc ========
12 *
13 */
14 package ti.catalog.c6000;
15
16 /*!
17 * ======== TMS320CF761990 ========
18 * The C64P device data sheet module.
19 *
20 * This module implements the xdc.platform.ICpuDataSheet interface and is
21 * used by platforms to obtain "data sheet" information about this device.
22 */
23 metaonly module TMS320CF761990 inherits ti.catalog.ICpuDataSheet
24 {
25
26 config long cacheSizeL1[string] = [
27 ["0k", 0x0000],
28 ["4k", 0x1000],
29 ["8k", 0x2000],
30 ["16k", 0x4000],
31 ["32k", 0x8000],
32 ];
33
34 config long cacheSizeL2[string] = [
35 ["0k", 0x00000],
36 ["32k", 0x08000],
37 ["64k", 0x10000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',{desc:"L1P Cache",
42 map : [["0k",0x0000],
43 ["4k",0x1000],
44 ["8k",0x2000],
45 ["16k",0x4000],
46 ["32k",0x8000]],
47 defaultValue: "0k",
48 memorySection: "L1PSRAM"}],
49
50 ['l1DMode',{desc:"L1D Cache",
51 map : [["0k",0x0000],
52 ["4k",0x1000],
53 ["8k",0x2000],
54 ["16k",0x4000],
55 ["32k",0x8000]],
56 defaultValue: "0k",
57 memorySection: "L1DSRAM"}],
58
59 ['l2Mode',{desc:"L2 Cache",
60 map : [["0k",0x0000],
61 ["32k",0x8000],
62 ["64k",0x10000]],
63 defaultValue: "0k",
64 memorySection: "IRAM"}],
65
66 ];
67
68 instance:
69 override config int minProgUnitSize = 1;
70 override config int minDataUnitSize = 1;
71 override config int dataWordSize = 4;
72
73 override config string cpuCore = "F761990";
74 override config string isa = "64P";
75 override config string cpuCoreRevision = "1.0";
76
77 config xdc.platform.IPlatform.Memory memMap[string] = [
78 ["IRAM", {
79 comment: "Internal 64KB L2 UMAP0 memory",
80 name: "IRAM",
81 base: 0x11800000,
82 len: 0x00010000,
83 space: "code/data",
84 access: "RWX"
85 }],
86
87 ["L1PSRAM", {
88 comment: "Internal 32KB L1 program memory",
89 name: "L1PSRAM",
90 base: 0x11E08000,
91 len: 0x00008000,
92 space: "code",
93 access: "RWX"
94 }],
95
96 ["L1DSRAM", {
97 comment: "Internal 80KB L1 data memory",
98 name: "L1DSRAM",
99 base: 0x11F04000,
100 len: 0x00014000,
101 space: "data",
102 access: "RW"
103 }],
104
105 ["ARM_RAM0", {
106 comment: "Internal ARM RAM instruction memory",
107 name: "ARM_RAM0",
108 base: 0x02000000,
109 len: 0x00008000,
110 space: "code",
111 access: "RWX"
112 }],
113
114 ["ARM_RAM1", {
115 comment: "Internal ARM RAM data memory",
116 name: "ARM_RAM1",
117 base: 0x02008000,
118 len: 0x00004000,
119 space: "data",
120 access: "RW"
121 }],
122 ];
123 };
124 /*
125 * @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:56; /db/ztree/library/trees/platform-k10x/src/
126 */
127