1    /*
     2     *  Copyright 2009 by Texas Instruments Incorporated.
     3     *
     4     *  All rights reserved. Property of Texas Instruments Incorporated.
     5     *  Restricted rights to use, duplicate or disclose this code are
     6     *  granted through contract.
     7     *
     8     */
     9    
    10    /*
    11     *  ======== TMS320CDRA447.xdc ========
    12     *
    13     */
    14    
    15    /*!
    16     *  ======== TMS320CDRA447 ========
    17     *  The DRA447 device data sheet module.
    18     *
    19     *  This module implements the xdc.platform.ICpuDataSheet interface and is 
    20     *  used by platforms to obtain "data sheet" information about this device.
    21     */
    22    metaonly module TMS320CDRA447 inherits ITMS320CDRA44x
    23    {
    24    
    25        override config long cacheSizeL2[string] = [
    26            ["0k",  0x00000],
    27            ["32k", 0x08000],
    28            ["64k", 0x10000],
    29            ["128k", 0x20000]
    30        ];
    31    
    32        override readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    33                 ['l1PMode',{desc:"L1P Cache",
    34                             map : [["0k",0x0000],
    35                                    ["4k",0x1000],
    36                                    ["8k",0x2000],
    37                                    ["16k",0x4000],
    38                                    ["32k",0x8000]],
    39                             defaultValue: "0k",
    40                             memorySection: "L1PSRAM"}],
    41             
    42                     ['l1DMode',{desc:"L1D Cache",
    43                             map : [["0k",0x0000],
    44                                    ["4k",0x1000],
    45                                    ["8k",0x2000],
    46                                    ["16k",0x4000],
    47                                    ["32k",0x8000]],
    48                             defaultValue: "0k",
    49                             memorySection: "L1DSRAM"}],
    50                         
    51                 ['l2Mode',{desc:"L2 Cache",
    52                             map : [["0k",0x0000],
    53                                    ["32k",0x8000],
    54                                    ["64k",0x10000],
    55                                    ],
    56                             defaultValue: "0k",
    57                             memorySection: "IRAM"}], 
    58    
    59        ];
    60    
    61    instance:
    62    
    63        /*!
    64         *  ======== memMap ========
    65         *  The default memory map for this device
    66         */
    67        override config xdc.platform.IPlatform.Memory memMap[string] = [
    68            ["IRAM", {
    69                comment:    "Internal 128KB UMAP0 memory",
    70                name:       "IRAM",
    71                base:       0x11800000,
    72                len:        0x00020000,
    73                space:      "code/data",
    74                access:     "RWX"
    75            }],
    76            
    77            ["L1PSRAM", {
    78                comment:    "Internal 32KB RAM/CACHE L1 program memory",
    79                name:       "L1PSRAM",
    80                base:       0x11E08000,
    81                len:        0x00008000,
    82                space:      "code",
    83                access:     "RWX"
    84            }],
    85    
    86            ["L1DSRAM", {
    87                comment:    "Internal 80KB RAM/CACHE L1 data memory",
    88                name:       "L1DSRAM",
    89                base:       0x11F04000,
    90                len:        0x00014000,
    91                space:      "data",
    92                access:     "RW"
    93            }],
    94    
    95            ["ARM_RAM", {
    96                comment:    "Internal ARM RAM memory",
    97                name:       "ARM_RAM",
    98                base:       0x10008000,
    99                len:        0x00004000,
   100                space:      "data",
   101                access:     "RW"
   102            }],
   103        ];
   104    
   105    };
   106    /*
   107     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:56; /db/ztree/library/trees/platform-k10x/src/
   108     */
   109