1 /*
2 * Copyright 2009 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10 /*
11 * ======== TMS320CDM6431.xdc ========
12 *
13 */
14
15 package ti.catalog.c6000;
16
17 /*!
18 * ======== TMS320CDM6431 ========
19 * The DM6431 device data sheet module.
20 *
21 * This module implements the xdc.platform.ICpuDataSheet interface and is
22 * used by platforms to obtain "data sheet" information about this device.
23 */
24 metaonly module TMS320CDM6431 inherits ti.catalog.ICpuDataSheet
25 {
26 config long cacheSizeL1[string] = [
27 ["0k", 0x0000],
28 ["4k", 0x1000],
29 ["8k", 0x2000],
30 ["16k", 0x4000],
31 ["32k", 0x8000]
32 ];
33
34 config long cacheSizeL2[string] = [
35 ["0k", 0x00000],
36 ["32k", 0x08000],
37 ["64k", 0x10000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',{desc:"L1P Cache",
42 map : [["0k",0x0000],
43 ["4k",0x1000],
44 ["8k",0x2000],
45 ["16k",0x4000],
46 ["32k",0x8000]],
47 defaultValue: "0k",
48 memorySection: "L1PSRAM"}],
49
50 ['l1DMode',{desc:"L1D Cache",
51 map : [["0k",0x0000],
52 ["4k",0x1000],
53 ["8k",0x2000],
54 ["16k",0x4000],
55 ["32k",0x8000]],
56 defaultValue: "0k",
57 memorySection: "L1DSRAM"}],
58
59 ['l2Mode',{desc:"L2 Cache",
60 map : [["0k",0x0000],
61 ["32k",0x8000],
62 ["64k",0x10000]],
63 defaultValue: "0k",
64 memorySection: "IRAM"}],
65 ];
66
67 instance:
68
69 override config string cpuCore = "64x+";
70 override config string isa = "64P";
71 override config string cpuCoreRevision = "1.0";
72
73 override config int minProgUnitSize = 1;
74 override config int minDataUnitSize = 1;
75 override config int dataWordSize = 4;
76
77 /*!
78 * ======== memMap ========
79 * The default memory map for this device
80 */
81 config xdc.platform.IPlatform.Memory memMap[string] = [
82 ["IRAM", {
83 comment: "Internal 64KB L2 RAM/CACHE in UMAP0 memory",
84 name: "IRAM",
85 base: 0x10810000,
86 len: 0x00010000,
87 space: "code/data",
88 access: "RWX"
89 }],
90
91 ["L1PSRAM", {
92 comment: "Internal 32KB RAM/CACHE L1 program memory",
93 name: "L1PSRAM",
94 base: 0x10E08000,
95 len: 0x00008000,
96 space: "code",
97 access: "RWX"
98 }],
99
100 ["L1DSRAM", {
101 comment: "Internal 32KB RAM/CACHE L1 data memory",
102 name: "L1DSRAM",
103 base: 0x10F10000,
104 len: 0x00008000,
105 space: "data",
106 access: "RW"
107 }],
108 ];
109 };
110 /*
111 * @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:55; /db/ztree/library/trees/platform-k10x/src/
112 */
113