1    /*
     2     *  Copyright 2009 by Texas Instruments Incorporated.
     3     *
     4     *  All rights reserved. Property of Texas Instruments Incorporated.
     5     *  Restricted rights to use, duplicate or disclose this code are
     6     *  granted through contract.
     7     *
     8     */
     9    
    10    /*
    11     *  ======== ITMS320DA8xx.xdc ========
    12     *
    13     */
    14    package ti.catalog.c6000;
    15    
    16    /*!
    17     *  ======== ITMS320DA8xx ========
    18     *  An interface implemented by TMS320DA8xx devices.
    19     *
    20     */
    21    metaonly interface ITMS320DA8xx inherits ti.catalog.ICpuDataSheet
    22    {
    23    
    24        config long cacheSizeL1[string] = [
    25            ["0k",  0x0000],
    26            ["4k",  0x1000],
    27            ["8k",  0x2000],
    28            ["16k", 0x4000],
    29            ["32k", 0x8000],
    30        ];
    31    
    32        config long cacheSizeL2[string] = [
    33            ["0k",  0x00000],
    34            ["32k", 0x08000],
    35            ["64k", 0x10000],
    36            ["128k",0x20000],
    37            ["256k",0x40000],
    38        ];
    39    
    40        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    41                 ['l1PMode',{desc:"L1P Cache",
    42                             map : [["0k",0x0000],
    43                                    ["4k",0x1000],
    44                                    ["8k",0x2000],
    45                                    ["16k",0x4000],
    46                                    ["32k",0x8000]],
    47                             defaultValue: "0k",
    48                             memorySection: "L1PSRAM"}],
    49             
    50                     ['l1DMode',{desc:"L1D Cache",
    51                             map : [["0k",0x0000],
    52                                    ["4k",0x1000],
    53                                    ["8k",0x2000],
    54                                    ["16k",0x4000],
    55                                    ["32k",0x8000]],
    56                             defaultValue: "0k",
    57                             memorySection: "L1DSRAM"}],
    58                         
    59                 ['l2Mode',{desc:"L2 Cache",
    60                             map : [["0k",0x0000],
    61                                    ["32k",0x8000],
    62                                    ["64k",0x10000],
    63                                    ["128k",0x20000],
    64                                    ["256k",0x40000]],
    65                             defaultValue: "0k",
    66                             memorySection: "IRAM"}], 
    67    
    68        ];
    69    
    70    instance:
    71        override config int     minProgUnitSize = 1;
    72        override config int     minDataUnitSize = 1;    
    73        override config int     dataWordSize    = 4;
    74    
    75        override config string   cpuCore        = "C674";
    76        override config string   isa = "674";
    77        override config string   cpuCoreRevision = "1.0";
    78    
    79        config xdc.platform.IPlatform.Memory memMap[string]  = [
    80            ["IROM", {
    81                comment:    "Internal 1MB L2 ROM",
    82                name:       "IROM",
    83                base:       0x11700000,
    84                len:        0x00100000,
    85                space:      "code/data",
    86                access:     "RX"
    87            }],
    88    
    89            ["IRAM", {
    90                comment:    "Internal 256KB L2 memory",
    91                name:       "IRAM",
    92                base:       0x11800000,
    93                len:        0x00040000,
    94                space:      "code/data",
    95                access:     "RWX"
    96            }],
    97            
    98            ["L1PSRAM", {
    99                comment:    "Internal 32KB L1 program memory",
   100                name:       "L1PSRAM",
   101                base:       0x11E00000,
   102                len:        0x00008000,
   103                space:      "code",
   104                access:     "RWX"
   105            }],
   106    
   107            ["L1DSRAM", {
   108                comment:    "Internal 32KB L1 data memory",
   109                name:       "L1DSRAM",
   110                base:       0x11F00000,
   111                len:        0x00008000,
   112                space:      "data",
   113                access:     "RW"
   114            }],
   115            
   116            ["L3_CBA_RAM", {
   117                comment:    "128KB ARM/DSP local shared RAM",
   118                name:       "L3_CBA_RAM",
   119                base:       0x80000000,
   120                len:        0x00020000,
   121                space:      "code/data",
   122                access:     "RWX"
   123            }],
   124        ];
   125    };
   126    /*
   127     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:53; /db/ztree/library/trees/platform-k10x/src/
   128     */
   129