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14
15 package ti.catalog.c6000;
16
17 metaonly interface ITMS320CTCI6497 inherits ti.catalog.ICpuDataSheet
18 {
19
20 config long cacheSizeL1[string] = [
21 ["0k", 0x0000],
22 ["4k", 0x1000],
23 ["8k", 0x2000],
24 ["16k", 0x4000],
25 ["32k", 0x8000],
26 ];
27
28 config long cacheSizeL2[string] = [
29 ["0k", 0x000000],
30 ["32k", 0x008000],
31 ["64k", 0x010000],
32 ["128k", 0x020000],
33 ["256k", 0x040000],
34 ["512k", 0x080000],
35 ["1024k", 0x100000]
36 ];
37
38 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
39 ['l1PMode',{desc:"L1P Cache",
40 map : [["0k",0x0000],
41 ["4k",0x1000],
42 ["8k",0x2000],
43 ["16k",0x4000],
44 ["32k",0x8000]],
45 defaultValue: "0k",
46 memorySection: "L1PSRAM"}],
47
48 ['l1DMode',{desc:"L1D Cache",
49 map : [["0k",0x0000],
50 ["4k",0x1000],
51 ["8k",0x2000],
52 ["16k",0x4000],
53 ["32k",0x8000]],
54 defaultValue: "0k",
55 memorySection: "L1DSRAM"}],
56
57 ['l2Mode',{desc:"L2 Cache",
58 map : [["0k",0x0000],
59 ["32k",0x8000],
60 ["64k",0x10000],
61 ["128k", 0x020000],
62 ["256k", 0x040000],
63 ["512k", 0x080000],
64 ["1024k", 0x100000]],
65 defaultValue: "0k",
66 memorySection: "L2SRAM"}],
67
68 ];
69
70 instance:
71
72 override config string cpuCore = "64x+";
73 override config string isa = "64P";
74 override config string cpuCoreRevision = "1.0";
75
76 override config int minProgUnitSize = 1;
77 override config int minDataUnitSize = 1;
78 override config int dataWordSize = 4;
79
80 /*!
81 * ======== memMap ========
82 * The default memory map for this device
83 */
84 config xdc.platform.IPlatform.Memory memMap[string] = [
85 ["L2SRAM", {
86 comment: "1MB L2 SRAM/CACHE",
87 name: "L2SRAM",
88 base: 0x00800000,
89 len: 0x00100000,
90 space: "code/data",
91 access: "RWX"
92 }],
93
94 ["L1PSRAM", {
95 comment: "32KB RAM/CACHE L1 program memory",
96 name: "L1PSRAM",
97 base: 0x00E00000,
98 len: 0x00008000,
99 space: "code",
100 access: "RWX"
101 }],
102
103 ["L1DSRAM", {
104 comment: "32KB RAM/CACHE L1 data memory",
105 name: "L1DSRAM",
106 base: 0x00F00000,
107 len: 0x00008000,
108 space: "data",
109 access: "RW"
110 }],
111
112 ["MSMCSRAM", {
113 comment: "2MB MSMC SRAM",
114 name: "MSMCSRAM",
115 base: 0x0C000000,
116 len: 0x00200000,
117 space: "code/data",
118 access: "RWX"
119 }],
120 ];
121 };
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125