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14
15 package ti.catalog.c6000;
16
17 metaonly interface ITMS320CTCI6496 inherits ti.catalog.ICpuDataSheet
18 {
19
20 config long cacheSizeL1[string] = [
21 ["0k", 0x0000],
22 ["4k", 0x1000],
23 ["8k", 0x2000],
24 ["16k", 0x4000],
25 ["32k", 0x8000],
26 ];
27
28 config long cacheSizeL2[string] = [
29 ["0k", 0x000000],
30 ["32k", 0x008000],
31 ["64k", 0x010000],
32 ["128k", 0x020000],
33 ["256k", 0x040000],
34 ["512k", 0x080000]
35 ];
36
37 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
38 ['l1PMode',{desc:"L1P Cache",
39 map : [["0k",0x0000],
40 ["4k",0x1000],
41 ["8k",0x2000],
42 ["16k",0x4000],
43 ["32k",0x8000]],
44 defaultValue: "0k",
45 memorySection: "L1PSRAM"}],
46
47 ['l1DMode',{desc:"L1D Cache",
48 map : [["0k",0x0000],
49 ["4k",0x1000],
50 ["8k",0x2000],
51 ["16k",0x4000],
52 ["32k",0x8000]],
53 defaultValue: "0k",
54 memorySection: "L1DSRAM"}],
55
56 ['l2Mode',{desc:"L2 Cache",
57 map : [["0k",0x0000],
58 ["32k",0x8000],
59 ["64k",0x10000],
60 ["128k", 0x020000],
61 ["256k", 0x040000],
62 ["512k", 0x080000]],
63 defaultValue: "0k",
64 memorySection: "IRAM"}],
65
66 ];
67
68 instance:
69
70 override config string cpuCore = "64x+";
71 override config string isa = "64P";
72 override config string cpuCoreRevision = "1.0";
73
74 override config int minProgUnitSize = 1;
75 override config int minDataUnitSize = 1;
76 override config int dataWordSize = 4;
77
78 /*!
79 * ======== memMap ========
80 * The default memory map for this device
81 */
82 config xdc.platform.IPlatform.Memory memMap[string] = [
83 ["L2SRAM", {
84 comment: "512KB L2 SRAM/CACHE",
85 name: "L2SRAM",
86 base: 0x00800000,
87 len: 0x00080000,
88 space: "code/data",
89 access: "RWX"
90 }],
91
92 ["L1PSRAM", {
93 comment: "32KB RAM/CACHE L1 program memory",
94 name: "L1PSRAM",
95 base: 0x00E00000,
96 len: 0x00008000,
97 space: "code",
98 access: "RWX"
99 }],
100
101 ["L1DSRAM", {
102 comment: "32KB RAM/CACHE L1 data memory",
103 name: "L1DSRAM",
104 base: 0x00F00000,
105 len: 0x00008000,
106 space: "data",
107 access: "RW"
108 }],
109
110 ["MSMCSRAM", {
111 comment: "4MB MSMC SRAM",
112 name: "MSMCSRAM",
113 base: 0x0C000000,
114 len: 0x00400000,
115 space: "code/data",
116 access: "RWX"
117 }],
118 ];
119 };
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