1    /*
     2     *  Copyright 2009 by Texas Instruments Incorporated.
     3     *
     4     *  All rights reserved. Property of Texas Instruments Incorporated.
     5     *  Restricted rights to use, duplicate or disclose this code are
     6     *  granted through contract.
     7     *
     8     */
     9    
    10    /*
    11     *  ======== ITMS320CTCI6486.xdc ========
    12     *
    13     */
    14    
    15    /*!
    16     *  ======== ITMS320CTCI6486 ========
    17     *  An interface implemented by TCI6486 like devices
    18     *
    19     */
    20    metaonly interface ITMS320CTCI6486 inherits ti.catalog.ICpuDataSheet
    21    {
    22        config long cacheSizeL1[string] = [
    23            ["0k",  0x0000],
    24            ["4k",  0x1000],
    25            ["8k",  0x2000],
    26            ["16k", 0x4000],
    27            ["32k", 0x8000],
    28        ];
    29    
    30        config long cacheSizeL2[string] = [
    31            ["0k",   0x00000],
    32            ["32k",  0x08000],
    33            ["64k",  0x10000],
    34            ["128k", 0x20000],
    35            ["256k", 0x40000]
    36        ];
    37    
    38        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =
    39    
    40            [
    41                     ['l1PMode',{desc:"L1P Cache",
    42                                 map : [["0k",0x0000],
    43                                        ["4k",0x1000],
    44                                        ["8k",0x2000],
    45                                        ["16k",0x4000],
    46                                        ["32k",0x8000]],
    47                                 defaultValue: "0k",
    48                                 memorySection: "L1PSRAM"}],
    49             
    50                             ['l1DMode',{desc:"L1D Cache",
    51                                 map : [["0k",0x0000],
    52                                        ["4k",0x1000],
    53                                        ["8k",0x2000],
    54                                        ["16k",0x4000],
    55                                        ["32k",0x8000]],
    56                                 defaultValue: "0k",
    57                                 memorySection: "L1DSRAM"}],
    58                         
    59                 ['l2Mode',{desc:"L2 Cache",
    60                                 map : [["0k",0x0000],
    61                                    ["32k",0x8000],
    62                                    ["64k",0x10000],
    63                                    ["128k",0x20000],
    64                                    ["256k",0x40000]],
    65                                 defaultValue: "0k",
    66                                 memorySection: "LL2RAM"}], 
    67    
    68            ];
    69    
    70    instance:
    71    
    72        override config string   cpuCore        = "64x+";
    73        override config string   isa="64P";
    74        override config string   cpuCoreRevision = "1.0";
    75    
    76        override config int     minProgUnitSize = 1;
    77        override config int     minDataUnitSize = 1;    
    78        override config int     dataWordSize    = 4;
    79    
    80        /*!
    81         *  ======== memMap ========
    82         *  The default memory map for this device
    83         */
    84        config xdc.platform.IPlatform.Memory memMap[string]  = [
    85            ["LL2RAM", {
    86                comment:    "608K Local L2 RAM/CACHE memory",
    87                name:       "LL2RAM",
    88                base:       0x00800000,
    89                len:        0x00098000,
    90                space:      "code/data",
    91                access:     "RWX"
    92            }],
    93    
    94            ["L1PSRAM", {
    95                comment:    "Internal 32KB RAM/CACHE L1 program memory",
    96                name:       "L1PSRAM",
    97                base:       0xE00000,
    98                len:        0x008000,
    99                space:      "code",
   100                access:     "RWX"
   101            }],
   102    
   103            ["L1DSRAM", {
   104                comment:    "Internal 32KB RAM/CACHE L1 data memory",
   105                name:       "L1DSRAM",
   106                base:       0xF00000,
   107                len:        0x008000,
   108                space:      "data",
   109                access:     "RW"
   110            }],
   111    
   112            ["SL2RAM", {
   113                comment:    "768K Shared L2 RAM memory",
   114                name:       "SL2RAM",
   115                base:       0x00200000,
   116                len:        0x000C0000,
   117                space:      "code/data",
   118                access:     "RWX"
   119            }],
   120        ];
   121    };
   122    /*
   123     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:53; /db/ztree/library/trees/platform-k10x/src/
   124     */
   125