1 /*
2 * Copyright 2009 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10 /*
11 * ======== ITMS320CTCI6484.xdc ========
12 *
13 */
14 package ti.catalog.c6000;
15
16 /*!
17 * ======== ITMS320CTCI6484 ========
18 */
19 metaonly interface ITMS320CTCI6484 inherits ti.catalog.ICpuDataSheet
20 {
21
22 config long cacheSizeL1[string] = [
23 ["0k", 0x0000],
24 ["4k", 0x1000],
25 ["8k", 0x2000],
26 ["16k", 0x4000],
27 ["32k", 0x8000],
28 ];
29
30 config long cacheSizeL2[string] = [
31 ["0k", 0x000000],
32 ["32k", 0x008000],
33 ["64k", 0x010000],
34 ["128k", 0x020000],
35 ["256k", 0x040000],
36 ["512k", 0x080000],
37 ["1024k", 0x100000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',{desc:"L1P Cache",
42 map : [["0k",0x0000],
43 ["4k",0x1000],
44 ["8k",0x2000],
45 ["16k",0x4000],
46 ["32k",0x8000]],
47 defaultValue: "0k",
48 memorySection: "L1PSRAM"}],
49
50 ['l1DMode',{desc:"L1D Cache",
51 map : [["0k",0x0000],
52 ["4k",0x1000],
53 ["8k",0x2000],
54 ["16k",0x4000],
55 ["32k",0x8000]],
56 defaultValue: "0k",
57 memorySection: "L1DSRAM"}],
58
59 ['l2Mode',{desc:"L2 Cache",
60 map : [["0k",0x0000],
61 ["32k",0x8000],
62 ["64k",0x10000],
63 ["128k",0x20000],
64 ["256k",0x40000],
65 ["512k", 0x080000],
66 ["1024k", 0x100000]],
67 defaultValue: "0k",
68 memorySection: "IRAM"}],
69
70 ];
71
72 instance:
73
74 override config string cpuCore = "64x+";
75 override config string isa = "64P";
76 override config string cpuCoreRevision = "1.0";
77
78 override config int minProgUnitSize = 1;
79 override config int minDataUnitSize = 1;
80 override config int dataWordSize = 4;
81
82 /*!
83 * ======== memMap ========
84 * The default memory map for this device
85 */
86 config xdc.platform.IPlatform.Memory memMap[string] = [
87 ["IRAM", {
88 comment: "Internal 2MB L2 memory",
89 name: "IRAM",
90 base: 0x800000,
91 len: 0x200000,
92 space: "code/data",
93 access: "RWX"
94 }],
95
96 ["L1PSRAM", {
97 comment: "Internal 32KB RAM/CACHE L1 program memory",
98 name: "L1PSRAM",
99 base: 0xE00000,
100 len: 0x008000,
101 space: "code",
102 access: "RWX"
103 }],
104
105 ["L1DSRAM", {
106 comment: "Internal 32KB RAM/CACHE L1 data memory",
107 name: "L1DSRAM",
108 base: 0xF00000,
109 len: 0x008000,
110 space: "data",
111 access: "RW"
112 }],
113
114 ];
115 };
116 /*
117 * @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:52; /db/ztree/library/trees/platform-k10x/src/
118 */
119