1    /*
     2     *  Copyright 2009 by Texas Instruments Incorporated.
     3     *
     4     *  All rights reserved. Property of Texas Instruments Incorporated.
     5     *  Restricted rights to use, duplicate or disclose this code are
     6     *  granted through contract.
     7     *
     8     */
     9    
    10    /*
    11     *  ======== ITMS320CDRA45x.xdc ========
    12     *
    13     */
    14    
    15    /*!
    16     *  ======== ITMS320CDRA45x ========
    17     *  An interface implemented by all DRA45x devices
    18     *
    19     *  This interface is defined to factor common data about all DRA45x devices
    20     *  into a single place; they are all the same from the configuration point of
    21     *  view.
    22     */
    23    metaonly interface ITMS320CDRA45x inherits ti.catalog.ICpuDataSheet
    24    {
    25        config long cacheSizeL1[string] = [
    26            ["0k",  0x0000],
    27            ["4k",  0x1000],
    28            ["8k",  0x2000],
    29            ["16k", 0x4000],
    30            ["32k", 0x8000],
    31        ];
    32    
    33        config long cacheSizeL2[string] = [
    34            ["0k",  0x00000],
    35            ["32k", 0x08000],
    36            ["64k", 0x10000],
    37            ["128k", 0x20000]
    38        ];
    39    
    40        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    41                 ['l1PMode',{desc:"L1P Cache",
    42                             map : [["0k",0x0000],
    43                                    ["4k",0x1000],
    44                                    ["8k",0x2000],
    45                                    ["16k",0x4000],
    46                                    ["32k",0x8000]],
    47                             defaultValue: "0k",
    48                             memorySection: "L1PSRAM"}],
    49             
    50                     ['l1DMode',{desc:"L1D Cache",
    51                             map : [["0k",0x0000],
    52                                    ["4k",0x1000],
    53                                    ["8k",0x2000],
    54                                    ["16k",0x4000],
    55                                    ["32k",0x8000]],
    56                             defaultValue: "0k",
    57                             memorySection: "L1DSRAM"}],
    58                         
    59                 ['l2Mode',{desc:"L2 Cache",
    60                             map : [["0k",0x0000],
    61                                    ["32k",0x8000],
    62                                    ["64k",0x10000],
    63                                    ["128k",0x20000]],
    64                             defaultValue: "0k",
    65                             memorySection: "IRAM"}], 
    66    
    67        ];
    68    
    69    instance:
    70        
    71        override config string   cpuCore        = "64x+";
    72        override config string   isa            = "64P";
    73        override config string   cpuCoreRevision = "1.0";
    74    
    75        override config int     minProgUnitSize = 1;
    76        override config int     minDataUnitSize = 1;    
    77        override config int     dataWordSize    = 4;
    78    
    79        /*!
    80         *  ======== memMap ========
    81         *  The default memory map for this device
    82         */
    83        config xdc.platform.IPlatform.Memory memMap[string]  = [
    84            ["IRAM", {
    85                comment:    "Internal 128KB UMAP0 memory",
    86                name:       "IRAM",
    87                base:       0x11800000,
    88                len:        0x00020000,
    89                space:      "code/data",
    90                access:     "RWX"
    91            }],
    92    
    93            ["L1PSRAM", {
    94                comment:    "Internal 32KB RAM/CACHE L1 program memory",
    95                name:       "L1PSRAM",
    96                base:       0x11E08000,
    97                len:        0x00008000,
    98                space:      "code",
    99                access:     "RWX"
   100            }],
   101    
   102            ["L1DSRAM", {
   103                comment:    "Internal 80KB RAM/CACHE L1 data memory",
   104                name:       "L1DSRAM",
   105                base:       0x11F04000,
   106                len:        0x00014000,
   107                space:      "data",
   108                access:     "RW"
   109            }],
   110    
   111            ["ARM_RAM", {
   112                comment:    "Internal ARM RAM memory",
   113                name:       "ARM_RAM",
   114                base:       0x10008000,
   115                len:        0x00004000,
   116                space:      "data",
   117                access:     "RW"
   118            }],
   119        ];
   120    };
   121    /*
   122     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:52; /db/ztree/library/trees/platform-k10x/src/
   123     */
   124