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15 /*!
16 * ======== ITMS320CDRA44x ========
17 * An interface implemented by all DRA44x devices
18 *
19 * This interface is defined to factor common data about all DRA44x devices
20 * into a single place; they are all the same from the configuration point of
21 * view.
22 */
23 metaonly interface ITMS320CDRA44x inherits ti.catalog.ICpuDataSheet
24 {
25 config long cacheSizeL1[string] = [
26 ["0k", 0x0000],
27 ["4k", 0x1000],
28 ["8k", 0x2000],
29 ["16k", 0x4000],
30 ["32k", 0x8000],
31 ];
32
33 config long cacheSizeL2[string] = [
34 ["0k", 0x00000],
35 ["32k", 0x08000],
36 ["64k", 0x10000]
37 ];
38
39 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
40 ['l1PMode',{desc:"L1P Cache",
41 map : [["0k",0x0000],
42 ["4k",0x1000],
43 ["8k",0x2000],
44 ["16k",0x4000],
45 ["32k",0x8000]],
46 defaultValue: "0k",
47 memorySection: "L1PSRAM"}],
48
49 ['l1DMode',{desc:"L1D Cache",
50 map : [["0k",0x0000],
51 ["4k",0x1000],
52 ["8k",0x2000],
53 ["16k",0x4000],
54 ["32k",0x8000]],
55 defaultValue: "0k",
56 memorySection: "L1DSRAM"}],
57
58 ['l2Mode',{desc:"L2 Cache",
59 map : [["0k",0x0000],
60 ["32k",0x8000],
61 ["64k",0x10000]],
62 defaultValue: "0k",
63 memorySection: "IRAM"}]
64
65 ];
66
67 instance:
68
69 override config string cpuCore = "64x+";
70 override config string isa = "64P";
71 override config string cpuCoreRevision = "1.0";
72
73 override config int minProgUnitSize = 1;
74 override config int minDataUnitSize = 1;
75 override config int dataWordSize = 4;
76
77 /*!
78 * ======== memMap ========
79 * The default memory map for this device
80 */
81 config xdc.platform.IPlatform.Memory memMap[string] = [
82 ["IRAM", {
83 comment: "Internal 64KB UMAP0 memory",
84 name: "IRAM",
85 base: 0x11800000,
86 len: 0x00010000,
87 space: "code/data",
88 access: "RWX"
89 }],
90
91 ["L1PSRAM", {
92 comment: "Internal 32KB RAM/CACHE L1 program memory",
93 name: "L1PSRAM",
94 base: 0x11E08000,
95 len: 0x00008000,
96 space: "code",
97 access: "RWX"
98 }],
99
100 ["L1DSRAM", {
101 comment: "Internal 80KB RAM/CACHE L1 data memory",
102 name: "L1DSRAM",
103 base: 0x11F04000,
104 len: 0x00014000,
105 space: "data",
106 access: "RW"
107 }],
108
109 ["ARM_RAM", {
110 comment: "Internal ARM RAM memory",
111 name: "ARM_RAM",
112 base: 0x10008000,
113 len: 0x00004000,
114 space: "data",
115 access: "RW"
116 }],
117 ];
118 };
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