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10 11 12 13
14 package ti.catalog.c6000;
15
16 /*!
17 * ======== ITMS320CDM6467 ========
18 * An interface implemented by all DaVinci-HD devices
19 *
20 * This interface is defined to factor common data about all DaVinci-HD devices
21 * into a single place; they are all the same from the configuration point of
22 * view.
23 */
24 metaonly interface ITMS320CDM6467 inherits ti.catalog.ICpuDataSheet
25 {
26 config long cacheSizeL1[string] = [
27 ["0k", 0x0000],
28 ["4k", 0x1000],
29 ["8k", 0x2000],
30 ["16k", 0x4000],
31 ["32k", 0x8000],
32 ];
33
34 config long cacheSizeL2[string] = [
35 ["0k", 0x00000],
36 ["32k", 0x08000],
37 ["64k", 0x10000],
38 ["128k", 0x20000],
39 ];
40
41 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
42 ['l1PMode',{desc:"L1P Cache",
43 map : [["0k",0x0000],
44 ["4k",0x1000],
45 ["8k",0x2000],
46 ["16k",0x4000],
47 ["32k",0x8000]],
48 defaultValue: "0k",
49 memorySection: "L1PSRAM"}],
50
51 ['l1DMode',{desc:"L1D Cache",
52 map : [["0k",0x0000],
53 ["4k",0x1000],
54 ["8k",0x2000],
55 ["16k",0x4000],
56 ["32k",0x8000]],
57 defaultValue: "0k",
58 memorySection: "L1DSRAM"}],
59
60 ['l2Mode',{desc:"L2 Cache",
61 map : [["0k",0x0000],
62 ["32k",0x8000],
63 ["64k",0x10000],
64 ["128k",0x20000]],
65 defaultValue: "0k",
66 memorySection: "IRAM"}]
67
68 ];
69
70 instance:
71
72 override config string cpuCore = "64x+";
73 override config string isa = "64P";
74 override config string cpuCoreRevision = "1.0";
75
76 override config int minProgUnitSize = 1;
77 override config int minDataUnitSize = 1;
78 override config int dataWordSize = 4;
79
80 /*!
81 * ======== memMap ========
82 * The default memory map for this device
83 */
84 config xdc.platform.IPlatform.Memory memMap[string] = [
85 ["ARM_RAM", {
86 comment: "Internal ARM RAM memory",
87 name: "ARM_RAM",
88 base: 0x10010000,
89 len: 0x00008000,
90 space: "data",
91 access: "RW"
92 }],
93
94 ["IRAM", {
95 comment: "Internal 128KB UMAP0 memory",
96 name: "IRAM",
97 base: 0x11818000,
98 len: 0x00020000,
99 space: "code/data",
100 access: "RWX"
101 }],
102
103 ["L1PSRAM", {
104 comment: "Internal 32KB RAM/CACHE L1 program memory",
105 name: "L1PSRAM",
106 base: 0x11E00000,
107 len: 0x00008000,
108 space: "code",
109 access: "RWX"
110 }],
111
112 ["L1DSRAM", {
113 comment: "Internal 32KB RAM/CACHE L1 data memory",
114 name: "L1DSRAM",
115 base: 0x11F00000,
116 len: 0x00008000,
117 space: "data",
118 access: "RW"
119 }],
120 ];
121 };
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125