1 /*
2 * Copyright 2009 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10 /*
11 * ======== ITMS320C642x.xdc ========
12 *
13 */
14
15 /*!
16 * ======== ITMS320C642x ========
17 * The C642x device data sheet module.
18 *
19 * This module implements the ICpuDataSheet interface and is
20 * used by platforms to obtain "data sheet" information about this device.
21 */
22 metaonly interface ITMS320C642x inherits ti.catalog.ICpuDataSheet
23 {
24 config long cacheSizeL1[string] = [
25 ["0k", 0x0000],
26 ["4k", 0x1000],
27 ["8k", 0x2000],
28 ["16k", 0x4000],
29 ["32k", 0x8000],
30 ];
31
32 config long cacheSizeL2[string] = [
33 ["0k", 0x00000],
34 ["32k", 0x08000],
35 ["64k", 0x10000],
36 ["128k", 0x20000]
37 ];
38
39 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
40 ['l1PMode',{desc:"L1P Cache",
41 map : [["0k",0x0000],
42 ["4k",0x1000],
43 ["8k",0x2000],
44 ["16k",0x4000],
45 ["32k",0x8000]],
46 defaultValue: "0k",
47 memorySection: "L1PSRAM"}],
48
49 ['l1DMode',{desc:"L1D Cache",
50 map : [["0k",0x0000],
51 ["4k",0x1000],
52 ["8k",0x2000],
53 ["16k",0x4000],
54 ["32k",0x8000]],
55 defaultValue: "0k",
56 memorySection: "L1DSRAM"}],
57
58 ['l2Mode',{desc:"L2 Cache",
59 map : [["0k",0x0000],
60 ["32k",0x8000],
61 ["64k",0x10000],
62 ["128k",0x20000]],
63 defaultValue: "0k",
64 memorySection: "IRAM"}],
65
66 ];
67
68 instance:
69
70 override config string cpuCore = "64x+";
71 override config string isa = "64P";
72 override config string cpuCoreRevision = "1.0";
73
74 override config int minProgUnitSize = 1;
75 override config int minDataUnitSize = 1;
76 override config int dataWordSize = 4;
77
78 /*!
79 * ======== memMap ========
80 * The default memory map for this device
81 */
82 config xdc.platform.IPlatform.Memory memMap[string] = [
83 ["IRAM", {
84 comment: "Internal 128KB UMAP0 memory",
85 name: "IRAM",
86 base: 0x10800000,
87 len: 0x00020000,
88 space: "code/data",
89 access: "RWX"
90 }],
91
92 ["L1PSRAM", {
93 comment: "Internal 32KB RAM/CACHE L1 program memory",
94 name: "L1PSRAM",
95 base: 0x10E08000,
96 len: 0x00008000,
97 space: "code",
98 access: "RWX"
99 }],
100
101 ["L1DSRAM", {
102 comment: "Internal 80KB RAM/CACHE L1 data memory",
103 name: "L1DSRAM",
104 base: 0x10F04000,
105 len: 0x00014000,
106 space: "data",
107 access: "RW"
108 }],
109 ];
110 };
111 /*
112 * @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:52; /db/ztree/library/trees/platform-k10x/src/
113 */
114