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14 package ti.catalog.c6000;
15
16 /*!
17 * ======== IOMAP3xxx ========
18 * An interface implemented by all OMAP3xxx devices
19 *
20 * This interface is defined to factor common data about all OMAP3xxx devices
21 * into a single place; they all have the same internal memory.
22 */
23 metaonly interface IOMAP3xxx inherits ti.catalog.ICpuDataSheet
24 {
25
26 config long cacheSizeL1[string] = [
27 ["0k", 0x0000],
28 ["4k", 0x1000],
29 ["8k", 0x2000],
30 ["16k", 0x4000],
31 ["32k", 0x8000],
32 ];
33
34 config long cacheSizeL2[string] = [
35 ["0k", 0x00000],
36 ["32k", 0x08000],
37 ["64k", 0x10000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',{desc:"L1P Cache",
42 map : [["0k",0x0000],
43 ["4k",0x1000],
44 ["8k",0x2000],
45 ["16k",0x4000],
46 ["32k",0x8000]],
47 defaultValue: "0k",
48 memorySection: "L1PSRAM"}],
49
50 ['l1DMode',{desc:"L1D Cache",
51 map : [["0k",0x0000],
52 ["4k",0x1000],
53 ["8k",0x2000],
54 ["16k",0x4000],
55 ["32k",0x8000]],
56 defaultValue: "0k",
57 memorySection: "L1DSRAM"}],
58
59 ['l2Mode',{desc:"L2 Cache",
60 map : [["0k",0x0000],
61 ["32k",0x8000],
62 ["64k",0x10000]],
63 defaultValue: "0k",
64 memorySection: "IRAM"}],
65
66 ];
67
68 instance:
69 override config int minProgUnitSize = 1;
70 override config int minDataUnitSize = 1;
71 override config int dataWordSize = 4;
72
73 override config string cpuCore = "64x+";
74 override config string isa = "64P";
75
76 config xdc.platform.IPlatform.Memory memMap[string] = [
77 ["IRAM", {
78 comment: "Internal 96KB L2 UMAP0 memory",
79 name: "IRAM",
80 base: 0x107F8000,
81 len: 0x00018000,
82 space: "code/data",
83 access: "RWX"
84 }],
85
86 ["L1PSRAM", {
87 comment: "Internal 32KB L1 program memory",
88 name: "L1PSRAM",
89 base: 0x10E00000,
90 len: 0x00008000,
91 space: "code",
92 access: "RWX"
93 }],
94
95 ["L1DSRAM", {
96 comment: "Internal 80KB L1 data memory",
97 name: "L1DSRAM",
98 base: 0x10F04000,
99 len: 0x00014000,
100 space: "data",
101 access: "RW"
102 }],
103 ];
104 };
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108