1    /*
     2     *  Copyright 2009 by Texas Instruments Incorporated.
     3     *
     4     *  All rights reserved. Property of Texas Instruments Incorporated.
     5     *  Restricted rights to use, duplicate or disclose this code are
     6     *  granted through contract.
     7     *
     8     */
     9    
    10    /*
    11     *  ======== IHimalaya.xdc ========
    12     *
    13     */
    14    package ti.catalog.c6000;
    15    
    16    /*!
    17     *  ======== IHimalaya ========
    18     *  An interface implemented by all Himalaya devices
    19     *
    20     *  This interface is defined to factor common data about all Himalaya devices
    21     *  into a single place; they are all the same from the configuration point of
    22     *  view.
    23     */
    24    metaonly interface IHimalaya inherits ti.catalog.ICpuDataSheet
    25    {
    26    
    27        config long cacheSizeL1[string] = [
    28            ["0k",  0x0000],
    29            ["4k",  0x1000],
    30            ["8k",  0x2000],
    31            ["16k", 0x4000],
    32            ["32k", 0x8000],
    33        ];
    34    
    35        config long cacheSizeL2[string] = [
    36            ["0k",   0x00000],
    37            ["32k",  0x08000],
    38            ["64k",  0x10000],
    39            ["128k", 0x20000],
    40            ["256k", 0x40000]
    41        ];
    42    
    43        readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    44                 ['l1PMode',{desc:"L1P Cache",
    45                             map : [["0k",0x0000],
    46                                    ["4k",0x1000],
    47                                    ["8k",0x2000],
    48                                    ["16k",0x4000],
    49                                    ["32k",0x8000]],
    50                             defaultValue: "0k",
    51                             memorySection: "L1PSRAM"}],
    52             
    53                     ['l1DMode',{desc:"L1D Cache",
    54                             map : [["0k",0x0000],
    55                                    ["4k",0x1000],
    56                                    ["8k",0x2000],
    57                                    ["16k",0x4000],
    58                                    ["32k",0x8000]],
    59                             defaultValue: "0k",
    60                             memorySection: "L1DSRAM"}],
    61                         
    62                 ['l2Mode',{desc:"L2 Cache",
    63                             map : [["0k",0x0000],
    64                                    ["32k",0x8000],
    65                                    ["64k",0x10000],
    66                                    ["128k", 0x20000],
    67                                ["256k", 0x40000]],
    68                             defaultValue: "0k",
    69                             memorySection: "IRAM"}], 
    70    
    71        ];  
    72    
    73    instance:
    74    
    75        override config string   cpuCore         = "64x+";
    76        override config string   isa = "64P";
    77        override config string   cpuCoreRevision = "1.0";
    78    
    79        override config int     minProgUnitSize = 1;
    80        override config int     minDataUnitSize = 1;    
    81        override config int     dataWordSize    = 4;
    82    
    83        /*!
    84         *  ======== memMap ========
    85         *  The default memory map for this device
    86         */
    87        config xdc.platform.IPlatform.Memory memMap[string]  = [
    88            ["IRAM", {
    89                comment:    "Internal 2MB UMAP0 memory",
    90                name:       "IRAM",
    91                base:       0x800000,
    92                len:        0x200000,
    93                space:      "code/data",
    94                access:     "RWX"
    95            }],
    96    
    97            ["L1PSRAM", {
    98                comment:    "Internal 32KB RAM/CACHE L1 program memory",
    99                name:       "L1PSRAM",
   100                base:       0xE00000,
   101                len:        0x008000,
   102                space:      "code",
   103                access:     "RWX"
   104            }],
   105    
   106            ["L1DSRAM", {
   107                comment:    "Internal 32KB RAM/CACHE L1 data memory",
   108                name:       "L1DSRAM",
   109                base:       0xF00000,
   110                len:        0x008000,
   111                space:      "data",
   112                access:     "RW"
   113            }],
   114    
   115        ];
   116    };
   117    /*
   118     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:51; /db/ztree/library/trees/platform-k10x/src/
   119     */
   120