1 /*
2 * Copyright 2009 by Texas Instruments Incorporated.
3 *
4 * All rights reserved. Property of Texas Instruments Incorporated.
5 * Restricted rights to use, duplicate or disclose this code are
6 * granted through contract.
7 *
8 */
9
10 /*
11 * ======== IDaVinci.xdc ========
12 *
13 */
14 package ti.catalog.c6000;
15
16 /*!
17 * ======== IDaVinci ========
18 * An interface implemented by all DaVinci devices
19 *
20 * This interface is defined to factor common data about all DaVinci devices
21 * into a single place; they are all the same from the configuration point of
22 * view.
23 */
24 metaonly interface IDaVinci inherits ti.catalog.ICpuDataSheet
25 {
26 config long cacheSizeL1[string] = [
27 ["0k", 0x0000],
28 ["4k", 0x1000],
29 ["8k", 0x2000],
30 ["16k", 0x4000],
31 ["32k", 0x8000],
32 ];
33
34 config long cacheSizeL2[string] = [
35 ["0k", 0x00000],
36 ["32k", 0x08000],
37 ["64k", 0x10000]
38 ];
39
40 readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] = [
41 ['l1PMode',{desc:"L1P Cache",
42 map : [["0k",0x0000],
43 ["4k",0x1000],
44 ["8k",0x2000],
45 ["16k",0x4000],
46 ["32k",0x8000]],
47 defaultValue: "0k",
48 memorySection: "L1PSRAM"}],
49
50 ['l1DMode',{desc:"L1D Cache",
51 map : [["0k",0x0000],
52 ["4k",0x1000],
53 ["8k",0x2000],
54 ["16k",0x4000],
55 ["32k",0x8000]],
56 defaultValue: "0k",
57 memorySection: "L1DSRAM"}],
58
59 ['l2Mode',{desc:"L2 Cache",
60 map : [["0k",0x0000],
61 ["32k",0x8000],
62 ["64k",0x10000]],
63 defaultValue: "0k",
64 memorySection: "IRAM"}],
65
66 ];
67
68 instance:
69
70 override config string cpuCore = "64x+";
71 override config string isa = "64P";
72 override config string cpuCoreRevision = "1.0";
73
74 override config int minProgUnitSize = 1;
75 override config int minDataUnitSize = 1;
76 override config int dataWordSize = 4;
77
78 /*!
79 * ======== memMap ========
80 * The default memory map for this device
81 */
82 config xdc.platform.IPlatform.Memory memMap[string] = [
83 ["IRAM", {
84 comment: "Internal 64KB UMAP0 memory",
85 name: "IRAM",
86 base: 0x11800000,
87 len: 0x00010000,
88 space: "code/data",
89 access: "RWX"
90 }],
91
92 ["L1PSRAM", {
93 comment: "Internal 32KB RAM/CACHE L1 program memory",
94 name: "L1PSRAM",
95 base: 0x11E08000,
96 len: 0x00008000,
97 space: "code",
98 access: "RWX"
99 }],
100
101 ["L1DSRAM", {
102 comment: "Internal 80KB RAM/CACHE L1 data memory",
103 name: "L1DSRAM",
104 base: 0x11F04000,
105 len: 0x00014000,
106 space: "data",
107 access: "RW"
108 }],
109
110 ["ARM_RAM", {
111 comment: "Internal ARM RAM memory",
112 name: "ARM_RAM",
113 base: 0x10008000,
114 len: 0x00004000,
115 space: "data",
116 access: "RW"
117 }],
118 ];
119 };
120 /*
121 * @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:51; /db/ztree/library/trees/platform-k10x/src/
122 */
123