1    /*
     2     *  Copyright 2009 by Texas Instruments Incorporated.
     3     *
     4     *  All rights reserved. Property of Texas Instruments Incorporated.
     5     *  Restricted rights to use, duplicate or disclose this code are
     6     *  granted through contract.
     7     *
     8     */
     9    
    10    /*
    11     *  ======== ICacheInfo.xdc ========
    12     */
    13    
    14    
    15    package ti.catalog.c6000;
    16    
    17    metaonly interface ICacheInfo {
    18        /*!
    19         *  ======== CacheDesc ========
    20         *  Structure used by ICpuDataSheet implementations to
    21         *  specify device cache modes. 
    22         *   
    23         *  A map is defined by an ICpuDataSheet implementation
    24         *  that maps a string denoting a device register setting
    25         *  to a CacheDesc structure. This maybe used in implementing
    26         *  the 'getMemoryMap' method. An example of such a map is shown below :
    27         *
    28         *   readonly config ti.catalog.c6000.ICacheInfo.CacheDesc cacheMap[string] =  [
    29             *    ['l1PMode',{desc:"L1P Cache",
    30             *                map : [["0k",0x0000],
    31             *                       ["4k",0x1000],
    32             *                       ["8k",0x2000],
    33             *                       ["16k",0x4000],
    34             *                       ["32k",0x8000]],
    35             *                defaultValue: "0k",
    36             *                memorySection: "L1PSRAM"}],
    37             *
    38             *        ['l1DMode',{desc:"L1D Cache",
    39             *                map : [["0k",0x0000],
    40             *                       ["4k",0x1000],
    41             *                       ["8k",0x2000],
    42             *                       ["16k",0x4000],
    43             *                       ["32k",0x8000]],
    44             *                defaultValue: "0k",
    45             *                memorySection: "L1DSRAM"}],
    46             *            
    47             *    ['l2Mode',{desc:"L2 Cache",
    48             *                map : [["0k",0x0000],
    49             *                       ["32k",0x8000],
    50             *                       ["64k",0x10000],
    51             *                       ["128k",0x20000],
    52             *                       ["256k",0x40000]],
    53             *                defaultValue: "0k",
    54             *                memorySection: "IRAM"}], 
    55         *
    56         *   ];
    57         *
    58         *  @_nodoc
    59         */
    60        struct CacheDesc {
    61            string desc;          /*! String describing the register setting */
    62            unsigned map[string]; /*! A hash of cache modes to cache size*/
    63            string defaultValue;  /*! The default cache mode for the device */
    64            string memorySection; /*! The associated memory section */
    65        };
    66    
    67    
    68    }
    69    /*
    70     *  @(#) ti.catalog.c6000; 1, 0, 0, 0,173; 6-4-2009 14:07:51; /db/ztree/library/trees/platform-k10x/src/
    71     */
    72