1    /*
     2     *  Copyright 2009 by Texas Instruments Incorporated.
     3     *
     4     *  All rights reserved. Property of Texas Instruments Incorporated.
     5     *  Restricted rights to use, duplicate or disclose this code are
     6     *  granted through contract.
     7     *
     8     */
     9    
    10    /*
    11     *  ======== Boot.xdc ========
    12     *
    13     */
    14    
    15    package ti.catalog.c2800.init;
    16    
    17    import xdc.rov.ViewInfo;
    18    
    19    @Template("./Boot.xdt")
    20    
    21    metaonly module Boot
    22    {
    23        metaonly struct ModuleView {
    24            Bool         disableWatchdog;
    25            Bool         configurePll;
    26            UInt         pllcrDIV;
    27            UInt         pllstsDIVSEL;
    28        }
    29    
    30        @Facet
    31        metaonly config ViewInfo.Instance rovViewInfo = 
    32            ViewInfo.create({
    33                viewMap: [
    34                [
    35                    'Module',
    36                    {
    37                        type: ViewInfo.MODULE,
    38                        viewInitFxn: 'viewInitModule',
    39                        structName: 'ModuleView'
    40                    }
    41                ],
    42                ]
    43            });
    44        
    45        /*! 
    46         *  Watchdog disable flag, default is false.
    47         *
    48         *  Set to true to automatically disabled the watchdog timer.
    49         */
    50        config Bool disableWatchdog = false;
    51    
    52        /*! 
    53         *  PLL configuration flag, default is false.
    54         *
    55         *  Set to true to automatically configure the PLL.
    56         */
    57        config Bool configurePll = false;
    58    
    59        /*! 
    60         *  PLLCR[DIV] value. Default is 10.
    61         *
    62         *  This is the actual value written to the DIV bits in 
    63         *  the PLL Control Register (PLLCR)
    64         */
    65        config UInt pllcrDIV = 10;
    66    
    67        /*! 
    68         *  PLLSTS[DIVSEL] value. Default is 2.
    69         *
    70         *  This is the actual value written to the DIVSEL bits in 
    71         *  the PLL Status Register (PLLSTS)
    72         */
    73        config UInt pllstsDIVSEL = 2;
    74    
    75        /*! 
    76         *  Code section that Boot module code is in.
    77         *
    78         *  To place this section into a memory segment yourself, add the 
    79         *  following to you configuration file: 
    80         *
    81         *  @p(code)
    82         *  Program.sectMap[Boot.bootCodeSection] = new Program.SectionSpec();
    83         *  Program.sectMap[Boot.bootCodeSection].loadSegment = "yourBootCodeMemorySegment";
    84         *  @p
    85         *
    86         *  or to place the code at a specific adress: 
    87         *
    88         *  @p(code)
    89         *  Program.sectMap[Boot.bootCodeSection] = new Program.SectionSpec();
    90         *  Program.sectMap[Boot.bootCodeSection].loadAdress = yourBootCodeAddress;
    91         *  @p
    92         *
    93         */
    94        readonly config String bootCodeSection = ".bootCodeSection";
    95        
    96        /*!
    97         * @_nodoc
    98         * Configure the external memory interface (XINTF) for the eZdsp283xx
    99         * devices.
   100         *
   101         * This will eventually be replaced by a more generic API for configuring
   102         * the XINTF on any 28x device.
   103         */
   104        config Bool enableEzdspXintfConfig = false;
   105    };
   106    /*
   107     *  @(#) ti.catalog.c2800.init; 1, 0, 0,24; 6-4-2009 14:07:27; /db/ztree/library/trees/platform-k10x/src/
   108     */
   109