1    /*
     2     * Copyright (c) 2012-2014 Texas Instruments Incorporated - https://www.ti.com
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    /*
    33     *  ======== InterruptIpu.xdc ========
    34     *
    35     */
    36    
    37    import ti.sdo.utils.MultiProc;
    38    
    39    /*!
    40     *  ======== InterruptIpu ========
    41     *  IPU interrupt manager
    42     */
    43    module InterruptIpu inherits ti.sdo.ipc.notifyDrivers.IInterrupt
    44    {
    45        /*!
    46         *  Maximum number of cores
    47         *
    48         *  @_nodoc
    49         */
    50        const UInt8 NUM_CORES = 11;
    51    
    52        /*!
    53         *  Maximum number of EVE cores
    54         *
    55         *  Although your device may have fewer EVE cores, `NUM_EVES` represents
    56         *  the maximum number of EVEs that may be present on a Vayu system.
    57         */
    58        const UInt8 NUM_EVES = 4;
    59    
    60        /*!
    61         *  Maximum number of IPU cores
    62         *
    63         *  @_nodoc
    64         */
    65        const UInt8 NUM_Ipu_CORES = 2;
    66    
    67        /*!
    68         *  Number of internal EVE mailboxes
    69         *
    70         *  Each EVE core has 3 mailboxes.
    71         *
    72         *  Although your device may have fewer EVE cores, `NUM_EVE_MBX` represents
    73         *  the maximum number of EVE mailboxes (including all EVE cores) that may
    74         *  be present.
    75         */
    76        const UInt8 NUM_EVE_MBX = NUM_EVES * 3;
    77    
    78        /*!
    79         *  Number of System mailboxes used by IPC
    80         *
    81         *  This represents the number of System mailboxes used by IPC.  IPC
    82         *  currently uses system mailboxes 5, 6, 7 and 8.
    83         */
    84        const UInt8 NUM_SYS_MBX = 4;
    85    
    86        /*!
    87         *  Base address for the mailbox subsystems
    88         *
    89         *  The `mailboxBaseAddr` array indicates the virtual addresses through
    90         *  which IPC will access various mailboxes.  The specific mailbox addresses
    91         *  each array index maps to follows:
    92         *  @p(blist)
    93         *    - 0  - EVE1 MBX0
    94         *    - 1  - EVE1 MBX1
    95         *    - 2  - EVE1 MBX2 (unused, do not assign)
    96         *    - 3  - EVE2 MBX0
    97         *    - 4  - EVE2 MBX1
    98         *    - 5  - EVE2 MBX2 (unused, do not assign)
    99         *    - 6  - EVE3 MBX0
   100         *    - 7  - EVE3 MBX1
   101         *    - 8  - EVE1 MBX2 (unused, do not assign)
   102         *    - 9  - EVE4 MBX0
   103         *    - 10 - EVE4 MBX1
   104         *    - 11 - EVE1 MBX2 (unused, do not assign)
   105         *    - 12  - System Mailbox 5
   106         *    - 13  - System Mailbox 6
   107         *    - 14  - System Mailbox 7
   108         *    - 15  - System Mailbox 8
   109         *  @p
   110         *
   111         *  Note that these mailboxes are not accessible at their physical
   112         *  addresses (in the 0x4XXX_XXXX range).  So default virtual addresses
   113         *  through which these mailboxes will be accessed are assigned in the
   114         *  0x6XXX_XXXX range.  Users must ensure these virtual addresses are
   115         *  correctly mapped to the 0x4XXX_XXXX-based phys addrs in each IPUs AMMU.
   116         */
   117        config UInt32 mailboxBaseAddr[NUM_EVE_MBX + NUM_SYS_MBX];
   118    
   119        /*!
   120         * Mailbox table for storing encoded Base Address, mailbox user Id,
   121         * and sub-mailbox index.
   122         *
   123         *  @_nodoc
   124         */
   125        config UInt32 mailboxTable[NUM_CORES * NUM_CORES];
   126    
   127        /*!
   128         *  Base address for the Ducati CTRL register
   129         */
   130        config UInt32 ducatiCtrlBaseAddr = 0x40001000;
   131    
   132        /*!
   133         *  Processor Id table
   134         *
   135         *  @_nodoc
   136         */
   137        config UInt32 procIdTable[NUM_CORES];
   138    
   139    internal:
   140    
   141        /*! Statically retrieve procIds to avoid doing this at runtime */
   142        config UInt eve1ProcId     = MultiProc.INVALIDID;
   143        config UInt eve2ProcId     = MultiProc.INVALIDID;
   144        config UInt eve3ProcId     = MultiProc.INVALIDID;
   145        config UInt eve4ProcId     = MultiProc.INVALIDID;
   146        config UInt dsp1ProcId     = MultiProc.INVALIDID;
   147        config UInt dsp2ProcId     = MultiProc.INVALIDID;
   148        config UInt ipu1_0ProcId   = MultiProc.INVALIDID;
   149        config UInt ipu2_0ProcId   = MultiProc.INVALIDID;
   150        config UInt hostProcId     = MultiProc.INVALIDID;
   151        config UInt ipu1_1ProcId   = MultiProc.INVALIDID;
   152        config UInt ipu2_1ProcId   = MultiProc.INVALIDID;
   153    
   154        /*! Function table */
   155        struct FxnTable {
   156            Fxn    func;
   157            UArg   arg;
   158        }
   159    
   160        /*! Stub to be plugged for inter-ducati interrupts */
   161        Void intShmDucatiStub(UArg arg);
   162    
   163        /*! Stub to be plugged for intra-ducati interrupts */
   164        Void intShmMbxStub(UInt16 idx);
   165    
   166        struct Module_State {
   167            /*
   168             * Create a function table of length 8 (Total number of cores in the
   169             * System) for each M4 core.
   170             */
   171            FxnTable   fxnTable[NUM_CORES];
   172        };
   173    }