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gatempapp_rsc_table_vayu_dsp.h
Go to the documentation of this file.
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/*
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* Copyright (c) 2013-2014, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ======== gatempapp_rsc_table_vayu_dsp.h ========
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*
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* Define the resource table entries for all DSP cores. This will be
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* incorporated into corresponding base images, and used by the remoteproc
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* on the host-side to allocated/reserve resources.
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*
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*/
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#ifndef _GATEMPAPP_RSC_TABLE_VAYU_DSP_H_
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#define _GATEMPAPP_RSC_TABLE_VAYU_DSP_H_
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#include <ti/ipc/remoteproc/rsc_types.h>
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/* DSP Memory Map */
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#define L4_DRA7XX_BASE 0x4A000000
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#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
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#define DSP_PERIPHERAL_L4CFG 0x4A000000
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#define L4_PERIPHERAL_L4PER1 0x48000000
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#define DSP_PERIPHERAL_L4PER1 0x48000000
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#define L4_PERIPHERAL_L4PER2 0x48400000
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#define DSP_PERIPHERAL_L4PER2 0x48400000
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#define L4_PERIPHERAL_L4PER3 0x48800000
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#define DSP_PERIPHERAL_L4PER3 0x48800000
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#define L4_PERIPHERAL_L4EMU 0x54000000
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#define DSP_PERIPHERAL_L4EMU 0x54000000
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#define L3_PERIPHERAL_DMM 0x4E000000
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#define DSP_PERIPHERAL_DMM 0x4E000000
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#define L3_PERIPHERAL_ISS 0x52000000
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#define DSP_PERIPHERAL_ISS 0x52000000
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#define L3_TILER_MODE_0_1 0x60000000
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#define DSP_TILER_MODE_0_1 0x60000000
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#define L3_TILER_MODE_2 0x70000000
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#define DSP_TILER_MODE_2 0x70000000
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#define L3_TILER_MODE_3 0x78000000
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#define DSP_TILER_MODE_3 0x78000000
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#define DSP_MEM_TEXT 0x95000000
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/* Co-locate alongside TILER region for easier flushing */
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#define DSP_MEM_IOBUFS 0x80000000
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#define DSP_MEM_DATA 0x95100000
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#define DSP_MEM_HEAP 0x95200000
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//0x85900000
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#define DSP_SR0_VIRT 0xBFC00000
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#define DSP_SR0 0xBFC00000
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#define DSP_MEM_IPC_DATA 0x9F000000
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#define DSP_MEM_IPC_VRING 0xA0000000
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#define DSP_MEM_RPMSG_VRING0 0xA0000000
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#define DSP_MEM_RPMSG_VRING1 0xA0004000
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#define DSP_MEM_VRING_BUFS0 0xA0040000
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#define DSP_MEM_VRING_BUFS1 0xA0080000
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#define DSP_MEM_IPC_VRING_SIZE SZ_1M
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#define DSP_MEM_IPC_DATA_SIZE SZ_1M
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#define DSP_MEM_TEXT_SIZE SZ_1M
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#define DSP_MEM_DATA_SIZE SZ_1M
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#define DSP_MEM_HEAP_SIZE (SZ_1M * 3)
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#define DSP_MEM_IOBUFS_SIZE (SZ_1M * 89)
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#define DSP_SR0_SIZE (SZ_1M * 1)
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/*
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* Assign fixed RAM addresses to facilitate a fixed MMU table.
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*/
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/* This address is derived from current IPU & ION carveouts */
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#define PHYS_MEM_IPC_VRING 0x99000000
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/* Need to be identical to that of IPU */
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#define PHYS_MEM_IOBUFS 0xBA300000
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/*
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* Sizes of the virtqueues (expressed in number of buffers supported,
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* and must be power of 2)
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*/
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#define DSP_RPMSG_VQ0_SIZE 256
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#define DSP_RPMSG_VQ1_SIZE 256
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/* flip up bits whose indices represent features we support */
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#define RPMSG_DSP_C0_FEATURES 1
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struct
my_resource_table
{
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struct
resource_table
base
;
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UInt32
offset
[19];
/* Should match 'num' in actual definition */
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/* rpmsg vdev entry */
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struct
fw_rsc_vdev
rpmsg_vdev
;
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struct
fw_rsc_vdev_vring
rpmsg_vring0
;
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struct
fw_rsc_vdev_vring
rpmsg_vring1
;
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/* text carveout entry */
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struct
fw_rsc_carveout
text_cout
;
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/* data carveout entry */
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struct
fw_rsc_carveout
data_cout
;
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/* heap carveout entry */
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struct
fw_rsc_carveout
heap_cout
;
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/* ipcdata carveout entry */
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struct
fw_rsc_carveout
ipcdata_cout
;
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/* trace entry */
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struct
fw_rsc_trace
trace
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem0
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem1
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem2
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem3
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem4
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem5
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem6
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem7
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem8
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem9
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem10
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem11
;
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/* devmem entry */
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struct
fw_rsc_devmem
devmem12
;
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};
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extern
char
ti_trace_SysMin_Module_State_0_outbuf__A
;
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#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
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#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
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#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
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struct
my_resource_table
ti_ipc_remoteproc_ResourceTable
= {
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1,
/* we're the first version that implements this */
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19,
/* number of entries in the table */
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0, 0,
/* reserved, must be zero */
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/* offsets to entries */
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{
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offsetof(
struct
my_resource_table
,
rpmsg_vdev
),
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offsetof(
struct
my_resource_table
,
text_cout
),
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offsetof(
struct
my_resource_table
,
data_cout
),
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offsetof(
struct
my_resource_table
,
heap_cout
),
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offsetof(
struct
my_resource_table
,
ipcdata_cout
),
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offsetof(
struct
my_resource_table
,
trace
),
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offsetof(
struct
my_resource_table
,
devmem0
),
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offsetof(
struct
my_resource_table
,
devmem1
),
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offsetof(
struct
my_resource_table
,
devmem2
),
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offsetof(
struct
my_resource_table
,
devmem3
),
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offsetof(
struct
my_resource_table
,
devmem4
),
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offsetof(
struct
my_resource_table
,
devmem5
),
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offsetof(
struct
my_resource_table
,
devmem6
),
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offsetof(
struct
my_resource_table
,
devmem7
),
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offsetof(
struct
my_resource_table
,
devmem8
),
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offsetof(
struct
my_resource_table
,
devmem9
),
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offsetof(
struct
my_resource_table
,
devmem10
),
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offsetof(
struct
my_resource_table
,
devmem11
),
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offsetof(
struct
my_resource_table
,
devmem12
),
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},
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/* rpmsg vdev entry */
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{
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TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
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RPMSG_DSP_C0_FEATURES
, 0, 0, 0, 2, { 0, 0 },
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/* no config data */
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},
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/* the two vrings */
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{
DSP_MEM_RPMSG_VRING0
, 4096,
DSP_RPMSG_VQ0_SIZE
, 1, 0 },
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{
DSP_MEM_RPMSG_VRING1
, 4096,
DSP_RPMSG_VQ1_SIZE
, 2, 0 },
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{
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TYPE_CARVEOUT,
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DSP_MEM_TEXT
, 0,
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DSP_MEM_TEXT_SIZE
, 0, 0,
"DSP_MEM_TEXT"
,
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},
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{
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TYPE_CARVEOUT,
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DSP_MEM_DATA
, 0,
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DSP_MEM_DATA_SIZE
, 0, 0,
"DSP_MEM_DATA"
,
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},
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{
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TYPE_CARVEOUT,
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DSP_MEM_HEAP
, 0,
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DSP_MEM_HEAP_SIZE
, 0, 0,
"DSP_MEM_HEAP"
,
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},
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{
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TYPE_CARVEOUT,
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DSP_MEM_IPC_DATA
, 0,
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DSP_MEM_IPC_DATA_SIZE
, 0, 0,
"DSP_MEM_IPC_DATA"
,
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},
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{
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TYPE_TRACE,
TRACEBUFADDR
, 0x8000, 0,
"trace:dsp"
,
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},
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{
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TYPE_DEVMEM,
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DSP_MEM_IPC_VRING
,
PHYS_MEM_IPC_VRING
,
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DSP_MEM_IPC_VRING_SIZE
, 0, 0,
"DSP_MEM_IPC_VRING"
,
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},
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{
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TYPE_DEVMEM,
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DSP_MEM_IOBUFS
,
PHYS_MEM_IOBUFS
,
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DSP_MEM_IOBUFS_SIZE
, 0, 0,
"DSP_MEM_IOBUFS"
,
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},
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{
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TYPE_DEVMEM,
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DSP_TILER_MODE_0_1
,
L3_TILER_MODE_0_1
,
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SZ_256M, 0, 0,
"DSP_TILER_MODE_0_1"
,
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},
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{
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TYPE_DEVMEM,
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DSP_TILER_MODE_2
,
L3_TILER_MODE_2
,
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SZ_128M, 0, 0,
"DSP_TILER_MODE_2"
,
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},
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{
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TYPE_DEVMEM,
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DSP_TILER_MODE_3
,
L3_TILER_MODE_3
,
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SZ_128M, 0, 0,
"DSP_TILER_MODE_3"
,
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},
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{
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TYPE_DEVMEM,
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DSP_PERIPHERAL_L4CFG
,
L4_PERIPHERAL_L4CFG
,
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SZ_16M, 0, 0,
"DSP_PERIPHERAL_L4CFG"
,
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},
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{
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TYPE_DEVMEM,
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DSP_PERIPHERAL_L4PER1
,
L4_PERIPHERAL_L4PER1
,
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SZ_2M, 0, 0,
"DSP_PERIPHERAL_L4PER1"
,
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},
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{
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TYPE_DEVMEM,
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DSP_PERIPHERAL_L4PER2
,
L4_PERIPHERAL_L4PER2
,
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SZ_4M, 0, 0,
"DSP_PERIPHERAL_L4PER2"
,
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},
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{
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TYPE_DEVMEM,
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DSP_PERIPHERAL_L4PER3
,
L4_PERIPHERAL_L4PER3
,
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SZ_8M, 0, 0,
"DSP_PERIPHERAL_L4PER3"
,
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},
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{
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TYPE_DEVMEM,
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DSP_PERIPHERAL_L4EMU
,
L4_PERIPHERAL_L4EMU
,
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SZ_16M, 0, 0,
"DSP_PERIPHERAL_L4EMU"
,
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},
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{
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TYPE_DEVMEM,
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DSP_PERIPHERAL_DMM
,
L3_PERIPHERAL_DMM
,
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SZ_1M, 0, 0,
"DSP_PERIPHERAL_DMM"
,
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},
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{
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TYPE_DEVMEM,
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DSP_PERIPHERAL_ISS
,
L3_PERIPHERAL_ISS
,
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SZ_256K, 0, 0,
"DSP_PERIPHERAL_ISS"
,
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},
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{
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TYPE_DEVMEM,
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DSP_SR0_VIRT
,
DSP_SR0
,
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DSP_SR0_SIZE
, 0, 0,
"DSP_SR0"
,
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},
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};
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#endif
/* _GATEMPAPP_RSC_TABLE_VAYU_DSP_H_ */
Copyright 2014, Texas Instruments Incorporated