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    32    /*
    33     *  ======== IpcMgr.xdc ========
    34     */
    35    
    36    import xdc.runtime.Assert;
    37    import xdc.runtime.Error;
    38    
    39    /*!
    40     *  ======== IpcMgr ========
    41     *  IPC Manager
    42     *
    43     *  This modules is used only for F28M35x devices.  Users can statically
    44     *  configure which shared memory segments to enable, the owner processor
    45     *  and the owner's write access.  This module used for specifying shared
    46     *  memory for IPC between the M3 and C28 processors.
    47     *  
    48     *  There are no API's that need to be called.  The necessary drivers for
    49     *  IPC are all created within this module's startup function.  The shared
    50     *  memory is also programmed within this function.  There is handshake
    51     *  between the processors.  The M3 releases the C28 and both processors
    52     *  will synchronize at this point.
    53     *
    54     *  The {@link #readAddr} must point to shared memory which is writeable
    55     *  by the remote core while the {@link #writeAddr} must point to shared
    56     *  memory which is writeable by the local core.  The {@link #readAddr}
    57     *  and {@link #writeAddr} pointers must point to different shared memory
    58     *  blocks.  Memory addresses must be specified in the local core's
    59     *  memory space.
    60     *  
    61     *  For example on the M3:
    62     *  @p(code)
    63     *  var IpcMgr = xdc.useModule('ti.sdo.ipc.family.f28m35x.IpcMgr');
    64     *  IpcMgr.readAddr  = 0x20016000;
    65     *  IpcMgr.writeAddr = 0x20014000;
    66     *  IpcMgr.sharedMemoryOwnerMask = 0x80;
    67     *  @p
    68     *
    69     *  On the C28:
    70     *  @p(code)
    71     *  var IpcMgr = xdc.useModule('ti.sdo.ipc.family.f28m35x.IpcMgr');
    72     *  IpcMgr.readAddr  = 0x12000;
    73     *  IpcMgr.writeAddr = 0x13000;
    74     *  @p
    75     */
    76    
    77    @ModuleStartup 
    78    
    79    module IpcMgr
    80    {
    81        /*!
    82         *  This value is used for setting {@link #sharedMemoryAccess}.
    83         *  If value specified, fetch is not allowed by owner.
    84         */
    85        const Bits32 NOFETCH    = 1;
    86        
    87        /*!
    88         *  This value is used for setting {@link #sharedMemoryAccess}.
    89         *  If value specified, DMA writes are not allowed by owner.
    90         */
    91        const Bits32 NODMAWRITE = 2;
    92        
    93        /*!
    94         *  This value is used for setting {@link #sharedMemoryAccess}.
    95         *  If value specified, CPU writes are not allowed by owner.
    96         */
    97        const Bits32 NOCPUWRITE = 4;
    98    
    99        /*
   100         *************************************************************************
   101         *                       Generic Errors/Asserts
   102         *************************************************************************
   103         */
   104    
   105        /*!
   106         *  ======== A_internal ========
   107         *  Assert raised when an internal error is encountered
   108         */
   109        config Assert.Id A_internal = {
   110            msg: "A_internal: An internal error has occurred"
   111        };
   112    
   113        /*!
   114         *  ======== A_invParam ========
   115         *  Assert raised when a parameter is invalid
   116         */
   117        config Assert.Id A_invParam  = {
   118            msg: "A_invParam: Invalid configuration parameter supplied"
   119        };
   120    
   121        /*!
   122         *  ======== A_notEnoughMemory ========
   123         *  Assert raised when there's not enough memory for creating instances.
   124         */
   125        config Assert.Id A_notEnoughMemory  = {
   126            msg: "A_notEnoughMemory: There is not enough memory for operation"
   127        };
   128    
   129        /*!
   130         *  ======== A_nullArgument ========
   131         *  Assert raised when a required argument is null
   132         */
   133        config Assert.Id A_nullArgument  = {
   134            msg: "A_nullArgument: Required argument is null"
   135        };
   136    
   137        /*!
   138         *  ======== E_internal ========
   139         *  Error raised when an internal error occured
   140         */
   141        config Error.Id E_internal  = {
   142            msg: "E_internal: An internal error occurred"
   143        };
   144    
   145        /*
   146         *************************************************************************
   147         *                       Module-wide Config Parameters
   148         *************************************************************************
   149         */
   150         
   151        /*!
   152         *  ======== genLinkerSections ========
   153         *  For generating or not generating the linker sections
   154         *
   155         *  By default this is set to 'true' so the following linker sections
   156         *  are generated for the amount of memory used for IPC. For the
   157         *  read address - "ti.sdo.ipc.family.f28m35x.IpcMgr.readSect" and for
   158         *  the write address - "ti.sdo.ipc.family.f28m35x.IpcMgr.writeSect".
   159         *  To disable generation, set this to 'false'.
   160         */
   161        metaonly config Bool genLinkerSections = true;
   162     
   163        /*!
   164         *  ======== ipcSetFlag ========
   165         *  The IPC set flag used for generating IPC interrupt
   166         *
   167         *  Only a value of 0, 1, 2, or 3 are valid since only those flags
   168         *  have an interrupt associated with them. This value must be the
   169         *  same on both processors.
   170         */
   171        config UInt32 ipcSetFlag = 3;
   172    
   173        /*!
   174         *  ======== messageQSize ========
   175         *  The largest MessageQ size (in bytes) supported by the transport
   176         *
   177         *  This value must be large enough to handle the largest message.
   178         *  The size must be specified in bytes.
   179         */
   180        config UInt32 messageQSize = 128;
   181    
   182        /*!
   183         *  ======== messageQEventId ========
   184         *  Notify event ID for MessageQ transport.
   185         */
   186        config UInt16 messageQEventId = 2;
   187        
   188        /*!
   189         *  ======== nameServerEventId ========
   190         *  Notify event ID for NameServer.
   191         */
   192        config UInt16 nameServerEventId = 4;
   193    
   194        /*!
   195         *  ======== numNotifyMsgs ========
   196         *  The number of messages for the Notify driver's circular buffer
   197         *
   198         *  This is use to determine the size of the put and get buffers.
   199         *  This value must be a power of 2.  A value of 'N' allows 'N-1'
   200         *  outstanding notifications.
   201         */
   202        config UInt32 numNotifyMsgs = 32;
   203        
   204        /*!
   205         *  ======== numMessageQMsgs ========
   206         *  The number of messages for the MessageQ transport's circular buffer
   207         *
   208         *  This is use to determine the size of the put and get buffers.
   209         *  This value must be a power of 2.  A value of 'N' allows 'N-1'
   210         *  outstanding notifications.
   211         */
   212        config UInt32 numMessageQMsgs = 4;
   213    
   214        /*!
   215         *  ======== sharedMemoryEnable ========
   216         *  Shared RAM memory configuration.
   217         *
   218         *  This parameter is only applicable to the M3 processor.  It is
   219         *  used for writing the MEMCNF register from the M3.
   220         *  By default, all shared RAM segments will be enabled at runtime.
   221         *  To disable a shared RAM segment, set the corresponding bit to 0.
   222         *  If any data is loaded to a shared RAM segment, the segment must
   223         *  be enabled prior to loading the program through other means.
   224         */
   225        config Bits32 sharedMemoryEnable = 0xffffffff;
   226        
   227        /*!
   228         *  ======== sharedMemoryOwnerMask ========
   229         *  Shared RAM owner select configuration.
   230         *
   231         *  This parameter is only applicable to the M3 processor.  It is
   232         *  used for writing the MSxMSEL register from the M3.
   233         *  By default, each value of each shared RAM select bit is '0'.
   234         *  This means the M3 is the owner and has write access based upon
   235         *  the sharedMemoryAccess bits.  Setting a '1' in any bit position
   236         *  makes the C28 the owner of that shared RAM segment.
   237         */
   238        config Bits32 sharedMemoryOwnerMask = 0;
   239    
   240        /*!
   241         *  ======== sharedMemoryAccess ========
   242         *  Shared RAM write configuration.
   243         *
   244         *  This parameter is only applicable to the M3 processor.  It is
   245         *  used for writing the MSxSRCR register from the M3.
   246         *  It determines the owner write access to each shared RAM segment.
   247         *  By default, the owner is allowed to fetch, DMA write, and CPU write.
   248         */
   249        config Bits32 sharedMemoryAccess[8];
   250        
   251        /*!
   252         *  ======== readAddr ========
   253         *  The base address of read-only shared memory.
   254         *
   255         *  The address must be specified in the local core's memory space.
   256         *  It must point to the same physical address as the writeAddr for
   257         *  the remote processor.
   258         */
   259        config Ptr readAddr;
   260    
   261        /*!
   262         *  ======== writeAddr ========
   263         *  The base address of read/write shared memory.
   264         *
   265         *  The address must be specified in the local core's memory space.
   266         *  It must point to the same physical address as the readAddr for
   267         *  the remote processor.
   268         */
   269        config Ptr writeAddr;
   270    
   271    internal:
   272    
   273        /* M3 control registers */
   274        const UInt32 MWRALLOW = 0x400FB980;
   275        const UInt32 MEMCNF  = 0x400FB930;
   276        const UInt32 MSxMSEL = 0x400FB210;
   277        const UInt32 MSxSRCR = 0x400FB220;
   278        const UInt32 C28RTESTINIT = 0x4920;
   279        const UInt32 C28RINITDONE = 0x4930;
   280        const UInt32 MTOCRTESTINIT = 0x400FB260;
   281        const UInt32 MTOCRINITDONE = 0x400FB288;
   282        
   283        /* the amount of shared memory used */
   284        config UInt32 sharedMemSizeUsed;
   285        
   286        /* initialize the MsgRams */
   287        Void init();
   288    
   289        /* function to create NotifyCirc driver instances */
   290        Int notifyCircAttach(UInt16 remoteProcId, Ptr writeAddr, Ptr readAddr);
   291    
   292        /* function to create NameServer remote instances */
   293        Int nameServerAttach(UInt16 remoteProcId, Ptr writeAddr, Ptr readAddr);
   294    
   295        /* function to create MessageQ transport instances */
   296        Int transportCircAttach(UInt16 remoteProcId, Ptr writeAddr, Ptr readAddr);
   297    }