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00048 #ifndef ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
00049 #define ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
00050
00053
00054 #ifdef __cplusplus
00055 extern "C" {
00056 #endif
00057
00058 #include <ti/xdais/xdas.h>
00059 #include <ti/xdais/ires_common.h>
00060
00064 #define IRES_EDMA3CHAN_PROTOCOLNAME "ti.sdo.fc.ires.edma3chan"
00065
00076 #define EDMA3CHAN_MODNAME "ti.sdo.fc.ires.edma3chan"
00077
00078
00079
00080
00081
00082
00083 #ifndef ti_sdo_fc_ires_NOPROTOCOLREV
00084
00089 static IRES_ProtocolRevision IRES_EDMA3CHAN_PROTOCOLREVISION = {1, 0, 0};
00090
00091 #endif
00092
00096 #define IRES_EDMA3CHAN_PROTOCOLREVISION_1_0_0 {1, 0, 0}
00097 #define IRES_EDMA3CHAN_SETPROTOCOLREVISION_1_0_0(rev) {(rev)->Major = 1; \
00098 (rev)->Source = 0; (rev)->Radius = 0;}
00099
00103 #define IRES_EDMA3CHAN_PROTOCOLREVISION_2_0_0 {2, 0, 0}
00104 #define IRES_EDMA3CHAN_SETPROTOCOLREVISION_2_0_0(rev) {(rev)->Major = 2; \
00105 (rev)->Source = 0; (rev)->Radius = 0;}
00106
00111 #define IRES_EDMA3CHAN_MAXPARAMS 512
00112 #define IRES_EDMA3CHAN_MAXTCCS 32
00113 #define IRES_EDMA3CHAN_NUMDESTTYPES 8
00114
00118 #define IRES_EDMA3CHAN_PARAM_ANY 512
00119 #define IRES_EDMA3CHAN_PARAM_NONE 513
00120 #define IRES_EDMA3CHAN_TCC_ANY 514
00121 #define IRES_EDMA3CHAN_TCC_NONE 515
00122 #define IRES_EDMA3CHAN_EDMACHAN_ANY 516
00123 #define IRES_EDMA3CHAN_QDMACHAN_ANY 516
00124 #define IRES_EDMA3CHAN_CHAN_NONE 518
00125
00129 typedef struct IRES_EDMA3CHAN_Obj *IRES_EDMA3CHAN_Handle;
00130
00134 typedef struct IRES_EDMA3CHAN2_Obj *IRES_EDMA3CHAN2_Handle;
00135
00141
00142 typedef struct IRES_EDMA3CHAN_PaRamStruct {
00143 unsigned int opt;
00148 unsigned int src;
00153 unsigned short acnt;
00164 unsigned short bcnt;
00174 unsigned int dst;
00179 unsigned short srcElementIndex;
00189 unsigned short dstElementIndex;
00200 unsigned short link;
00211 unsigned short bCntrld;
00222 unsigned short srcFrameIndex;
00248 unsigned short dstFrameIndex;
00276 unsigned short ccnt;
00287 unsigned short rsvd;
00288 } IRES_EDMA3CHAN_PaRamStruct;
00289
00290
00309 typedef struct IRES_EDMA3CHAN_ProtocolArgs {
00310 int size;
00311 IRES_RequestMode mode;
00315 short numPaRams;
00321 short paRamIndex;
00330 short numTccs;
00336 short tccIndex;
00345 short qdmaChan;
00351 short edmaChan;
00366 short contiguousAllocation;
00370 short shadowPaRamsAllocation;
00373 } IRES_EDMA3CHAN_ProtocolArgs;
00374
00385 typedef struct IRES_EDMA3CHAN_Obj {
00386
00387 IRES_Obj ires;
00388 IRES_EDMA3CHAN_PaRamStruct * shadowPaRams;
00391 unsigned int * assignedPaRamAddresses;
00394 short * assignedPaRamIndices;
00395 short * assignedTccIndices;
00396 short assignedNumPaRams;
00397 short assignedNumTccs;
00398 short assignedQdmaChannelIndex;
00406 short assignedEdmaChannelIndex;
00414 unsigned int esrBitMaskL;
00423 unsigned int esrBitMaskH;
00432 unsigned int iprBitMaskL;
00441 unsigned int iprBitMaskH;
00450 } IRES_EDMA3CHAN_Obj;
00451
00455 typedef struct IRES_EDMA3CHAN_EDMA3ShadowRegister {
00456 volatile unsigned int ER;
00457 volatile unsigned int ERH;
00458 volatile unsigned int ECR;
00459 volatile unsigned int ECRH;
00460 volatile unsigned int ESR;
00461 volatile unsigned int ESRH;
00462 volatile unsigned int CER;
00463 volatile unsigned int CERH;
00464 volatile unsigned int EER;
00465 volatile unsigned int EERH;
00466 volatile unsigned int EECR;
00467 volatile unsigned int EECRH;
00468 volatile unsigned int EESR;
00469 volatile unsigned int EESRH;
00470 volatile unsigned int SER;
00471 volatile unsigned int SERH;
00472 volatile unsigned int SECR;
00473 volatile unsigned int SECRH;
00474 volatile unsigned char RSVD0[8];
00475 volatile unsigned int IER;
00476 volatile unsigned int IERH;
00477 volatile unsigned int IECR;
00478 volatile unsigned int IECRH;
00479 volatile unsigned int IESR;
00480 volatile unsigned int IESRH;
00481 volatile unsigned int IPR;
00482 volatile unsigned int IPRH;
00483 volatile unsigned int ICR;
00484 volatile unsigned int ICRH;
00485 volatile unsigned int IEVAL;
00486 volatile unsigned char RSVD1[4];
00487 volatile unsigned int QER;
00488 volatile unsigned int QEER;
00489 volatile unsigned int QEECR;
00490 volatile unsigned int QEESR;
00491 volatile unsigned int QSER;
00492 volatile unsigned int QSECR;
00493 volatile unsigned char RSVD2[360];
00494
00495 } IRES_EDMA3CHAN_EDMA3ShadowRegister;
00496
00501 typedef struct IRES_EDMA3CHAN_EDMA3DraeRegister {
00502 volatile unsigned int DRAE;
00503 volatile unsigned int DRAEH;
00504 } IRES_EDMA3CHAN_EDMA3DraeRegister;
00505
00509 typedef struct IRES_EDMA3CHAN_EDMA3RegisterLayer {
00510 volatile unsigned int REV;
00511 volatile unsigned int CCCFG;
00512 volatile unsigned char RSVD0[248];
00513 volatile unsigned int DCHMAP[64];
00514 volatile unsigned int QCHMAP[8];
00515 volatile unsigned char RSVD1[32];
00516 volatile unsigned int DMAQNUM[8];
00517 volatile unsigned int QDMAQNUM;
00518 volatile unsigned char RSVD2[28];
00519 volatile unsigned int QUETCMAP;
00520 volatile unsigned int QUEPRI;
00521 volatile unsigned char RSVD3[120];
00522 volatile unsigned int EMR;
00523 volatile unsigned int EMRH;
00524 volatile unsigned int EMCR;
00525 volatile unsigned int EMCRH;
00526 volatile unsigned int QEMR;
00527 volatile unsigned int QEMCR;
00528 volatile unsigned int CCERR;
00529 volatile unsigned int CCERRCLR;
00530 volatile unsigned int EEVAL;
00531 volatile unsigned char RSVD4[28];
00532 IRES_EDMA3CHAN_EDMA3DraeRegister DRA[8];
00533 volatile unsigned int QRAE[8];
00534 volatile unsigned char RSVD5[96];
00535 volatile unsigned int QUEEVTENTRY[8][16];
00536 volatile unsigned int QSTAT[8];
00537 volatile unsigned int QWMTHRA;
00538 volatile unsigned int QWMTHRB;
00539 volatile unsigned char RSVD6[24];
00540 volatile unsigned int CCSTAT;
00541 volatile unsigned char RSVD7[188];
00542 volatile unsigned int AETCTL;
00543 volatile unsigned int AETSTAT;
00544 volatile unsigned int AETCMD;
00545 volatile unsigned char RSVD8[244];
00546 volatile unsigned int MPFAR;
00547 volatile unsigned int MPFSR;
00548 volatile unsigned int MPFCR;
00549 volatile unsigned int MPPAG;
00550 volatile unsigned int MPPA[8];
00551 volatile unsigned char RSVD9[2000];
00552 volatile unsigned int ER;
00553 volatile unsigned int ERH;
00554 volatile unsigned int ECR;
00555 volatile unsigned int ECRH;
00556 volatile unsigned int ESR;
00557 volatile unsigned int ESRH;
00558 volatile unsigned int CER;
00559 volatile unsigned int CERH;
00560 volatile unsigned int EER;
00561 volatile unsigned int EERH;
00562 volatile unsigned int EECR;
00563 volatile unsigned int EECRH;
00564 volatile unsigned int EESR;
00565 volatile unsigned int EESRH;
00566 volatile unsigned int SER;
00567 volatile unsigned int SERH;
00568 volatile unsigned int SECR;
00569 volatile unsigned int SECRH;
00570 volatile unsigned char RSVD10[8];
00571 volatile unsigned int IER;
00572 volatile unsigned int IERH;
00573 volatile unsigned int IECR;
00574 volatile unsigned int IECRH;
00575 volatile unsigned int IESR;
00576 volatile unsigned int IESRH;
00577 volatile unsigned int IPR;
00578 volatile unsigned int IPRH;
00579 volatile unsigned int ICR;
00580 volatile unsigned int ICRH;
00581 volatile unsigned int IEVAL;
00582 volatile unsigned char RSVD11[4];
00583 volatile unsigned int QER;
00584 volatile unsigned int QEER;
00585 volatile unsigned int QEECR;
00586 volatile unsigned int QEESR;
00587 volatile unsigned int QSER;
00588 volatile unsigned int QSECR;
00589 volatile unsigned char RSVD12[3944];
00590 IRES_EDMA3CHAN_EDMA3ShadowRegister SHADOW[8];
00591 volatile unsigned char RSVD13[4096];
00592 IRES_EDMA3CHAN_PaRamStruct PARAMENTRY[512];
00593 } IRES_EDMA3CHAN_EDMA3RegisterLayer;
00594
00598 typedef struct IRES_EDMA3CHAN_Properties {
00599
00600 unsigned int numDmaChannels;
00603 unsigned int numQdmaChannels;
00607 unsigned int numTccs;
00610 unsigned int numPaRAMSets;
00613 unsigned int numEvtQueue;
00616 unsigned int numTcs;
00620 unsigned int numRegions;
00631 unsigned short dmaChPaRAMMapExists;
00632
00633 unsigned short memProtectionExists;
00637 IRES_EDMA3CHAN_EDMA3RegisterLayer *globalRegs;
00641 } IRES_EDMA3CHAN_Properties;
00642
00650 typedef enum IRES_EDMA3CHAN_DmaDestType {
00651 INTMEMORY0 = 0,
00652 INTMEMORY1 = 1,
00653 INTMEMORY2 = 2,
00654 EXTMEMORY0 = 3,
00655 EXTMEMORY1 = 4,
00656 EXTMEMORY2 = 5,
00657 OTHER0 = 6,
00658 OTHER1 = 7
00659 } IRES_EDMA3CHAN_DmaDestType;
00660
00679 typedef struct IRES_EDMA3CHAN2_Obj {
00680
00681 IRES_Obj ires;
00682
00684 IRES_EDMA3CHAN_PaRamStruct * shadowPaRams;
00685
00687 unsigned int * assignedPaRamAddresses;
00688
00690 short * assignedPaRamIndices;
00691
00693 short * assignedTccIndices;
00694
00696 short assignedNumPaRams;
00697
00699 short assignedNumTccs;
00700
00702 short assignedQdmaChannelIndex;
00703
00705 short assignedEdmaChannelIndex;
00706
00708 unsigned int esrBitMaskL;
00709
00711 unsigned int esrBitMaskH;
00712
00714 unsigned int iprBitMaskL;
00715
00717 unsigned int iprBitMaskH;
00718
00719 XDAS_Int32 * queueMap;
00733 } IRES_EDMA3CHAN2_Obj;
00734
00735 #ifdef __cplusplus
00736 }
00737 #endif
00738
00741 #endif
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