Go to the documentation of this file.00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00048 #ifndef ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
00049 #define ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
00050
00053
00054 #ifdef __cplusplus
00055 extern "C" {
00056 #endif
00057
00058 #include <ti/xdais/xdas.h>
00059 #include <ti/xdais/ires_common.h>
00060
00064 #define IRES_EDMA3CHAN_PROTOCOLNAME "ti.sdo.fc.ires.edma3chan"
00065
00074 #define EDMA3CHAN_MODNAME "ti.sdo.fc.ires.edma3chan"
00075
00079 #define EDMA3CHAN_GTNAME "ti.sdo.fc.ires.edma3chan"
00080
00081
00082
00083
00084
00085
00086 #ifndef ti_sdo_fc_ires_NOPROTOCOLREV
00087
00092 static IRES_ProtocolRevision IRES_EDMA3CHAN_PROTOCOLREVISION = {1, 0, 0};
00093
00094 #endif
00095
00099 #define IRES_EDMA3CHAN_PROTOCOLREVISION_1_0_0 {1, 0, 0}
00100 #define IRES_EDMA3CHAN_SETPROTOCOLREVISION_1_0_0(rev) {(rev)->Major = 1; \
00101 (rev)->Source = 0; (rev)->Radius = 0;}
00102
00106 #define IRES_EDMA3CHAN_PROTOCOLREVISION_2_0_0 {2, 0, 0}
00107 #define IRES_EDMA3CHAN_SETPROTOCOLREVISION_2_0_0(rev) {(rev)->Major = 2; \
00108 (rev)->Source = 0; (rev)->Radius = 0;}
00109
00114 #define IRES_EDMA3CHAN_MAXPARAMS 512
00115 #define IRES_EDMA3CHAN_MAXTCCS 32
00116 #define IRES_EDMA3CHAN_NUMDESTTYPES 8
00117
00121 #define IRES_EDMA3CHAN_PARAM_ANY 512
00122 #define IRES_EDMA3CHAN_PARAM_NONE 513
00123 #define IRES_EDMA3CHAN_TCC_ANY 514
00124 #define IRES_EDMA3CHAN_TCC_NONE 515
00125 #define IRES_EDMA3CHAN_EDMACHAN_ANY 516
00126 #define IRES_EDMA3CHAN_QDMACHAN_ANY 516
00127 #define IRES_EDMA3CHAN_CHAN_NONE 518
00128
00132 typedef struct IRES_EDMA3CHAN_Obj *IRES_EDMA3CHAN_Handle;
00133
00137 typedef struct IRES_EDMA3CHAN2_Obj *IRES_EDMA3CHAN2_Handle;
00138
00142 typedef struct IRES_EDMA3CHAN_PaRamStruct {
00143 unsigned int opt;
00144 unsigned int src;
00145 unsigned short acnt;
00146 unsigned short bcnt;
00147 unsigned int dst;
00148 unsigned short srcElementIndex;
00149 unsigned short dstElementIndex;
00150 unsigned short link;
00151 unsigned short bCntrld;
00152 unsigned short srcFrameIndex;
00153 unsigned short dstFrameIndex;
00154 unsigned short ccnt;
00155 unsigned short rsvd;
00156 } IRES_EDMA3CHAN_PaRamStruct;
00157
00175 typedef struct IRES_EDMA3CHAN_ProtocolArgs {
00176 int size;
00177 IRES_RequestMode mode;
00180 short numPaRams;
00183 short paRamIndex;
00189 short numTccs;
00192 short tccIndex;
00198 short qdmaChan;
00199 short edmaChan;
00208
00209
00210
00211
00212
00213
00214
00215 short contiguousAllocation;
00219 short shadowPaRamsAllocation;
00222 } IRES_EDMA3CHAN_ProtocolArgs;
00223
00229 typedef struct IRES_EDMA3CHAN_Obj {
00230
00231 IRES_Obj ires;
00232 IRES_EDMA3CHAN_PaRamStruct * shadowPaRams;
00234 unsigned int * assignedPaRamAddresses;
00236 short * assignedPaRamIndices;
00237 short * assignedTccIndices;
00238 short assignedNumPaRams;
00239 short assignedNumTccs;
00240 short assignedQdmaChannelIndex;
00245 short assignedEdmaChannelIndex;
00250 unsigned int esrBitMaskL;
00251 unsigned int esrBitMaskH;
00254 unsigned int iprBitMaskL;
00255 unsigned int iprBitMaskH;
00258 } IRES_EDMA3CHAN_Obj;
00259
00264 typedef struct IRES_EDMA3CHAN_EDMA3ShadowRegister {
00265 volatile unsigned int ER;
00266 volatile unsigned int ERH;
00267 volatile unsigned int ECR;
00268 volatile unsigned int ECRH;
00269 volatile unsigned int ESR;
00270 volatile unsigned int ESRH;
00271 volatile unsigned int CER;
00272 volatile unsigned int CERH;
00273 volatile unsigned int EER;
00274 volatile unsigned int EERH;
00275 volatile unsigned int EECR;
00276 volatile unsigned int EECRH;
00277 volatile unsigned int EESR;
00278 volatile unsigned int EESRH;
00279 volatile unsigned int SER;
00280 volatile unsigned int SERH;
00281 volatile unsigned int SECR;
00282 volatile unsigned int SECRH;
00283 volatile unsigned char RSVD0[8];
00284 volatile unsigned int IER;
00285 volatile unsigned int IERH;
00286 volatile unsigned int IECR;
00287 volatile unsigned int IECRH;
00288 volatile unsigned int IESR;
00289 volatile unsigned int IESRH;
00290 volatile unsigned int IPR;
00291 volatile unsigned int IPRH;
00292 volatile unsigned int ICR;
00293 volatile unsigned int ICRH;
00294 volatile unsigned int IEVAL;
00295 volatile unsigned char RSVD1[4];
00296 volatile unsigned int QER;
00297 volatile unsigned int QEER;
00298 volatile unsigned int QEECR;
00299 volatile unsigned int QEESR;
00300 volatile unsigned int QSER;
00301 volatile unsigned int QSECR;
00302 volatile unsigned char RSVD2[360];
00303
00304 } IRES_EDMA3CHAN_EDMA3ShadowRegister;
00305
00310 typedef struct IRES_EDMA3CHAN_EDMA3DraeRegister {
00311 volatile unsigned int DRAE;
00312 volatile unsigned int DRAEH;
00313 } IRES_EDMA3CHAN_EDMA3DraeRegister;
00314
00315
00316
00317
00318
00319 typedef struct IRES_EDMA3CHAN_EDMA3RegisterLayer {
00320 volatile unsigned int REV;
00321 volatile unsigned int CCCFG;
00322 volatile unsigned char RSVD0[248];
00323 volatile unsigned int DCHMAP[64];
00324 volatile unsigned int QCHMAP[8];
00325 volatile unsigned char RSVD1[32];
00326 volatile unsigned int DMAQNUM[8];
00327 volatile unsigned int QDMAQNUM;
00328 volatile unsigned char RSVD2[28];
00329 volatile unsigned int QUETCMAP;
00330 volatile unsigned int QUEPRI;
00331 volatile unsigned char RSVD3[120];
00332 volatile unsigned int EMR;
00333 volatile unsigned int EMRH;
00334 volatile unsigned int EMCR;
00335 volatile unsigned int EMCRH;
00336 volatile unsigned int QEMR;
00337 volatile unsigned int QEMCR;
00338 volatile unsigned int CCERR;
00339 volatile unsigned int CCERRCLR;
00340 volatile unsigned int EEVAL;
00341 volatile unsigned char RSVD4[28];
00342 IRES_EDMA3CHAN_EDMA3DraeRegister DRA[8];
00343 volatile unsigned int QRAE[8];
00344 volatile unsigned char RSVD5[96];
00345 volatile unsigned int QUEEVTENTRY[8][16];
00346 volatile unsigned int QSTAT[8];
00347 volatile unsigned int QWMTHRA;
00348 volatile unsigned int QWMTHRB;
00349 volatile unsigned char RSVD6[24];
00350 volatile unsigned int CCSTAT;
00351 volatile unsigned char RSVD7[188];
00352 volatile unsigned int AETCTL;
00353 volatile unsigned int AETSTAT;
00354 volatile unsigned int AETCMD;
00355 volatile unsigned char RSVD8[244];
00356 volatile unsigned int MPFAR;
00357 volatile unsigned int MPFSR;
00358 volatile unsigned int MPFCR;
00359 volatile unsigned int MPPAG;
00360 volatile unsigned int MPPA[8];
00361 volatile unsigned char RSVD9[2000];
00362 volatile unsigned int ER;
00363 volatile unsigned int ERH;
00364 volatile unsigned int ECR;
00365 volatile unsigned int ECRH;
00366 volatile unsigned int ESR;
00367 volatile unsigned int ESRH;
00368 volatile unsigned int CER;
00369 volatile unsigned int CERH;
00370 volatile unsigned int EER;
00371 volatile unsigned int EERH;
00372 volatile unsigned int EECR;
00373 volatile unsigned int EECRH;
00374 volatile unsigned int EESR;
00375 volatile unsigned int EESRH;
00376 volatile unsigned int SER;
00377 volatile unsigned int SERH;
00378 volatile unsigned int SECR;
00379 volatile unsigned int SECRH;
00380 volatile unsigned char RSVD10[8];
00381 volatile unsigned int IER;
00382 volatile unsigned int IERH;
00383 volatile unsigned int IECR;
00384 volatile unsigned int IECRH;
00385 volatile unsigned int IESR;
00386 volatile unsigned int IESRH;
00387 volatile unsigned int IPR;
00388 volatile unsigned int IPRH;
00389 volatile unsigned int ICR;
00390 volatile unsigned int ICRH;
00391 volatile unsigned int IEVAL;
00392 volatile unsigned char RSVD11[4];
00393 volatile unsigned int QER;
00394 volatile unsigned int QEER;
00395 volatile unsigned int QEECR;
00396 volatile unsigned int QEESR;
00397 volatile unsigned int QSER;
00398 volatile unsigned int QSECR;
00399 volatile unsigned char RSVD12[3944];
00400 IRES_EDMA3CHAN_EDMA3ShadowRegister SHADOW[8];
00401 volatile unsigned char RSVD13[4096];
00402 IRES_EDMA3CHAN_PaRamStruct PARAMENTRY[512];
00403 } IRES_EDMA3CHAN_EDMA3RegisterLayer;
00404
00408 typedef struct IRES_EDMA3CHAN_Properties {
00409
00410 unsigned int numDmaChannels;
00412 unsigned int numQdmaChannels;
00415 unsigned int numTccs;
00417 unsigned int numPaRAMSets;
00418 unsigned int numEvtQueue;
00420 unsigned int numTcs;
00423 unsigned int numRegions;
00433 unsigned short dmaChPaRAMMapExists;
00434
00435 unsigned short memProtectionExists;
00438 IRES_EDMA3CHAN_EDMA3RegisterLayer *globalRegs;
00441 } IRES_EDMA3CHAN_Properties;
00442
00450 typedef enum IRES_EDMA3CHAN_DmaDestType {
00451 INTMEMORY0 = 0,
00452 INTMEMORY1 = 1,
00453 INTMEMORY2 = 2,
00454 EXTMEMORY0 = 3,
00455 EXTMEMORY1 = 4,
00456 EXTMEMORY2 = 5,
00457 OTHER0 = 6,
00458 OTHER1 = 7
00459 } IRES_EDMA3CHAN_DmaDestType;
00460
00469 typedef struct IRES_EDMA3CHAN2_Obj {
00470
00471 IRES_Obj ires;
00472 IRES_EDMA3CHAN_PaRamStruct * shadowPaRams;
00474 unsigned int * assignedPaRamAddresses;
00476 short * assignedPaRamIndices;
00477 short * assignedTccIndices;
00478 short assignedNumPaRams;
00479 short assignedNumTccs;
00480 short assignedQdmaChannelIndex;
00485 short assignedEdmaChannelIndex;
00490 unsigned int esrBitMaskL;
00491 unsigned int esrBitMaskH;
00494 unsigned int iprBitMaskL;
00495 unsigned int iprBitMaskH;
00498 XDAS_Int32 * queueMap;
00508 } IRES_EDMA3CHAN2_Obj;
00509
00510 #ifdef __cplusplus
00511 }
00512 #endif
00513
00516 #endif
00517
00518
00519
00520
00521