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00039 #ifndef _EDMA3_COMMON_H_
00040 #define _EDMA3_COMMON_H_
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046
00048 #define EDMA3_RM_DEBUG
00049 #undef EDMA3_RM_DEBUG
00050
00052 #define EDMA3_DRV_DEBUG
00053 #undef EDMA3_DRV_DEBUG
00054
00055
00057 #ifdef EDMA3_RM_DEBUG
00058 #include <stdio.h>
00059 #define EDMA3_RM_PRINTF printf
00060 #endif
00061
00063 #ifdef EDMA3_DRV_DEBUG
00064 #include <stdio.h>
00065 #define EDMA3_DRV_PRINTF printf
00066 #endif
00067
00068
00070 #ifndef TRUE
00071
00072 #define TRUE (1u)
00073
00074 #define FALSE (0u)
00075 #endif
00076
00077
00079 #ifndef NULL
00080 #define NULL 0u
00081 #endif
00082
00083
00085 typedef int EDMA3_RM_Result;
00087 typedef int EDMA3_DRV_Result;
00088
00089
00091 #define EDMA3_RM_SOK (0u)
00092
00093 #define EDMA3_DRV_SOK (0u)
00094
00095
00101 typedef void *EDMA3_RM_Handle;
00107 typedef void *EDMA3_DRV_Handle;
00108
00109
00115 typedef void *EDMA3_OS_Sem_Handle;
00116
00118 #define EDMA3_OSSEM_NO_TIMEOUT (-1)
00119
00120
00128 #define EDMA3_MAX_EDMA3_INSTANCES (2u)
00129
00130 #define EDMA3_MAX_DMA_CH (64u)
00131
00132 #define EDMA3_MAX_QDMA_CH (8u)
00133
00134 #define EDMA3_MAX_PARAM_SETS (512u)
00135
00136 #define EDMA3_MAX_LOGICAL_CH (EDMA3_MAX_DMA_CH + \
00137 EDMA3_MAX_PARAM_SETS + \
00138 EDMA3_MAX_QDMA_CH)
00139
00140 #define EDMA3_MAX_TCC (64u)
00141
00142 #define EDMA3_MAX_EVT_QUE (8u)
00143
00144 #define EDMA3_MAX_TC (8u)
00145
00146 #define EDMA3_MAX_REGIONS (8u)
00147
00152 #define EDMA3_MAX_DMA_CHAN_DWRDS (EDMA3_MAX_DMA_CH / 32u)
00153
00158 #define EDMA3_MAX_QDMA_CHAN_DWRDS (1u)
00159
00164 #define EDMA3_MAX_PARAM_DWRDS (EDMA3_MAX_PARAM_SETS / 32u)
00165
00170 #define EDMA3_MAX_TCC_DWRDS (EDMA3_MAX_TCC / 32u)
00171
00172
00173
00181 extern void lisrEdma3ComplHandler0 (unsigned int arg);
00182
00184 extern void lisrEdma3CCErrHandler0 (unsigned int arg);
00185
00187 extern void lisrEdma3TC0ErrHandler0(unsigned int arg);
00189 extern void lisrEdma3TC1ErrHandler0(unsigned int arg);
00191 extern void lisrEdma3TC2ErrHandler0(unsigned int arg);
00193 extern void lisrEdma3TC3ErrHandler0(unsigned int arg);
00195 extern void lisrEdma3TC4ErrHandler0(unsigned int arg);
00197 extern void lisrEdma3TC5ErrHandler0(unsigned int arg);
00199 extern void lisrEdma3TC6ErrHandler0(unsigned int arg);
00201 extern void lisrEdma3TC7ErrHandler0(unsigned int arg);
00202
00203
00204
00211 #define EDMA3_OS_PROTECT_INTERRUPT 1
00212
00213 #define EDMA3_OS_PROTECT_SCHEDULER 2
00214
00215 #define EDMA3_OS_PROTECT_INTERRUPT_XFER_COMPLETION 3
00216
00217 #define EDMA3_OS_PROTECT_INTERRUPT_CC_ERROR 4
00218
00219 #define EDMA3_OS_PROTECT_INTERRUPT_TC_ERROR 5
00220
00221
00222
00277 extern void edma3OsProtectEntry (unsigned int edma3InstanceId,
00278 int level,
00279 unsigned int *intState);
00280
00281
00302 extern void edma3OsProtectExit (unsigned int edma3InstanceId,
00303 int level,
00304 unsigned int intState);
00305
00306
00330 extern EDMA3_DRV_Result edma3OsSemTake (EDMA3_OS_Sem_Handle hSem,
00331 int mSecTimeout);
00332
00343 extern EDMA3_DRV_Result edma3OsSemGive(EDMA3_OS_Sem_Handle hSem);
00344
00345 #ifdef __cplusplus
00346 }
00347 #endif
00348
00349 #endif
00350