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00039 #ifndef _EDMA3_RL_TC_H_
00040 #define _EDMA3_RL_TC_H_
00041
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045
00046
00047
00048
00049 typedef struct {
00050 volatile unsigned int DFOPT;
00051 volatile unsigned int DFSRC;
00052 volatile unsigned int DFCNT;
00053 volatile unsigned int DFDST;
00054 volatile unsigned int DFBIDX;
00055 volatile unsigned int DFMPPRXY;
00056 volatile unsigned char RSVD0[40];
00057 } EDMA3_TCRL_DfiregRegs;
00058
00059
00060
00061
00062 typedef struct {
00063 volatile unsigned int REV;
00064 volatile unsigned int TCCFG;
00065 volatile unsigned char RSVD0[248];
00066 volatile unsigned int TCSTAT;
00067 volatile unsigned int INTSTAT;
00068 volatile unsigned int INTEN;
00069 volatile unsigned int INTCLR;
00070 volatile unsigned int INTCMD;
00071 volatile unsigned char RSVD1[12];
00072 volatile unsigned int ERRSTAT;
00073 volatile unsigned int ERREN;
00074 volatile unsigned int ERRCLR;
00075 volatile unsigned int ERRDET;
00076 volatile unsigned int ERRCMD;
00077 volatile unsigned char RSVD2[12];
00078 volatile unsigned int RDRATE;
00079 volatile unsigned char RSVD3[188];
00080 volatile unsigned int POPT;
00081 volatile unsigned int PSRC;
00082 volatile unsigned int PCNT;
00083 volatile unsigned int PDST;
00084 volatile unsigned int PBIDX;
00085 volatile unsigned int PMPPRXY;
00086 volatile unsigned char RSVD4[40];
00087 volatile unsigned int SAOPT;
00088 volatile unsigned int SASRC;
00089 volatile unsigned int SACNT;
00090 volatile unsigned int SADST;
00091 volatile unsigned int SABIDX;
00092 volatile unsigned int SAMPPRXY;
00093 volatile unsigned int SACNTRLD;
00094 volatile unsigned int SASRCBREF;
00095 volatile unsigned int SADSTBREF;
00096 volatile unsigned char RSVD5[28];
00097 volatile unsigned int DFCNTRLD;
00098 volatile unsigned int DFSRCBREF;
00099 volatile unsigned int DFDSTBREF;
00100 volatile unsigned char RSVD6[116];
00101 EDMA3_TCRL_DfiregRegs DFIREG[4];
00102 } EDMA3_TCRL_Regs;
00103
00104
00105
00106
00107
00108
00109
00110 #define EDMA3_TCRL_REV_TYPE_MASK (0x00FF0000u)
00111 #define EDMA3_TCRL_REV_TYPE_SHIFT (0x00000010u)
00112 #define EDMA3_TCRL_REV_TYPE_RESETVAL (0x00000006u)
00113
00114 #define EDMA3_TCRL_REV_CLASS_MASK (0x0000FF00u)
00115 #define EDMA3_TCRL_REV_CLASS_SHIFT (0x00000008u)
00116 #define EDMA3_TCRL_REV_CLASS_RESETVAL (0x00000004u)
00117
00118 #define EDMA3_TCRL_REV_REV_MASK (0x000000FFu)
00119 #define EDMA3_TCRL_REV_REV_SHIFT (0x00000000u)
00120 #define EDMA3_TCRL_REV_REV_RESETVAL (0x00000001u)
00121
00122 #define EDMA3_TCRL_REV_RESETVAL (0x00060401u)
00123
00124
00125
00126 #define EDMA3_TCRL_TCCFG_DREGDEPTH_MASK (0x00000300u)
00127 #define EDMA3_TCRL_TCCFG_DREGDEPTH_SHIFT (0x00000008u)
00128 #define EDMA3_TCRL_TCCFG_DREGDEPTH_RESETVAL (0x00000000u)
00129
00130
00131 #define EDMA3_TCRL_TCCFG_DREGDEPTH_1ENTRY (0x00000000u)
00132 #define EDMA3_TCRL_TCCFG_DREGDEPTH_2ENTRY (0x00000001u)
00133 #define EDMA3_TCRL_TCCFG_DREGDEPTH_4ENTRY (0x00000002u)
00134
00135 #define EDMA3_TCRL_TCCFG_BUSWIDTH_MASK (0x00000030u)
00136 #define EDMA3_TCRL_TCCFG_BUSWIDTH_SHIFT (0x00000004u)
00137 #define EDMA3_TCRL_TCCFG_BUSWIDTH_RESETVAL (0x00000000u)
00138
00139
00140 #define EDMA3_TCRL_TCCFG_BUSWIDTH_32BIT (0x00000000u)
00141 #define EDMA3_TCRL_TCCFG_BUSWIDTH_64BIY (0x00000001u)
00142 #define EDMA3_TCRL_TCCFG_BUSWIDTH_128BIT (0x00000002u)
00143
00144 #define EDMA3_TCRL_TCCFG_FIFOSIZE_MASK (0x00000007u)
00145 #define EDMA3_TCRL_TCCFG_FIFOSIZE_SHIFT (0x00000000u)
00146 #define EDMA3_TCRL_TCCFG_FIFOSIZE_RESETVAL (0x00000000u)
00147
00148
00149 #define EDMA3_TCRL_TCCFG_FIFOSIZE_32BYTE (0x00000000u)
00150 #define EDMA3_TCRL_TCCFG_FIFOSIZE_64BYTE (0x00000001u)
00151 #define EDMA3_TCRL_TCCFG_FIFOSIZE_128BYTE (0x00000002u)
00152 #define EDMA3_TCRL_TCCFG_FIFOSIZE_256BYTE (0x00000003u)
00153 #define EDMA3_TCRL_TCCFG_FIFOSIZE_512BYTE (0x00000004u)
00154
00155 #define EDMA3_TCRL_TCCFG_RESETVAL (0x00000000u)
00156
00157
00158
00159 #define EDMA3_TCRL_TCSTAT_DFSTRT_MASK (0x00003000u)
00160 #define EDMA3_TCRL_TCSTAT_DFSTRT_SHIFT (0x0000000Cu)
00161 #define EDMA3_TCRL_TCSTAT_DFSTRT_RESETVAL (0x00000000u)
00162
00163 #define EDMA3_TCRL_TCSTAT_ATCV_MASK (0x00000100u)
00164 #define EDMA3_TCRL_TCSTAT_ATCV_SHIFT (0x00000008u)
00165 #define EDMA3_TCRL_TCSTAT_ATCV_RESETVAL (0x00000000u)
00166
00167
00168 #define EDMA3_TCRL_TCSTAT_ATCV_IDLE (0x00000000u)
00169 #define EDMA3_TCRL_TCSTAT_ATCV_BUSY (0x00000001u)
00170
00171 #define EDMA3_TCRL_TCSTAT_DSTACT_MASK (0x00000070u)
00172 #define EDMA3_TCRL_TCSTAT_DSTACT_SHIFT (0x00000004u)
00173 #define EDMA3_TCRL_TCSTAT_DSTACT_RESETVAL (0x00000000u)
00174
00175
00176 #define EDMA3_TCRL_TCSTAT_DSTACT_EMPTY (0x00000000u)
00177 #define EDMA3_TCRL_TCSTAT_DSTACT_1TR (0x00000001u)
00178 #define EDMA3_TCRL_TCSTAT_DSTACT_2TR (0x00000002u)
00179 #define EDMA3_TCRL_TCSTAT_DSTACT_3TR (0x00000003u)
00180 #define EDMA3_TCRL_TCSTAT_DSTACT_4TR (0x00000004u)
00181
00182 #define EDMA3_TCRL_TCSTAT_WSACTV_MASK (0x00000004u)
00183 #define EDMA3_TCRL_TCSTAT_WSACTV_SHIFT (0x00000002u)
00184 #define EDMA3_TCRL_TCSTAT_WSACTV_RESETVAL (0x00000000u)
00185
00186
00187 #define EDMA3_TCRL_TCSTAT_WSACTV_NONE (0x00000000u)
00188 #define EDMA3_TCRL_TCSTAT_WSACTV_PEND (0x00000001u)
00189
00190 #define EDMA3_TCRL_TCSTAT_SRCACTV_MASK (0x00000002u)
00191 #define EDMA3_TCRL_TCSTAT_SRCACTV_SHIFT (0x00000001u)
00192 #define EDMA3_TCRL_TCSTAT_SRCACTV_RESETVAL (0x00000000u)
00193
00194
00195 #define EDMA3_TCRL_TCSTAT_SRCACTV_IDLE (0x00000000u)
00196 #define EDMA3_TCRL_TCSTAT_SRCACTV_BUSY (0x00000001u)
00197
00198 #define EDMA3_TCRL_TCSTAT_PROGBUSY_MASK (0x00000001u)
00199 #define EDMA3_TCRL_TCSTAT_PROGBUSY_SHIFT (0x00000000u)
00200 #define EDMA3_TCRL_TCSTAT_PROGBUSY_RESETVAL (0x00000000u)
00201
00202
00203 #define EDMA3_TCRL_TCSTAT_PROGBUSY_IDLE (0x00000000u)
00204 #define EDMA3_TCRL_TCSTAT_PROGBUSY_BUSY (0x00000001u)
00205
00206 #define EDMA3_TCRL_TCSTAT_RESETVAL (0x00000000u)
00207
00208
00209
00210 #define EDMA3_TCRL_INTSTAT_TRDONE_MASK (0x00000002u)
00211 #define EDMA3_TCRL_INTSTAT_TRDONE_SHIFT (0x00000001u)
00212 #define EDMA3_TCRL_INTSTAT_TRDONE_RESETVAL (0x00000000u)
00213
00214
00215 #define EDMA3_TCRL_INTSTAT_TRDONE_NONE (0x00000000u)
00216 #define EDMA3_TCRL_INTSTAT_TRDONE_DONE (0x00000001u)
00217
00218 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_MASK (0x00000001u)
00219 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_SHIFT (0x00000000u)
00220 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_RESETVAL (0x00000000u)
00221
00222
00223 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_NONE (0x00000000u)
00224 #define EDMA3_TCRL_INTSTAT_PROGEMPTY_EMPTY (0x00000001u)
00225
00226 #define EDMA3_TCRL_INTSTAT_RESETVAL (0x00000000u)
00227
00228
00229
00230 #define EDMA3_TCRL_INTEN_TRDONE_MASK (0x00000002u)
00231 #define EDMA3_TCRL_INTEN_TRDONE_SHIFT (0x00000001u)
00232 #define EDMA3_TCRL_INTEN_TRDONE_RESETVAL (0x00000000u)
00233
00234
00235 #define EDMA3_TCRL_INTEN_TRDONE_DISABLE (0x00000000u)
00236 #define EDMA3_TCRL_INTEN_TRDONE_ENABLE (0x00000001u)
00237
00238 #define EDMA3_TCRL_INTEN_PROGEMPTY_MASK (0x00000001u)
00239 #define EDMA3_TCRL_INTEN_PROGEMPTY_SHIFT (0x00000000u)
00240 #define EDMA3_TCRL_INTEN_PROGEMPTY_RESETVAL (0x00000000u)
00241
00242
00243 #define EDMA3_TCRL_INTEN_PROGEMPTY_DISABLE (0x00000000u)
00244 #define EDMA3_TCRL_INTEN_PROGEMPTY_ENABLE (0x00000001u)
00245
00246 #define EDMA3_TCRL_INTEN_RESETVAL (0x00000000u)
00247
00248
00249
00250 #define EDMA3_TCRL_INTCLR_TRDONE_MASK (0x00000002u)
00251 #define EDMA3_TCRL_INTCLR_TRDONE_SHIFT (0x00000001u)
00252 #define EDMA3_TCRL_INTCLR_TRDONE_RESETVAL (0x00000000u)
00253
00254
00255 #define EDMA3_TCRL_INTCLR_TRDONE_CLEAR (0x00000001u)
00256
00257 #define EDMA3_TCRL_INTCLR_PROGEMPTY_MASK (0x00000001u)
00258 #define EDMA3_TCRL_INTCLR_PROGEMPTY_SHIFT (0x00000000u)
00259 #define EDMA3_TCRL_INTCLR_PROGEMPTY_RESETVAL (0x00000000u)
00260
00261
00262 #define EDMA3_TCRL_INTCLR_PROGEMPTY_CLEAR (0x00000001u)
00263
00264 #define EDMA3_TCRL_INTCLR_RESETVAL (0x00000000u)
00265
00266
00267
00268 #define EDMA3_TCRL_INTCMD_SET_MASK (0x00000002u)
00269 #define EDMA3_TCRL_INTCMD_SET_SHIFT (0x00000001u)
00270 #define EDMA3_TCRL_INTCMD_SET_RESETVAL (0x00000000u)
00271
00272
00273 #define EDMA3_TCRL_INTCMD_SET_SET (0x00000001u)
00274
00275 #define EDMA3_TCRL_INTCMD_EVAL_MASK (0x00000001u)
00276 #define EDMA3_TCRL_INTCMD_EVAL_SHIFT (0x00000000u)
00277 #define EDMA3_TCRL_INTCMD_EVAL_RESETVAL (0x00000000u)
00278
00279
00280 #define EDMA3_TCRL_INTCMD_EVAL_EVAL (0x00000001u)
00281
00282 #define EDMA3_TCRL_INTCMD_RESETVAL (0x00000000u)
00283
00284
00285
00286 #define EDMA3_TCRL_ERRSTAT_MMRAERR_MASK (0x00000008u)
00287 #define EDMA3_TCRL_ERRSTAT_MMRAERR_SHIFT (0x00000003u)
00288 #define EDMA3_TCRL_ERRSTAT_MMRAERR_RESETVAL (0x00000000u)
00289
00290
00291 #define EDMA3_TCRL_ERRSTAT_MMRAERR_NONE (0x00000000u)
00292 #define EDMA3_TCRL_ERRSTAT_MMRAERR_ERROR (0x00000001u)
00293
00294 #define EDMA3_TCRL_ERRSTAT_TRERR_MASK (0x00000004u)
00295 #define EDMA3_TCRL_ERRSTAT_TRERR_SHIFT (0x00000002u)
00296 #define EDMA3_TCRL_ERRSTAT_TRERR_RESETVAL (0x00000000u)
00297
00298
00299 #define EDMA3_TCRL_ERRSTAT_TRERR_NONE (0x00000000u)
00300 #define EDMA3_TCRL_ERRSTAT_TRERR_ERROR (0x00000001u)
00301
00302 #define EDMA3_TCRL_ERRSTAT_BUSERR_MASK (0x00000001u)
00303 #define EDMA3_TCRL_ERRSTAT_BUSERR_SHIFT (0x00000000u)
00304 #define EDMA3_TCRL_ERRSTAT_BUSERR_RESETVAL (0x00000000u)
00305
00306
00307 #define EDMA3_TCRL_ERRSTAT_BUSERR_NONE (0x00000000u)
00308 #define EDMA3_TCRL_ERRSTAT_BUSERR_ERROR (0x00000001u)
00309
00310 #define EDMA3_TCRL_ERRSTAT_RESETVAL (0x00000000u)
00311
00312
00313
00314 #define EDMA3_TCRL_ERREN_MMRAERR_MASK (0x00000008u)
00315 #define EDMA3_TCRL_ERREN_MMRAERR_SHIFT (0x00000003u)
00316 #define EDMA3_TCRL_ERREN_MMRAERR_RESETVAL (0x00000000u)
00317
00318
00319 #define EDMA3_TCRL_ERREN_MMRAERR_ENABLE (0x00000001u)
00320 #define EDMA3_TCRL_ERREN_MMRAERR_DISABLE (0x00000000u)
00321
00322 #define EDMA3_TCRL_ERREN_TRERR_MASK (0x00000004u)
00323 #define EDMA3_TCRL_ERREN_TRERR_SHIFT (0x00000002u)
00324 #define EDMA3_TCRL_ERREN_TRERR_RESETVAL (0x00000000u)
00325
00326
00327 #define EDMA3_TCRL_ERREN_TRERR_ENABLE (0x00000001u)
00328 #define EDMA3_TCRL_ERREN_TRERR_DISABLE (0x00000000u)
00329
00330 #define EDMA3_TCRL_ERREN_BUSERR_MASK (0x00000001u)
00331 #define EDMA3_TCRL_ERREN_BUSERR_SHIFT (0x00000000u)
00332 #define EDMA3_TCRL_ERREN_BUSERR_RESETVAL (0x00000000u)
00333
00334
00335 #define EDMA3_TCRL_ERREN_BUSERR_ENABLE (0x00000001u)
00336 #define EDMA3_TCRL_ERREN_BUSERR_DISABLE (0x00000000u)
00337
00338 #define EDMA3_TCRL_ERREN_RESETVAL (0x00000000u)
00339
00340
00341
00342 #define EDMA3_TCRL_ERRCLR_MMRAERR_MASK (0x00000008u)
00343 #define EDMA3_TCRL_ERRCLR_MMRAERR_SHIFT (0x00000003u)
00344 #define EDMA3_TCRL_ERRCLR_MMRAERR_RESETVAL (0x00000000u)
00345
00346
00347 #define EDMA3_TCRL_ERRCLR_MMRAERR_CLEAR (0x00000001u)
00348
00349 #define EDMA3_TCRL_ERRCLR_TRERR_MASK (0x00000004u)
00350 #define EDMA3_TCRL_ERRCLR_TRERR_SHIFT (0x00000002u)
00351 #define EDMA3_TCRL_ERRCLR_TRERR_RESETVAL (0x00000000u)
00352
00353
00354 #define EDMA3_TCRL_ERRCLR_TRERR_CLEAR (0x00000001u)
00355
00356 #define EDMA3_TCRL_ERRCLR_BUSERR_MASK (0x00000001u)
00357 #define EDMA3_TCRL_ERRCLR_BUSERR_SHIFT (0x00000000u)
00358 #define EDMA3_TCRL_ERRCLR_BUSERR_RESETVAL (0x00000000u)
00359
00360
00361 #define EDMA3_TCRL_ERRCLR_BUSERR_CLEAR (0x00000001u)
00362
00363 #define EDMA3_TCRL_ERRCLR_RESETVAL (0x00000000u)
00364
00365
00366
00367 #define EDMA3_TCRL_ERRDET_TCCHEN_MASK (0x00020000u)
00368 #define EDMA3_TCRL_ERRDET_TCCHEN_SHIFT (0x00000011u)
00369 #define EDMA3_TCRL_ERRDET_TCCHEN_RESETVAL (0x00000000u)
00370
00371 #define EDMA3_TCRL_ERRDET_TCINTEN_MASK (0x00010000u)
00372 #define EDMA3_TCRL_ERRDET_TCINTEN_SHIFT (0x00000010u)
00373 #define EDMA3_TCRL_ERRDET_TCINTEN_RESETVAL (0x00000000u)
00374
00375 #define EDMA3_TCRL_ERRDET_TCC_MASK (0x00003F00u)
00376 #define EDMA3_TCRL_ERRDET_TCC_SHIFT (0x00000008u)
00377 #define EDMA3_TCRL_ERRDET_TCC_RESETVAL (0x00000000u)
00378
00379 #define EDMA3_TCRL_ERRDET_STAT_MASK (0x0000000Fu)
00380 #define EDMA3_TCRL_ERRDET_STAT_SHIFT (0x00000000u)
00381 #define EDMA3_TCRL_ERRDET_STAT_RESETVAL (0x00000000u)
00382
00383
00384 #define EDMA3_TCRL_ERRDET_STAT_NONE (0x00000000u)
00385 #define EDMA3_TCRL_ERRDET_STAT_READ_ADDRESS (0x00000001u)
00386 #define EDMA3_TCRL_ERRDET_STAT_READ_PRIVILEGE (0x00000002u)
00387 #define EDMA3_TCRL_ERRDET_STAT_READ_TIMEOUT (0x00000003u)
00388 #define EDMA3_TCRL_ERRDET_STAT_READ_DATA (0x00000004u)
00389 #define EDMA3_TCRL_ERRDET_STAT_READ_EXCLUSIVE (0x00000007u)
00390 #define EDMA3_TCRL_ERRDET_STAT_WRITE_ADDRESS (0x00000009u)
00391 #define EDMA3_TCRL_ERRDET_STAT_WRITE_PRIVILEGE (0x0000000Au)
00392 #define EDMA3_TCRL_ERRDET_STAT_WRITE_TIMEOUT (0x0000000Bu)
00393 #define EDMA3_TCRL_ERRDET_STAT_WRITE_DATA (0x0000000Cu)
00394 #define EDMA3_TCRL_ERRDET_STAT_WRITE_EXCLUSIVE (0x0000000Fu)
00395
00396 #define EDMA3_TCRL_ERRDET_RESETVAL (0x00000000u)
00397
00398
00399
00400 #define EDMA3_TCRL_ERRCMD_SET_MASK (0x00000002u)
00401 #define EDMA3_TCRL_ERRCMD_SET_SHIFT (0x00000001u)
00402 #define EDMA3_TCRL_ERRCMD_SET_RESETVAL (0x00000000u)
00403
00404
00405 #define EDMA3_TCRL_ERRCMD_SET_SET (0x00000001u)
00406
00407 #define EDMA3_TCRL_ERRCMD_EVAL_MASK (0x00000001u)
00408 #define EDMA3_TCRL_ERRCMD_EVAL_SHIFT (0x00000000u)
00409 #define EDMA3_TCRL_ERRCMD_EVAL_RESETVAL (0x00000000u)
00410
00411
00412 #define EDMA3_TCRL_ERRCMD_EVAL_EVAL (0x00000001u)
00413
00414 #define EDMA3_TCRL_ERRCMD_RESETVAL (0x00000000u)
00415
00416
00417
00418 #define EDMA3_TCRL_RDRATE_RDRATE_MASK (0x00000007u)
00419 #define EDMA3_TCRL_RDRATE_RDRATE_SHIFT (0x00000000u)
00420 #define EDMA3_TCRL_RDRATE_RDRATE_RESETVAL (0x00000000u)
00421
00422
00423 #define EDMA3_TCRL_RDRATE_RDRATE_AFAP (0x00000000u)
00424 #define EDMA3_TCRL_RDRATE_RDRATE_4CYCLE (0x00000001u)
00425 #define EDMA3_TCRL_RDRATE_RDRATE_8CYCLE (0x00000002u)
00426 #define EDMA3_TCRL_RDRATE_RDRATE_16CYCLE (0x00000003u)
00427 #define EDMA3_TCRL_RDRATE_RDRATE_32CYCLE (0x00000004u)
00428
00429 #define EDMA3_TCRL_RDRATE_RESETVAL (0x00000000u)
00430
00431
00432
00433 #define EDMA3_TCRL_POPT_TCCHEN_MASK (0x00400000u)
00434 #define EDMA3_TCRL_POPT_TCCHEN_SHIFT (0x00000016u)
00435 #define EDMA3_TCRL_POPT_TCCHEN_RESETVAL (0x00000000u)
00436
00437
00438 #define EDMA3_TCRL_POPT_TCCHEN_DISABLE (0x00000000u)
00439 #define EDMA3_TCRL_POPT_TCCHEN_ENABLE (0x00000001u)
00440
00441 #define EDMA3_TCRL_POPT_TCINTEN_MASK (0x00100000u)
00442 #define EDMA3_TCRL_POPT_TCINTEN_SHIFT (0x00000014u)
00443 #define EDMA3_TCRL_POPT_TCINTEN_RESETVAL (0x00000000u)
00444
00445
00446 #define EDMA3_TCRL_POPT_TCINTEN_DISABLE (0x00000000u)
00447 #define EDMA3_TCRL_POPT_TCINTEN_ENABLE (0x00000001u)
00448
00449 #define EDMA3_TCRL_POPT_TCC_MASK (0x0003F000u)
00450 #define EDMA3_TCRL_POPT_TCC_SHIFT (0x0000000Cu)
00451 #define EDMA3_TCRL_POPT_TCC_RESETVAL (0x00000000u)
00452
00453 #define EDMA3_TCRL_POPT_FWID_MASK (0x00000700u)
00454 #define EDMA3_TCRL_POPT_FWID_SHIFT (0x00000008u)
00455 #define EDMA3_TCRL_POPT_FWID_RESETVAL (0x00000000u)
00456
00457
00458 #define EDMA3_TCRL_POPT_FWID_8BIT (0x00000000u)
00459 #define EDMA3_TCRL_POPT_FWID_16BIT (0x00000001u)
00460 #define EDMA3_TCRL_POPT_FWID_32BIT (0x00000002u)
00461 #define EDMA3_TCRL_POPT_FWID_64BIT (0x00000003u)
00462 #define EDMA3_TCRL_POPT_FWID_128BIT (0x00000004u)
00463 #define EDMA3_TCRL_POPT_FWID_256BIT (0x00000005u)
00464
00465 #define EDMA3_TCRL_POPT_PRI_MASK (0x00000070u)
00466 #define EDMA3_TCRL_POPT_PRI_SHIFT (0x00000004u)
00467 #define EDMA3_TCRL_POPT_PRI_RESETVAL (0x00000000u)
00468
00469 #define EDMA3_TCRL_POPT_DAM_MASK (0x00000002u)
00470 #define EDMA3_TCRL_POPT_DAM_SHIFT (0x00000001u)
00471 #define EDMA3_TCRL_POPT_DAM_RESETVAL (0x00000000u)
00472
00473
00474 #define EDMA3_TCRL_POPT_DAM_INCR (0x00000000u)
00475 #define EDMA3_TCRL_POPT_DAM_FIFO (0x00000001u)
00476
00477 #define EDMA3_TCRL_POPT_SAM_MASK (0x00000001u)
00478 #define EDMA3_TCRL_POPT_SAM_SHIFT (0x00000000u)
00479 #define EDMA3_TCRL_POPT_SAM_RESETVAL (0x00000000u)
00480
00481
00482 #define EDMA3_TCRL_POPT_SAM_INCR (0x00000000u)
00483 #define EDMA3_TCRL_POPT_SAM_FIFO (0x00000001u)
00484
00485 #define EDMA3_TCRL_POPT_RESETVAL (0x00000000u)
00486
00487
00488
00489 #define EDMA3_TCRL_PSRC_SADDR_MASK (0xFFFFFFFFu)
00490 #define EDMA3_TCRL_PSRC_SADDR_SHIFT (0x00000000u)
00491 #define EDMA3_TCRL_PSRC_SADDR_RESETVAL (0x00000000u)
00492
00493 #define EDMA3_TCRL_PSRC_RESETVAL (0x00000000u)
00494
00495
00496
00497 #define EDMA3_TCRL_PCNT_BCNT_MASK (0xFFFF0000u)
00498 #define EDMA3_TCRL_PCNT_BCNT_SHIFT (0x00000010u)
00499 #define EDMA3_TCRL_PCNT_BCNT_RESETVAL (0x00000000u)
00500
00501 #define EDMA3_TCRL_PCNT_ACNT_MASK (0x0000FFFFu)
00502 #define EDMA3_TCRL_PCNT_ACNT_SHIFT (0x00000000u)
00503 #define EDMA3_TCRL_PCNT_ACNT_RESETVAL (0x00000000u)
00504
00505 #define EDMA3_TCRL_PCNT_RESETVAL (0x00000000u)
00506
00507
00508
00509 #define EDMA3_TCRL_PDST_DADDR_MASK (0xFFFFFFFFu)
00510 #define EDMA3_TCRL_PDST_DADDR_SHIFT (0x00000000u)
00511 #define EDMA3_TCRL_PDST_DADDR_RESETVAL (0x00000000u)
00512
00513 #define EDMA3_TCRL_PDST_RESETVAL (0x00000000u)
00514
00515
00516
00517 #define EDMA3_TCRL_PBIDX_DBIDX_MASK (0xFFFF0000u)
00518 #define EDMA3_TCRL_PBIDX_DBIDX_SHIFT (0x00000010u)
00519 #define EDMA3_TCRL_PBIDX_DBIDX_RESETVAL (0x00000000u)
00520
00521 #define EDMA3_TCRL_PBIDX_SBIDX_MASK (0x0000FFFFu)
00522 #define EDMA3_TCRL_PBIDX_SBIDX_SHIFT (0x00000000u)
00523 #define EDMA3_TCRL_PBIDX_SBIDX_RESETVAL (0x00000000u)
00524
00525 #define EDMA3_TCRL_PBIDX_RESETVAL (0x00000000u)
00526
00527
00528
00529 #define EDMA3_TCRL_PMPPRXY_PRIV_MASK (0x00000100u)
00530 #define EDMA3_TCRL_PMPPRXY_PRIV_SHIFT (0x00000008u)
00531 #define EDMA3_TCRL_PMPPRXY_PRIV_RESETVAL (0x00000000u)
00532
00533
00534 #define EDMA3_TCRL_PMPPRXY_PRIV_USER (0x00000000u)
00535 #define EDMA3_TCRL_PMPPRXY_PRIV_SUPERVISOR (0x00000001u)
00536
00537 #define EDMA3_TCRL_PMPPRXY_PRIVID_MASK (0x0000000Fu)
00538 #define EDMA3_TCRL_PMPPRXY_PRIVID_SHIFT (0x00000000u)
00539 #define EDMA3_TCRL_PMPPRXY_PRIVID_RESETVAL (0x00000000u)
00540
00541 #define EDMA3_TCRL_PMPPRXY_RESETVAL (0x00000000u)
00542
00543
00544
00545 #define EDMA3_TCRL_SAOPT_TCCHEN_MASK (0x00400000u)
00546 #define EDMA3_TCRL_SAOPT_TCCHEN_SHIFT (0x00000016u)
00547 #define EDMA3_TCRL_SAOPT_TCCHEN_RESETVAL (0x00000000u)
00548
00549
00550 #define EDMA3_TCRL_SAOPT_TCCHEN_DISABLE (0x00000000u)
00551 #define EDMA3_TCRL_SAOPT_TCCHEN_ENABLE (0x00000001u)
00552
00553 #define EDMA3_TCRL_SAOPT_TCINTEN_MASK (0x00100000u)
00554 #define EDMA3_TCRL_SAOPT_TCINTEN_SHIFT (0x00000014u)
00555 #define EDMA3_TCRL_SAOPT_TCINTEN_RESETVAL (0x00000000u)
00556
00557
00558 #define EDMA3_TCRL_SAOPT_TCINTEN_DISABLE (0x00000000u)
00559 #define EDMA3_TCRL_SAOPT_TCINTEN_ENABLE (0x00000001u)
00560
00561 #define EDMA3_TCRL_SAOPT_TCC_MASK (0x0003F000u)
00562 #define EDMA3_TCRL_SAOPT_TCC_SHIFT (0x0000000Cu)
00563 #define EDMA3_TCRL_SAOPT_TCC_RESETVAL (0x00000000u)
00564
00565 #define EDMA3_TCRL_SAOPT_FWID_MASK (0x00000700u)
00566 #define EDMA3_TCRL_SAOPT_FWID_SHIFT (0x00000008u)
00567 #define EDMA3_TCRL_SAOPT_FWID_RESETVAL (0x00000000u)
00568
00569
00570 #define EDMA3_TCRL_SAOPT_FWID_8BIT (0x00000000u)
00571 #define EDMA3_TCRL_SAOPT_FWID_16BIT (0x00000001u)
00572 #define EDMA3_TCRL_SAOPT_FWID_32BIT (0x00000002u)
00573 #define EDMA3_TCRL_SAOPT_FWID_64BIT (0x00000003u)
00574 #define EDMA3_TCRL_SAOPT_FWID_128BIT (0x00000004u)
00575 #define EDMA3_TCRL_SAOPT_FWID_256BIT (0x00000005u)
00576
00577 #define EDMA3_TCRL_SAOPT_PRI_MASK (0x00000070u)
00578 #define EDMA3_TCRL_SAOPT_PRI_SHIFT (0x00000004u)
00579 #define EDMA3_TCRL_SAOPT_PRI_RESETVAL (0x00000000u)
00580
00581 #define EDMA3_TCRL_SAOPT_DAM_MASK (0x00000002u)
00582 #define EDMA3_TCRL_SAOPT_DAM_SHIFT (0x00000001u)
00583 #define EDMA3_TCRL_SAOPT_DAM_RESETVAL (0x00000000u)
00584
00585
00586 #define EDMA3_TCRL_SAOPT_DAM_INCR (0x00000000u)
00587 #define EDMA3_TCRL_SAOPT_DAM_FIFO (0x00000001u)
00588
00589 #define EDMA3_TCRL_SAOPT_SAM_MASK (0x00000001u)
00590 #define EDMA3_TCRL_SAOPT_SAM_SHIFT (0x00000000u)
00591 #define EDMA3_TCRL_SAOPT_SAM_RESETVAL (0x00000000u)
00592
00593
00594 #define EDMA3_TCRL_SAOPT_SAM_INCR (0x00000000u)
00595 #define EDMA3_TCRL_SAOPT_SAM_FIFO (0x00000001u)
00596
00597 #define EDMA3_TCRL_SAOPT_RESETVAL (0x00000000u)
00598
00599
00600
00601 #define EDMA3_TCRL_SASRC_SADDR_MASK (0xFFFFFFFFu)
00602 #define EDMA3_TCRL_SASRC_SADDR_SHIFT (0x00000000u)
00603 #define EDMA3_TCRL_SASRC_SADDR_RESETVAL (0x00000000u)
00604
00605 #define EDMA3_TCRL_SASRC_RESETVAL (0x00000000u)
00606
00607
00608
00609 #define EDMA3_TCRL_SACNT_BCNT_MASK (0xFFFF0000u)
00610 #define EDMA3_TCRL_SACNT_BCNT_SHIFT (0x00000010u)
00611 #define EDMA3_TCRL_SACNT_BCNT_RESETVAL (0x00000000u)
00612
00613 #define EDMA3_TCRL_SACNT_ACNT_MASK (0x0000FFFFu)
00614 #define EDMA3_TCRL_SACNT_ACNT_SHIFT (0x00000000u)
00615 #define EDMA3_TCRL_SACNT_ACNT_RESETVAL (0x00000000u)
00616
00617 #define EDMA3_TCRL_SACNT_RESETVAL (0x00000000u)
00618
00619
00620
00621 #define EDMA3_TCRL_SADST_RESETVAL (0x00000000u)
00622
00623
00624
00625 #define EDMA3_TCRL_SABIDX_DBIDX_MASK (0xFFFF0000u)
00626 #define EDMA3_TCRL_SABIDX_DBIDX_SHIFT (0x00000010u)
00627 #define EDMA3_TCRL_SABIDX_DBIDX_RESETVAL (0x00000000u)
00628
00629 #define EDMA3_TCRL_SABIDX_SBIDX_MASK (0x0000FFFFu)
00630 #define EDMA3_TCRL_SABIDX_SBIDX_SHIFT (0x00000000u)
00631 #define EDMA3_TCRL_SABIDX_SBIDX_RESETVAL (0x00000000u)
00632
00633 #define EDMA3_TCRL_SABIDX_RESETVAL (0x00000000u)
00634
00635
00636
00637 #define EDMA3_TCRL_SAMPPRXY_PRIV_MASK (0x00000100u)
00638 #define EDMA3_TCRL_SAMPPRXY_PRIV_SHIFT (0x00000008u)
00639 #define EDMA3_TCRL_SAMPPRXY_PRIV_RESETVAL (0x00000000u)
00640
00641
00642 #define EDMA3_TCRL_SAMPPRXY_PRIV_USER (0x00000000u)
00643 #define EDMA3_TCRL_SAMPPRXY_PRIV_SUPERVISOR (0x00000001u)
00644
00645 #define EDMA3_TCRL_SAMPPRXY_PRIVID_MASK (0x0000000Fu)
00646 #define EDMA3_TCRL_SAMPPRXY_PRIVID_SHIFT (0x00000000u)
00647 #define EDMA3_TCRL_SAMPPRXY_PRIVID_RESETVAL (0x00000000u)
00648
00649 #define EDMA3_TCRL_SAMPPRXY_RESETVAL (0x00000000u)
00650
00651
00652
00653 #define EDMA3_TCRL_SACNTRLD_ACNTRLD_MASK (0x0000FFFFu)
00654 #define EDMA3_TCRL_SACNTRLD_ACNTRLD_SHIFT (0x00000000u)
00655 #define EDMA3_TCRL_SACNTRLD_ACNTRLD_RESETVAL (0x00000000u)
00656
00657 #define EDMA3_TCRL_SACNTRLD_RESETVAL (0x00000000u)
00658
00659
00660
00661 #define EDMA3_TCRL_SASRCBREF_SADDRBREFG_MASK (0xFFFFFFFFu)
00662 #define EDMA3_TCRL_SASRCBREF_SADDRBREFG_SHIFT (0x00000000u)
00663 #define EDMA3_TCRL_SASRCBREF_SADDRBREFG_RESETVAL (0x00000000u)
00664
00665 #define EDMA3_TCRL_SASRCBREF_RESETVAL (0x00000000u)
00666
00667
00668
00669 #define EDMA3_TCRL_SADSTBREF_RESETVAL (0x00000000u)
00670
00671
00672
00673 #define EDMA3_TCRL_DFCNTRLD_ACNTRLD_MASK (0x0000FFFFu)
00674 #define EDMA3_TCRL_DFCNTRLD_ACNTRLD_SHIFT (0x00000000u)
00675 #define EDMA3_TCRL_DFCNTRLD_ACNTRLD_RESETVAL (0x00000000u)
00676
00677 #define EDMA3_TCRL_DFCNTRLD_RESETVAL (0x00000000u)
00678
00679
00680
00681 #define EDMA3_TCRL_DFSRCBREF_RESETVAL (0x00000000u)
00682
00683
00684
00685 #define EDMA3_TCRL_DFDSTBREF_DADDRBREF_MASK (0xFFFFFFFFu)
00686 #define EDMA3_TCRL_DFDSTBREF_DADDRBREF_SHIFT (0x00000000u)
00687 #define EDMA3_TCRL_DFDSTBREF_DADDRBREF_RESETVAL (0x00000000u)
00688
00689 #define EDMA3_TCRL_DFDSTBREF_RESETVAL (0x00000000u)
00690
00691
00692
00693 #define EDMA3_TCRL_DFOPT_TCCHEN_MASK (0x00400000u)
00694 #define EDMA3_TCRL_DFOPT_TCCHEN_SHIFT (0x00000016u)
00695 #define EDMA3_TCRL_DFOPT_TCCHEN_RESETVAL (0x00000000u)
00696
00697
00698 #define EDMA3_TCRL_DFOPT_TCCHEN_DISABLE (0x00000000u)
00699 #define EDMA3_TCRL_DFOPT_TCCHEN_ENABLE (0x00000001u)
00700
00701 #define EDMA3_TCRL_DFOPT_TCINTEN_MASK (0x00100000u)
00702 #define EDMA3_TCRL_DFOPT_TCINTEN_SHIFT (0x00000014u)
00703 #define EDMA3_TCRL_DFOPT_TCINTEN_RESETVAL (0x00000000u)
00704
00705
00706 #define EDMA3_TCRL_DFOPT_TCINTEN_DISABLE (0x00000000u)
00707 #define EDMA3_TCRL_DFOPT_TCINTEN_ENABLE (0x00000001u)
00708
00709 #define EDMA3_TCRL_DFOPT_TCC_MASK (0x0003F000u)
00710 #define EDMA3_TCRL_DFOPT_TCC_SHIFT (0x0000000Cu)
00711 #define EDMA3_TCRL_DFOPT_TCC_RESETVAL (0x00000000u)
00712
00713 #define EDMA3_TCRL_DFOPT_FWID_MASK (0x00000700u)
00714 #define EDMA3_TCRL_DFOPT_FWID_SHIFT (0x00000008u)
00715 #define EDMA3_TCRL_DFOPT_FWID_RESETVAL (0x00000000u)
00716
00717
00718 #define EDMA3_TCRL_DFOPT_FWID_8BIT (0x00000000u)
00719 #define EDMA3_TCRL_DFOPT_FWID_16BIT (0x00000001u)
00720 #define EDMA3_TCRL_DFOPT_FWID_32BIT (0x00000002u)
00721 #define EDMA3_TCRL_DFOPT_FWID_64BIT (0x00000003u)
00722 #define EDMA3_TCRL_DFOPT_FWID_128BIT (0x00000004u)
00723 #define EDMA3_TCRL_DFOPT_FWID_256BIT (0x00000005u)
00724
00725 #define EDMA3_TCRL_DFOPT_PRI_MASK (0x00000070u)
00726 #define EDMA3_TCRL_DFOPT_PRI_SHIFT (0x00000004u)
00727 #define EDMA3_TCRL_DFOPT_PRI_RESETVAL (0x00000000u)
00728
00729 #define EDMA3_TCRL_DFOPT_DAM_MASK (0x00000002u)
00730 #define EDMA3_TCRL_DFOPT_DAM_SHIFT (0x00000001u)
00731 #define EDMA3_TCRL_DFOPT_DAM_RESETVAL (0x00000000u)
00732
00733
00734 #define EDMA3_TCRL_DFOPT_DAM_INCR (0x00000000u)
00735 #define EDMA3_TCRL_DFOPT_DAM_FIFO (0x00000001u)
00736
00737 #define EDMA3_TCRL_DFOPT_SAM_MASK (0x00000001u)
00738 #define EDMA3_TCRL_DFOPT_SAM_SHIFT (0x00000000u)
00739 #define EDMA3_TCRL_DFOPT_SAM_RESETVAL (0x00000000u)
00740
00741
00742 #define EDMA3_TCRL_DFOPT_SAM_INCR (0x00000000u)
00743 #define EDMA3_TCRL_DFOPT_SAM_FIFO (0x00000001u)
00744
00745 #define EDMA3_TCRL_DFOPT_RESETVAL (0x00000000u)
00746
00747
00748
00749 #define EDMA3_TCRL_DFSRC_RESETVAL (0x00000000u)
00750
00751
00752
00753 #define EDMA3_TCRL_DFCNT_BCNT_MASK (0xFFFF0000u)
00754 #define EDMA3_TCRL_DFCNT_BCNT_SHIFT (0x00000010u)
00755 #define EDMA3_TCRL_DFCNT_BCNT_RESETVAL (0x00000000u)
00756
00757 #define EDMA3_TCRL_DFCNT_ACNT_MASK (0x0000FFFFu)
00758 #define EDMA3_TCRL_DFCNT_ACNT_SHIFT (0x00000000u)
00759 #define EDMA3_TCRL_DFCNT_ACNT_RESETVAL (0x00000000u)
00760
00761 #define EDMA3_TCRL_DFCNT_RESETVAL (0x00000000u)
00762
00763
00764
00765 #define EDMA3_TCRL_DFDST_DADDR_MASK (0xFFFFFFFFu)
00766 #define EDMA3_TCRL_DFDST_DADDR_SHIFT (0x00000000u)
00767 #define EDMA3_TCRL_DFDST_DADDR_RESETVAL (0x00000000u)
00768
00769 #define EDMA3_TCRL_DFDST_RESETVAL (0x00000000u)
00770
00771
00772
00773 #define EDMA3_TCRL_DFBIDX_DBIDX_MASK (0xFFFF0000u)
00774 #define EDMA3_TCRL_DFBIDX_DBIDX_SHIFT (0x00000010u)
00775 #define EDMA3_TCRL_DFBIDX_DBIDX_RESETVAL (0x00000000u)
00776
00777 #define EDMA3_TCRL_DFBIDX_SBIDX_MASK (0x0000FFFFu)
00778 #define EDMA3_TCRL_DFBIDX_SBIDX_SHIFT (0x00000000u)
00779 #define EDMA3_TCRL_DFBIDX_SBIDX_RESETVAL (0x00000000u)
00780
00781 #define EDMA3_TCRL_DFBIDX_RESETVAL (0x00000000u)
00782
00783
00784
00785 #define EDMA3_TCRL_DFMPPRXY_PRIV_MASK (0x00000100u)
00786 #define EDMA3_TCRL_DFMPPRXY_PRIV_SHIFT (0x00000008u)
00787 #define EDMA3_TCRL_DFMPPRXY_PRIV_RESETVAL (0x00000000u)
00788
00789
00790 #define EDMA3_TCRL_DFMPPRXY_PRIV_USER (0x00000000u)
00791 #define EDMA3_TCRL_DFMPPRXY_PRIV_SUPERVISOR (0x00000001u)
00792
00793 #define EDMA3_TCRL_DFMPPRXY_PRIVID_MASK (0x0000000Fu)
00794 #define EDMA3_TCRL_DFMPPRXY_PRIVID_SHIFT (0x00000000u)
00795 #define EDMA3_TCRL_DFMPPRXY_PRIVID_RESETVAL (0x00000000u)
00796
00797 #define EDMA3_TCRL_DFMPPRXY_RESETVAL (0x00000000u)
00798
00799 #ifdef __cplusplus
00800 }
00801 #endif
00802
00803 #endif