EDMA3 Resource Manager: edma3_rl

00001 /*
00002  * edma3_rl_cc.h
00003  *
00004  * EDMA3 Channel Controller Register Desciption.
00005  *
00006  * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
00007  *
00008  *
00009  *  Redistribution and use in source and binary forms, with or without
00010  *  modification, are permitted provided that the following conditions
00011  *  are met:
00012  *
00013  *    Redistributions of source code must retain the above copyright
00014  *    notice, this list of conditions and the following disclaimer.
00015  *
00016  *    Redistributions in binary form must reproduce the above copyright
00017  *    notice, this list of conditions and the following disclaimer in the
00018  *    documentation and/or other materials provided with the
00019  *    distribution.
00020  *
00021  *    Neither the name of Texas Instruments Incorporated nor the names of
00022  *    its contributors may be used to endorse or promote products derived
00023  *    from this software without specific prior written permission.
00024  *
00025  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
00026  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00027  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
00028  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
00029  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
00030  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00031  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
00032  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
00033  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00034  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00035  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00036  *
00037 */
00038 
00039 #ifndef _EDMA3_RL_CC_H_
00040 #define _EDMA3_RL_CC_H_
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /**************************************************************************\
00047 * Register Overlay Structure for DRA
00048 \**************************************************************************/
00049 typedef struct  {
00050     volatile unsigned int DRAE;
00051     volatile unsigned int DRAEH;
00052 } EDMA3_CCRL_DraRegs;
00053 
00054 /**************************************************************************\
00055 * Register Overlay Structure for QUEEVTENTRY
00056 \**************************************************************************/
00057 typedef struct  {
00058     volatile unsigned int QUEEVT_ENTRY;
00059 } EDMA3_CCRL_QueevtentryRegs;
00060 
00061 /**************************************************************************\
00062 * Register Overlay Structure for SHADOW
00063 \**************************************************************************/
00064 typedef struct  {
00065     volatile unsigned int ER;
00066     volatile unsigned int ERH;
00067     volatile unsigned int ECR;
00068     volatile unsigned int ECRH;
00069     volatile unsigned int ESR;
00070     volatile unsigned int ESRH;
00071     volatile unsigned int CER;
00072     volatile unsigned int CERH;
00073     volatile unsigned int EER;
00074     volatile unsigned int EERH;
00075     volatile unsigned int EECR;
00076     volatile unsigned int EECRH;
00077     volatile unsigned int EESR;
00078     volatile unsigned int EESRH;
00079     volatile unsigned int SER;
00080     volatile unsigned int SERH;
00081     volatile unsigned int SECR;
00082     volatile unsigned int SECRH;
00083     volatile unsigned char RSVD0[8];
00084     volatile unsigned int IER;
00085     volatile unsigned int IERH;
00086     volatile unsigned int IECR;
00087     volatile unsigned int IECRH;
00088     volatile unsigned int IESR;
00089     volatile unsigned int IESRH;
00090     volatile unsigned int IPR;
00091     volatile unsigned int IPRH;
00092     volatile unsigned int ICR;
00093     volatile unsigned int ICRH;
00094     volatile unsigned int IEVAL;
00095     volatile unsigned char RSVD1[4];
00096     volatile unsigned int QER;
00097     volatile unsigned int QEER;
00098     volatile unsigned int QEECR;
00099     volatile unsigned int QEESR;
00100     volatile unsigned int QSER;
00101     volatile unsigned int QSECR;
00102     volatile unsigned char RSVD2[360];
00103 } EDMA3_CCRL_ShadowRegs;
00104 
00105 typedef volatile EDMA3_CCRL_ShadowRegs  *EDMA3_CCRL_ShadowRegsOvly;
00106 
00107 /**************************************************************************\
00108 * Register Overlay Structure for PARAMENTRY
00109 \**************************************************************************/
00110 typedef struct  {
00111     volatile unsigned int OPT;
00112     volatile unsigned int SRC;
00113     volatile unsigned int A_B_CNT;
00114     volatile unsigned int DST;
00115     volatile unsigned int SRC_DST_BIDX;
00116     volatile unsigned int LINK_BCNTRLD;
00117     volatile unsigned int SRC_DST_CIDX;
00118     volatile unsigned int CCNT;
00119 } EDMA3_CCRL_ParamentryRegs;
00120 typedef volatile EDMA3_CCRL_ParamentryRegs  *EDMA3_CCRL_ParamentryRegsOvly;
00121 
00122 /**************************************************************************\
00123 * Register Overlay Structure
00124 \**************************************************************************/
00125 typedef struct  {
00126     volatile unsigned int REV;
00127     volatile unsigned int CCCFG;
00128     volatile unsigned char RSVD0[248];
00129     volatile unsigned int DCHMAP[64];
00130     volatile unsigned int QCHMAP[8];
00131     volatile unsigned char RSVD1[32];
00132     volatile unsigned int DMAQNUM[8];
00133     volatile unsigned int QDMAQNUM;
00134     volatile unsigned char RSVD2[28];
00135     volatile unsigned int QUETCMAP;
00136     volatile unsigned int QUEPRI;
00137     volatile unsigned char RSVD3[120];
00138     volatile unsigned int EMR;
00139     volatile unsigned int EMRH;
00140     volatile unsigned int EMCR;
00141     volatile unsigned int EMCRH;
00142     volatile unsigned int QEMR;
00143     volatile unsigned int QEMCR;
00144     volatile unsigned int CCERR;
00145     volatile unsigned int CCERRCLR;
00146     volatile unsigned int EEVAL;
00147     volatile unsigned char RSVD4[28];
00148     EDMA3_CCRL_DraRegs DRA[8];
00149     volatile unsigned int QRAE[8];
00150     volatile unsigned char RSVD5[96];
00151     EDMA3_CCRL_QueevtentryRegs QUEEVTENTRY[8][16];
00152     volatile unsigned int QSTAT[8];
00153     volatile unsigned int QWMTHRA;
00154     volatile unsigned int QWMTHRB;
00155     volatile unsigned char RSVD6[24];
00156     volatile unsigned int CCSTAT;
00157     volatile unsigned char RSVD7[188];
00158     volatile unsigned int AETCTL;
00159     volatile unsigned int AETSTAT;
00160     volatile unsigned int AETCMD;
00161     volatile unsigned char RSVD8[244];
00162     volatile unsigned int MPFAR;
00163     volatile unsigned int MPFSR;
00164     volatile unsigned int MPFCR;
00165     volatile unsigned int MPPAG;
00166     volatile unsigned int MPPA[8];
00167     volatile unsigned char RSVD9[2000];
00168     volatile unsigned int ER;
00169     volatile unsigned int ERH;
00170     volatile unsigned int ECR;
00171     volatile unsigned int ECRH;
00172     volatile unsigned int ESR;
00173     volatile unsigned int ESRH;
00174     volatile unsigned int CER;
00175     volatile unsigned int CERH;
00176     volatile unsigned int EER;
00177     volatile unsigned int EERH;
00178     volatile unsigned int EECR;
00179     volatile unsigned int EECRH;
00180     volatile unsigned int EESR;
00181     volatile unsigned int EESRH;
00182     volatile unsigned int SER;
00183     volatile unsigned int SERH;
00184     volatile unsigned int SECR;
00185     volatile unsigned int SECRH;
00186     volatile unsigned char RSVD10[8];
00187     volatile unsigned int IER;
00188     volatile unsigned int IERH;
00189     volatile unsigned int IECR;
00190     volatile unsigned int IECRH;
00191     volatile unsigned int IESR;
00192     volatile unsigned int IESRH;
00193     volatile unsigned int IPR;
00194     volatile unsigned int IPRH;
00195     volatile unsigned int ICR;
00196     volatile unsigned int ICRH;
00197     volatile unsigned int IEVAL;
00198     volatile unsigned char RSVD11[4];
00199     volatile unsigned int QER;
00200     volatile unsigned int QEER;
00201     volatile unsigned int QEECR;
00202     volatile unsigned int QEESR;
00203     volatile unsigned int QSER;
00204     volatile unsigned int QSECR;
00205     volatile unsigned char RSVD12[3944];
00206     EDMA3_CCRL_ShadowRegs SHADOW[8];
00207     volatile unsigned char RSVD13[4096];
00208     EDMA3_CCRL_ParamentryRegs PARAMENTRY[512];
00209 } EDMA3_CCRL_Regs;
00210 
00211 typedef volatile EDMA3_CCRL_Regs  *EDMA3_CCRL_RegsOvly;
00212 
00213 
00214 /**************************************************************************\
00215 * Field Definition Macros
00216 \**************************************************************************/
00217 
00218 /* REV */
00219 
00220 #define EDMA3_CCRL_REV_TYPE_MASK         (0x00FF0000u)
00221 #define EDMA3_CCRL_REV_TYPE_SHIFT        (0x00000010u)
00222 #define EDMA3_CCRL_REV_TYPE_RESETVAL     (0x00000007u)
00223 
00224 #define EDMA3_CCRL_REV_CLASS_MASK        (0x0000FF00u)
00225 #define EDMA3_CCRL_REV_CLASS_SHIFT       (0x00000008u)
00226 #define EDMA3_CCRL_REV_CLASS_RESETVAL    (0x00000004u)
00227 
00228 #define EDMA3_CCRL_REV_RESERVED_MASK     (0x000000FFu)
00229 #define EDMA3_CCRL_REV_RESERVED_SHIFT    (0x00000000u)
00230 #define EDMA3_CCRL_REV_RESERVED_RESETVAL (0x00000000u)
00231 
00232 #define EDMA3_CCRL_REV_RESETVAL          (0x00070400u)
00233 
00234 /* CCCFG */
00235 
00236 #define EDMA3_CCRL_CCCFG_MP_EXIST_MASK   (0x02000000u)
00237 #define EDMA3_CCRL_CCCFG_MP_EXIST_SHIFT  (0x00000019u)
00238 #define EDMA3_CCRL_CCCFG_MP_EXIST_RESETVAL (0x00000000u)
00239 
00240 /*----MP_EXIST Tokens----*/
00241 #define EDMA3_CCRL_CCCFG_MP_EXIST_NONE   (0x00000000u)
00242 #define EDMA3_CCRL_CCCFG_MP_EXIST_INCLUDED (0x00000001u)
00243 
00244 #define EDMA3_CCRL_CCCFG_CHMAP_EXIST_MASK (0x01000000u)
00245 #define EDMA3_CCRL_CCCFG_CHMAP_EXIST_SHIFT (0x00000018u)
00246 #define EDMA3_CCRL_CCCFG_CHMAP_EXIST_RESETVAL (0x00000000u)
00247 
00248 /*----CHMAP_EXIST Tokens----*/
00249 #define EDMA3_CCRL_CCCFG_CHMAP_EXIST_NONE (0x00000000u)
00250 #define EDMA3_CCRL_CCCFG_CHMAP_EXIST_INCLUDED (0x00000001u)
00251 
00252 #define EDMA3_CCRL_CCCFG_NUM_REGN_MASK   (0x00300000u)
00253 #define EDMA3_CCRL_CCCFG_NUM_REGN_SHIFT  (0x00000014u)
00254 #define EDMA3_CCRL_CCCFG_NUM_REGN_RESETVAL (0x00000000u)
00255 
00256 /*----NUM_REGN Tokens----*/
00257 #define EDMA3_CCRL_CCCFG_NUM_REGN_0      (0x00000000u)
00258 #define EDMA3_CCRL_CCCFG_NUM_REGN_2      (0x00000001u)
00259 #define EDMA3_CCRL_CCCFG_NUM_REGN_4      (0x00000002u)
00260 #define EDMA3_CCRL_CCCFG_NUM_REGN_8      (0x00000003u)
00261 
00262 #define EDMA3_CCRL_CCCFG_NUM_TC_MASK     (0x00070000u)
00263 #define EDMA3_CCRL_CCCFG_NUM_TC_SHIFT    (0x00000010u)
00264 #define EDMA3_CCRL_CCCFG_NUM_TC_RESETVAL (0x00000000u)
00265 
00266 /*----NUM_TC Tokens----*/
00267 #define EDMA3_CCRL_CCCFG_NUM_TC_1        (0x00000000u)
00268 #define EDMA3_CCRL_CCCFG_NUM_TC_2        (0x00000001u)
00269 #define EDMA3_CCRL_CCCFG_NUM_TC_3        (0x00000002u)
00270 #define EDMA3_CCRL_CCCFG_NUM_TC_4        (0x00000003u)
00271 #define EDMA3_CCRL_CCCFG_NUM_TC_5        (0x00000004u)
00272 #define EDMA3_CCRL_CCCFG_NUM_TC_6        (0x00000005u)
00273 #define EDMA3_CCRL_CCCFG_NUM_TC_7        (0x00000006u)
00274 #define EDMA3_CCRL_CCCFG_NUM_TC_8        (0x00000007u)
00275 
00276 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_MASK (0x00007000u)
00277 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_SHIFT (0x0000000Cu)
00278 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_RESETVAL (0x00000000u)
00279 
00280 /*----NUM_PAENTRY Tokens----*/
00281 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_16  (0x00000000u)
00282 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_32  (0x00000001u)
00283 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_64  (0x00000002u)
00284 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_128 (0x00000003u)
00285 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_256 (0x00000004u)
00286 #define EDMA3_CCRL_CCCFG_NUM_PAENTRY_512 (0x00000005u)
00287 
00288 #define EDMA3_CCRL_CCCFG_NUM_INTCH_MASK  (0x00000700u)
00289 #define EDMA3_CCRL_CCCFG_NUM_INTCH_SHIFT (0x00000008u)
00290 #define EDMA3_CCRL_CCCFG_NUM_INTCH_RESETVAL (0x00000000u)
00291 
00292 /*----NUM_INTCH Tokens----*/
00293 #define EDMA3_CCRL_CCCFG_NUM_INTCH_8     (0x00000001u)
00294 #define EDMA3_CCRL_CCCFG_NUM_INTCH_16    (0x00000002u)
00295 #define EDMA3_CCRL_CCCFG_NUM_INTCH_32    (0x00000003u)
00296 #define EDMA3_CCRL_CCCFG_NUM_INTCH_64    (0x00000004u)
00297 
00298 #define EDMA3_CCRL_CCCFG_NUM_QDMACH_MASK (0x00000070u)
00299 #define EDMA3_CCRL_CCCFG_NUM_QDMACH_SHIFT (0x00000004u)
00300 #define EDMA3_CCRL_CCCFG_NUM_QDMACH_RESETVAL (0x00000000u)
00301 
00302 /*----NUM_QDMACH Tokens----*/
00303 #define EDMA3_CCRL_CCCFG_NUM_QDMACH_NONE (0x00000000u)
00304 #define EDMA3_CCRL_CCCFG_NUM_QDMACH_2    (0x00000001u)
00305 #define EDMA3_CCRL_CCCFG_NUM_QDMACH_4    (0x00000002u)
00306 #define EDMA3_CCRL_CCCFG_NUM_QDMACH_6    (0x00000003u)
00307 #define EDMA3_CCRL_CCCFG_NUM_QDMACH_8    (0x00000004u)
00308 
00309 #define EDMA3_CCRL_CCCFG_NUM_DMACH_MASK  (0x00000007u)
00310 #define EDMA3_CCRL_CCCFG_NUM_DMACH_SHIFT (0x00000000u)
00311 #define EDMA3_CCRL_CCCFG_NUM_DMACH_RESETVAL (0x00000000u)
00312 
00313 /*----NUM_DMACH Tokens----*/
00314 #define EDMA3_CCRL_CCCFG_NUM_DMACH_NONE  (0x00000000u)
00315 #define EDMA3_CCRL_CCCFG_NUM_DMACH_4     (0x00000001u)
00316 #define EDMA3_CCRL_CCCFG_NUM_DMACH_8     (0x00000002u)
00317 #define EDMA3_CCRL_CCCFG_NUM_DMACH_16    (0x00000003u)
00318 #define EDMA3_CCRL_CCCFG_NUM_DMACH_32    (0x00000004u)
00319 #define EDMA3_CCRL_CCCFG_NUM_DMACH_64    (0x00000005u)
00320 
00321 #define EDMA3_CCRL_CCCFG_RESETVAL        (0x00000000u)
00322 
00323 /* DCHMAP */
00324 
00325 #define EDMA3_CCRL_DCHMAP_PAENTRY_MASK   (0x00003FE0u)
00326 #define EDMA3_CCRL_DCHMAP_PAENTRY_SHIFT  (0x00000005u)
00327 #define EDMA3_CCRL_DCHMAP_PAENTRY_RESETVAL (0x00000000u)
00328 
00329 #define EDMA3_CCRL_DCHMAP_RESETVAL       (0x00000000u)
00330 
00331 /* QCHMAP */
00332 
00333 #define EDMA3_CCRL_QCHMAP_PAENTRY_MASK   (0x00003FE0u)
00334 #define EDMA3_CCRL_QCHMAP_PAENTRY_SHIFT  (0x00000005u)
00335 #define EDMA3_CCRL_QCHMAP_PAENTRY_RESETVAL (0x00000000u)
00336 
00337 #define EDMA3_CCRL_QCHMAP_TRWORD_MASK    (0x0000001Cu)
00338 #define EDMA3_CCRL_QCHMAP_TRWORD_SHIFT   (0x00000002u)
00339 #define EDMA3_CCRL_QCHMAP_TRWORD_RESETVAL (0x00000000u)
00340 
00341 #define EDMA3_CCRL_QCHMAP_RESETVAL       (0x00000000u)
00342 
00343 /* DMAQNUM */
00344 
00345 #define EDMA3_CCRL_DMAQNUM_E7_MASK       (0x70000000u)
00346 #define EDMA3_CCRL_DMAQNUM_E7_SHIFT      (0x0000001Cu)
00347 #define EDMA3_CCRL_DMAQNUM_E7_RESETVAL   (0x00000000u)
00348 
00349 #define EDMA3_CCRL_DMAQNUM_E6_MASK       (0x07000000u)
00350 #define EDMA3_CCRL_DMAQNUM_E6_SHIFT      (0x00000018u)
00351 #define EDMA3_CCRL_DMAQNUM_E6_RESETVAL   (0x00000000u)
00352 
00353 #define EDMA3_CCRL_DMAQNUM_E5_MASK       (0x00700000u)
00354 #define EDMA3_CCRL_DMAQNUM_E5_SHIFT      (0x00000014u)
00355 #define EDMA3_CCRL_DMAQNUM_E5_RESETVAL   (0x00000000u)
00356 
00357 #define EDMA3_CCRL_DMAQNUM_E4_MASK       (0x00070000u)
00358 #define EDMA3_CCRL_DMAQNUM_E4_SHIFT      (0x00000010u)
00359 #define EDMA3_CCRL_DMAQNUM_E4_RESETVAL   (0x00000000u)
00360 
00361 #define EDMA3_CCRL_DMAQNUM_E3_MASK       (0x00007000u)
00362 #define EDMA3_CCRL_DMAQNUM_E3_SHIFT      (0x0000000Cu)
00363 #define EDMA3_CCRL_DMAQNUM_E3_RESETVAL   (0x00000000u)
00364 
00365 #define EDMA3_CCRL_DMAQNUM_E2_MASK       (0x00000700u)
00366 #define EDMA3_CCRL_DMAQNUM_E2_SHIFT      (0x00000008u)
00367 #define EDMA3_CCRL_DMAQNUM_E2_RESETVAL   (0x00000000u)
00368 
00369 #define EDMA3_CCRL_DMAQNUM_E1_MASK       (0x00000070u)
00370 #define EDMA3_CCRL_DMAQNUM_E1_SHIFT      (0x00000004u)
00371 #define EDMA3_CCRL_DMAQNUM_E1_RESETVAL   (0x00000000u)
00372 
00373 #define EDMA3_CCRL_DMAQNUM_E0_MASK       (0x00000007u)
00374 #define EDMA3_CCRL_DMAQNUM_E0_SHIFT      (0x00000000u)
00375 #define EDMA3_CCRL_DMAQNUM_E0_RESETVAL   (0x00000000u)
00376 
00377 #define EDMA3_CCRL_DMAQNUM_RESETVAL      (0x00000000u)
00378 
00379 /* QDMAQNUM */
00380 
00381 #define EDMA3_CCRL_QDMAQNUM_E7_MASK      (0x70000000u)
00382 #define EDMA3_CCRL_QDMAQNUM_E7_SHIFT     (0x0000001Cu)
00383 #define EDMA3_CCRL_QDMAQNUM_E7_RESETVAL  (0x00000000u)
00384 
00385 #define EDMA3_CCRL_QDMAQNUM_E6_MASK      (0x07000000u)
00386 #define EDMA3_CCRL_QDMAQNUM_E6_SHIFT     (0x00000018u)
00387 #define EDMA3_CCRL_QDMAQNUM_E6_RESETVAL  (0x00000000u)
00388 
00389 #define EDMA3_CCRL_QDMAQNUM_E5_MASK      (0x00700000u)
00390 #define EDMA3_CCRL_QDMAQNUM_E5_SHIFT     (0x00000014u)
00391 #define EDMA3_CCRL_QDMAQNUM_E5_RESETVAL  (0x00000000u)
00392 
00393 #define EDMA3_CCRL_QDMAQNUM_E4_MASK      (0x00070000u)
00394 #define EDMA3_CCRL_QDMAQNUM_E4_SHIFT     (0x00000010u)
00395 #define EDMA3_CCRL_QDMAQNUM_E4_RESETVAL  (0x00000000u)
00396 
00397 #define EDMA3_CCRL_QDMAQNUM_E3_MASK      (0x00007000u)
00398 #define EDMA3_CCRL_QDMAQNUM_E3_SHIFT     (0x0000000Cu)
00399 #define EDMA3_CCRL_QDMAQNUM_E3_RESETVAL  (0x00000000u)
00400 
00401 #define EDMA3_CCRL_QDMAQNUM_E2_MASK      (0x00000700u)
00402 #define EDMA3_CCRL_QDMAQNUM_E2_SHIFT     (0x00000008u)
00403 #define EDMA3_CCRL_QDMAQNUM_E2_RESETVAL  (0x00000000u)
00404 
00405 #define EDMA3_CCRL_QDMAQNUM_E1_MASK      (0x00000070u)
00406 #define EDMA3_CCRL_QDMAQNUM_E1_SHIFT     (0x00000004u)
00407 #define EDMA3_CCRL_QDMAQNUM_E1_RESETVAL  (0x00000000u)
00408 
00409 #define EDMA3_CCRL_QDMAQNUM_E0_MASK      (0x00000007u)
00410 #define EDMA3_CCRL_QDMAQNUM_E0_SHIFT     (0x00000000u)
00411 #define EDMA3_CCRL_QDMAQNUM_E0_RESETVAL  (0x00000000u)
00412 
00413 #define EDMA3_CCRL_QDMAQNUM_RESETVAL     (0x00000000u)
00414 
00415 /* QUETCMAP */
00416 
00417 #define EDMA3_CCRL_QUETCMAP_TCNUMQ7_MASK (0x70000000u)
00418 #define EDMA3_CCRL_QUETCMAP_TCNUMQ7_SHIFT (0x0000001Cu)
00419 #define EDMA3_CCRL_QUETCMAP_TCNUMQ7_RESETVAL (0x00000000u)
00420 
00421 #define EDMA3_CCRL_QUETCMAP_TCNUMQ6_MASK (0x07000000u)
00422 #define EDMA3_CCRL_QUETCMAP_TCNUMQ6_SHIFT (0x00000018u)
00423 #define EDMA3_CCRL_QUETCMAP_TCNUMQ6_RESETVAL (0x00000000u)
00424 
00425 #define EDMA3_CCRL_QUETCMAP_TCNUMQ5_MASK (0x00700000u)
00426 #define EDMA3_CCRL_QUETCMAP_TCNUMQ5_SHIFT (0x00000014u)
00427 #define EDMA3_CCRL_QUETCMAP_TCNUMQ5_RESETVAL (0x00000000u)
00428 
00429 #define EDMA3_CCRL_QUETCMAP_TCNUMQ4_MASK (0x00070000u)
00430 #define EDMA3_CCRL_QUETCMAP_TCNUMQ4_SHIFT (0x00000010u)
00431 #define EDMA3_CCRL_QUETCMAP_TCNUMQ4_RESETVAL (0x00000000u)
00432 
00433 #define EDMA3_CCRL_QUETCMAP_TCNUMQ3_MASK (0x00007000u)
00434 #define EDMA3_CCRL_QUETCMAP_TCNUMQ3_SHIFT (0x0000000Cu)
00435 #define EDMA3_CCRL_QUETCMAP_TCNUMQ3_RESETVAL (0x00000000u)
00436 
00437 #define EDMA3_CCRL_QUETCMAP_TCNUMQ2_MASK (0x00000700u)
00438 #define EDMA3_CCRL_QUETCMAP_TCNUMQ2_SHIFT (0x00000008u)
00439 #define EDMA3_CCRL_QUETCMAP_TCNUMQ2_RESETVAL (0x00000000u)
00440 
00441 #define EDMA3_CCRL_QUETCMAP_TCNUMQ1_MASK (0x00000070u)
00442 #define EDMA3_CCRL_QUETCMAP_TCNUMQ1_SHIFT (0x00000004u)
00443 #define EDMA3_CCRL_QUETCMAP_TCNUMQ1_RESETVAL (0x00000000u)
00444 
00445 #define EDMA3_CCRL_QUETCMAP_TCNUMQ0_MASK (0x00000007u)
00446 #define EDMA3_CCRL_QUETCMAP_TCNUMQ0_SHIFT (0x00000000u)
00447 #define EDMA3_CCRL_QUETCMAP_TCNUMQ0_RESETVAL (0x00000000u)
00448 
00449 #define EDMA3_CCRL_QUETCMAP_RESETVAL     (0x00000000u)
00450 
00451 /* QUEPRI */
00452 
00453 #define EDMA3_CCRL_QUEPRI_PRIQ7_MASK     (0x70000000u)
00454 #define EDMA3_CCRL_QUEPRI_PRIQ7_SHIFT    (0x0000001Cu)
00455 #define EDMA3_CCRL_QUEPRI_PRIQ7_RESETVAL (0x00000000u)
00456 
00457 #define EDMA3_CCRL_QUEPRI_PRIQ6_MASK     (0x07000000u)
00458 #define EDMA3_CCRL_QUEPRI_PRIQ6_SHIFT    (0x00000018u)
00459 #define EDMA3_CCRL_QUEPRI_PRIQ6_RESETVAL (0x00000000u)
00460 
00461 #define EDMA3_CCRL_QUEPRI_PRIQ5_MASK     (0x00700000u)
00462 #define EDMA3_CCRL_QUEPRI_PRIQ5_SHIFT    (0x00000014u)
00463 #define EDMA3_CCRL_QUEPRI_PRIQ5_RESETVAL (0x00000000u)
00464 
00465 #define EDMA3_CCRL_QUEPRI_PRIQ4_MASK     (0x00070000u)
00466 #define EDMA3_CCRL_QUEPRI_PRIQ4_SHIFT    (0x00000010u)
00467 #define EDMA3_CCRL_QUEPRI_PRIQ4_RESETVAL (0x00000000u)
00468 
00469 #define EDMA3_CCRL_QUEPRI_PRIQ3_MASK     (0x00007000u)
00470 #define EDMA3_CCRL_QUEPRI_PRIQ3_SHIFT    (0x0000000Cu)
00471 #define EDMA3_CCRL_QUEPRI_PRIQ3_RESETVAL (0x00000000u)
00472 
00473 #define EDMA3_CCRL_QUEPRI_PRIQ2_MASK     (0x00000700u)
00474 #define EDMA3_CCRL_QUEPRI_PRIQ2_SHIFT    (0x00000008u)
00475 #define EDMA3_CCRL_QUEPRI_PRIQ2_RESETVAL (0x00000000u)
00476 
00477 #define EDMA3_CCRL_QUEPRI_PRIQ1_MASK     (0x00000070u)
00478 #define EDMA3_CCRL_QUEPRI_PRIQ1_SHIFT    (0x00000004u)
00479 #define EDMA3_CCRL_QUEPRI_PRIQ1_RESETVAL (0x00000000u)
00480 
00481 #define EDMA3_CCRL_QUEPRI_PRIQ0_MASK     (0x00000007u)
00482 #define EDMA3_CCRL_QUEPRI_PRIQ0_SHIFT    (0x00000000u)
00483 #define EDMA3_CCRL_QUEPRI_PRIQ0_RESETVAL (0x00000000u)
00484 
00485 #define EDMA3_CCRL_QUEPRI_RESETVAL       (0x00000000u)
00486 
00487 /* EMR */
00488 
00489 #define EDMA3_CCRL_EMR_E31_MASK          (0x80000000u)
00490 #define EDMA3_CCRL_EMR_E31_SHIFT         (0x0000001Fu)
00491 #define EDMA3_CCRL_EMR_E31_RESETVAL      (0x00000000u)
00492 
00493 #define EDMA3_CCRL_EMR_E30_MASK          (0x40000000u)
00494 #define EDMA3_CCRL_EMR_E30_SHIFT         (0x0000001Eu)
00495 #define EDMA3_CCRL_EMR_E30_RESETVAL      (0x00000000u)
00496 
00497 #define EDMA3_CCRL_EMR_E29_MASK          (0x20000000u)
00498 #define EDMA3_CCRL_EMR_E29_SHIFT         (0x0000001Du)
00499 #define EDMA3_CCRL_EMR_E29_RESETVAL      (0x00000000u)
00500 
00501 #define EDMA3_CCRL_EMR_E28_MASK          (0x10000000u)
00502 #define EDMA3_CCRL_EMR_E28_SHIFT         (0x0000001Cu)
00503 #define EDMA3_CCRL_EMR_E28_RESETVAL      (0x00000000u)
00504 
00505 #define EDMA3_CCRL_EMR_E27_MASK          (0x08000000u)
00506 #define EDMA3_CCRL_EMR_E27_SHIFT         (0x0000001Bu)
00507 #define EDMA3_CCRL_EMR_E27_RESETVAL      (0x00000000u)
00508 
00509 #define EDMA3_CCRL_EMR_E26_MASK          (0x04000000u)
00510 #define EDMA3_CCRL_EMR_E26_SHIFT         (0x0000001Au)
00511 #define EDMA3_CCRL_EMR_E26_RESETVAL      (0x00000000u)
00512 
00513 #define EDMA3_CCRL_EMR_E25_MASK          (0x02000000u)
00514 #define EDMA3_CCRL_EMR_E25_SHIFT         (0x00000019u)
00515 #define EDMA3_CCRL_EMR_E25_RESETVAL      (0x00000000u)
00516 
00517 #define EDMA3_CCRL_EMR_E24_MASK          (0x01000000u)
00518 #define EDMA3_CCRL_EMR_E24_SHIFT         (0x00000018u)
00519 #define EDMA3_CCRL_EMR_E24_RESETVAL      (0x00000000u)
00520 
00521 #define EDMA3_CCRL_EMR_E23_MASK          (0x00800000u)
00522 #define EDMA3_CCRL_EMR_E23_SHIFT         (0x00000017u)
00523 #define EDMA3_CCRL_EMR_E23_RESETVAL      (0x00000000u)
00524 
00525 #define EDMA3_CCRL_EMR_E22_MASK          (0x00400000u)
00526 #define EDMA3_CCRL_EMR_E22_SHIFT         (0x00000016u)
00527 #define EDMA3_CCRL_EMR_E22_RESETVAL      (0x00000000u)
00528 
00529 #define EDMA3_CCRL_EMR_E21_MASK          (0x00200000u)
00530 #define EDMA3_CCRL_EMR_E21_SHIFT         (0x00000015u)
00531 #define EDMA3_CCRL_EMR_E21_RESETVAL      (0x00000000u)
00532 
00533 #define EDMA3_CCRL_EMR_E20_MASK          (0x00100000u)
00534 #define EDMA3_CCRL_EMR_E20_SHIFT         (0x00000014u)
00535 #define EDMA3_CCRL_EMR_E20_RESETVAL      (0x00000000u)
00536 
00537 #define EDMA3_CCRL_EMR_E19_MASK          (0x00080000u)
00538 #define EDMA3_CCRL_EMR_E19_SHIFT         (0x00000013u)
00539 #define EDMA3_CCRL_EMR_E19_RESETVAL      (0x00000000u)
00540 
00541 #define EDMA3_CCRL_EMR_E18_MASK          (0x00040000u)
00542 #define EDMA3_CCRL_EMR_E18_SHIFT         (0x00000012u)
00543 #define EDMA3_CCRL_EMR_E18_RESETVAL      (0x00000000u)
00544 
00545 #define EDMA3_CCRL_EMR_E17_MASK          (0x00020000u)
00546 #define EDMA3_CCRL_EMR_E17_SHIFT         (0x00000011u)
00547 #define EDMA3_CCRL_EMR_E17_RESETVAL      (0x00000000u)
00548 
00549 #define EDMA3_CCRL_EMR_E16_MASK          (0x00010000u)
00550 #define EDMA3_CCRL_EMR_E16_SHIFT         (0x00000010u)
00551 #define EDMA3_CCRL_EMR_E16_RESETVAL      (0x00000000u)
00552 
00553 #define EDMA3_CCRL_EMR_E15_MASK          (0x00008000u)
00554 #define EDMA3_CCRL_EMR_E15_SHIFT         (0x0000000Fu)
00555 #define EDMA3_CCRL_EMR_E15_RESETVAL      (0x00000000u)
00556 
00557 #define EDMA3_CCRL_EMR_E14_MASK          (0x00004000u)
00558 #define EDMA3_CCRL_EMR_E14_SHIFT         (0x0000000Eu)
00559 #define EDMA3_CCRL_EMR_E14_RESETVAL      (0x00000000u)
00560 
00561 #define EDMA3_CCRL_EMR_E13_MASK          (0x00002000u)
00562 #define EDMA3_CCRL_EMR_E13_SHIFT         (0x0000000Du)
00563 #define EDMA3_CCRL_EMR_E13_RESETVAL      (0x00000000u)
00564 
00565 #define EDMA3_CCRL_EMR_E12_MASK          (0x00001000u)
00566 #define EDMA3_CCRL_EMR_E12_SHIFT         (0x0000000Cu)
00567 #define EDMA3_CCRL_EMR_E12_RESETVAL      (0x00000000u)
00568 
00569 #define EDMA3_CCRL_EMR_E11_MASK          (0x00000800u)
00570 #define EDMA3_CCRL_EMR_E11_SHIFT         (0x0000000Bu)
00571 #define EDMA3_CCRL_EMR_E11_RESETVAL      (0x00000000u)
00572 
00573 #define EDMA3_CCRL_EMR_E10_MASK          (0x00000400u)
00574 #define EDMA3_CCRL_EMR_E10_SHIFT         (0x0000000Au)
00575 #define EDMA3_CCRL_EMR_E10_RESETVAL      (0x00000000u)
00576 
00577 #define EDMA3_CCRL_EMR_E9_MASK           (0x00000200u)
00578 #define EDMA3_CCRL_EMR_E9_SHIFT          (0x00000009u)
00579 #define EDMA3_CCRL_EMR_E9_RESETVAL       (0x00000000u)
00580 
00581 #define EDMA3_CCRL_EMR_E8_MASK           (0x00000100u)
00582 #define EDMA3_CCRL_EMR_E8_SHIFT          (0x00000008u)
00583 #define EDMA3_CCRL_EMR_E8_RESETVAL       (0x00000000u)
00584 
00585 #define EDMA3_CCRL_EMR_E7_MASK           (0x00000080u)
00586 #define EDMA3_CCRL_EMR_E7_SHIFT          (0x00000007u)
00587 #define EDMA3_CCRL_EMR_E7_RESETVAL       (0x00000000u)
00588 
00589 #define EDMA3_CCRL_EMR_E6_MASK           (0x00000040u)
00590 #define EDMA3_CCRL_EMR_E6_SHIFT          (0x00000006u)
00591 #define EDMA3_CCRL_EMR_E6_RESETVAL       (0x00000000u)
00592 
00593 #define EDMA3_CCRL_EMR_E5_MASK           (0x00000020u)
00594 #define EDMA3_CCRL_EMR_E5_SHIFT          (0x00000005u)
00595 #define EDMA3_CCRL_EMR_E5_RESETVAL       (0x00000000u)
00596 
00597 #define EDMA3_CCRL_EMR_E4_MASK           (0x00000010u)
00598 #define EDMA3_CCRL_EMR_E4_SHIFT          (0x00000004u)
00599 #define EDMA3_CCRL_EMR_E4_RESETVAL       (0x00000000u)
00600 
00601 #define EDMA3_CCRL_EMR_E3_MASK           (0x00000008u)
00602 #define EDMA3_CCRL_EMR_E3_SHIFT          (0x00000003u)
00603 #define EDMA3_CCRL_EMR_E3_RESETVAL       (0x00000000u)
00604 
00605 #define EDMA3_CCRL_EMR_E2_MASK           (0x00000004u)
00606 #define EDMA3_CCRL_EMR_E2_SHIFT          (0x00000002u)
00607 #define EDMA3_CCRL_EMR_E2_RESETVAL       (0x00000000u)
00608 
00609 #define EDMA3_CCRL_EMR_E1_MASK           (0x00000002u)
00610 #define EDMA3_CCRL_EMR_E1_SHIFT          (0x00000001u)
00611 #define EDMA3_CCRL_EMR_E1_RESETVAL       (0x00000000u)
00612 
00613 #define EDMA3_CCRL_EMR_E0_MASK           (0x00000001u)
00614 #define EDMA3_CCRL_EMR_E0_SHIFT          (0x00000000u)
00615 #define EDMA3_CCRL_EMR_E0_RESETVAL       (0x00000000u)
00616 
00617 #define EDMA3_CCRL_EMR_RESETVAL          (0x00000000u)
00618 
00619 /* EMRH */
00620 
00621 #define EDMA3_CCRL_EMRH_E63_MASK         (0x80000000u)
00622 #define EDMA3_CCRL_EMRH_E63_SHIFT        (0x0000001Fu)
00623 #define EDMA3_CCRL_EMRH_E63_RESETVAL     (0x00000000u)
00624 
00625 #define EDMA3_CCRL_EMRH_E62_MASK         (0x40000000u)
00626 #define EDMA3_CCRL_EMRH_E62_SHIFT        (0x0000001Eu)
00627 #define EDMA3_CCRL_EMRH_E62_RESETVAL     (0x00000000u)
00628 
00629 #define EDMA3_CCRL_EMRH_E61_MASK         (0x20000000u)
00630 #define EDMA3_CCRL_EMRH_E61_SHIFT        (0x0000001Du)
00631 #define EDMA3_CCRL_EMRH_E61_RESETVAL     (0x00000000u)
00632 
00633 #define EDMA3_CCRL_EMRH_E60_MASK         (0x10000000u)
00634 #define EDMA3_CCRL_EMRH_E60_SHIFT        (0x0000001Cu)
00635 #define EDMA3_CCRL_EMRH_E60_RESETVAL     (0x00000000u)
00636 
00637 #define EDMA3_CCRL_EMRH_E59_MASK         (0x08000000u)
00638 #define EDMA3_CCRL_EMRH_E59_SHIFT        (0x0000001Bu)
00639 #define EDMA3_CCRL_EMRH_E59_RESETVAL     (0x00000000u)
00640 
00641 #define EDMA3_CCRL_EMRH_E58_MASK         (0x04000000u)
00642 #define EDMA3_CCRL_EMRH_E58_SHIFT        (0x0000001Au)
00643 #define EDMA3_CCRL_EMRH_E58_RESETVAL     (0x00000000u)
00644 
00645 #define EDMA3_CCRL_EMRH_E57_MASK         (0x02000000u)
00646 #define EDMA3_CCRL_EMRH_E57_SHIFT        (0x00000019u)
00647 #define EDMA3_CCRL_EMRH_E57_RESETVAL     (0x00000000u)
00648 
00649 #define EDMA3_CCRL_EMRH_E56_MASK         (0x01000000u)
00650 #define EDMA3_CCRL_EMRH_E56_SHIFT        (0x00000018u)
00651 #define EDMA3_CCRL_EMRH_E56_RESETVAL     (0x00000000u)
00652 
00653 #define EDMA3_CCRL_EMRH_E55_MASK         (0x00800000u)
00654 #define EDMA3_CCRL_EMRH_E55_SHIFT        (0x00000017u)
00655 #define EDMA3_CCRL_EMRH_E55_RESETVAL     (0x00000000u)
00656 
00657 #define EDMA3_CCRL_EMRH_E54_MASK         (0x00400000u)
00658 #define EDMA3_CCRL_EMRH_E54_SHIFT        (0x00000016u)
00659 #define EDMA3_CCRL_EMRH_E54_RESETVAL     (0x00000000u)
00660 
00661 #define EDMA3_CCRL_EMRH_E53_MASK         (0x00200000u)
00662 #define EDMA3_CCRL_EMRH_E53_SHIFT        (0x00000015u)
00663 #define EDMA3_CCRL_EMRH_E53_RESETVAL     (0x00000000u)
00664 
00665 #define EDMA3_CCRL_EMRH_E52_MASK         (0x00100000u)
00666 #define EDMA3_CCRL_EMRH_E52_SHIFT        (0x00000014u)
00667 #define EDMA3_CCRL_EMRH_E52_RESETVAL     (0x00000000u)
00668 
00669 #define EDMA3_CCRL_EMRH_E51_MASK         (0x00080000u)
00670 #define EDMA3_CCRL_EMRH_E51_SHIFT        (0x00000013u)
00671 #define EDMA3_CCRL_EMRH_E51_RESETVAL     (0x00000000u)
00672 
00673 #define EDMA3_CCRL_EMRH_E50_MASK         (0x00040000u)
00674 #define EDMA3_CCRL_EMRH_E50_SHIFT        (0x00000012u)
00675 #define EDMA3_CCRL_EMRH_E50_RESETVAL     (0x00000000u)
00676 
00677 #define EDMA3_CCRL_EMRH_E49_MASK         (0x00020000u)
00678 #define EDMA3_CCRL_EMRH_E49_SHIFT        (0x00000011u)
00679 #define EDMA3_CCRL_EMRH_E49_RESETVAL     (0x00000000u)
00680 
00681 #define EDMA3_CCRL_EMRH_E48_MASK         (0x00010000u)
00682 #define EDMA3_CCRL_EMRH_E48_SHIFT        (0x00000010u)
00683 #define EDMA3_CCRL_EMRH_E48_RESETVAL     (0x00000000u)
00684 
00685 #define EDMA3_CCRL_EMRH_E47_MASK         (0x00008000u)
00686 #define EDMA3_CCRL_EMRH_E47_SHIFT        (0x0000000Fu)
00687 #define EDMA3_CCRL_EMRH_E47_RESETVAL     (0x00000000u)
00688 
00689 #define EDMA3_CCRL_EMRH_E46_MASK         (0x00004000u)
00690 #define EDMA3_CCRL_EMRH_E46_SHIFT        (0x0000000Eu)
00691 #define EDMA3_CCRL_EMRH_E46_RESETVAL     (0x00000000u)
00692 
00693 #define EDMA3_CCRL_EMRH_E45_MASK         (0x00002000u)
00694 #define EDMA3_CCRL_EMRH_E45_SHIFT        (0x0000000Du)
00695 #define EDMA3_CCRL_EMRH_E45_RESETVAL     (0x00000000u)
00696 
00697 #define EDMA3_CCRL_EMRH_E44_MASK         (0x00001000u)
00698 #define EDMA3_CCRL_EMRH_E44_SHIFT        (0x0000000Cu)
00699 #define EDMA3_CCRL_EMRH_E44_RESETVAL     (0x00000000u)
00700 
00701 #define EDMA3_CCRL_EMRH_E43_MASK         (0x00000800u)
00702 #define EDMA3_CCRL_EMRH_E43_SHIFT        (0x0000000Bu)
00703 #define EDMA3_CCRL_EMRH_E43_RESETVAL     (0x00000000u)
00704 
00705 #define EDMA3_CCRL_EMRH_E42_MASK         (0x00000400u)
00706 #define EDMA3_CCRL_EMRH_E42_SHIFT        (0x0000000Au)
00707 #define EDMA3_CCRL_EMRH_E42_RESETVAL     (0x00000000u)
00708 
00709 #define EDMA3_CCRL_EMRH_E41_MASK         (0x00000200u)
00710 #define EDMA3_CCRL_EMRH_E41_SHIFT        (0x00000009u)
00711 #define EDMA3_CCRL_EMRH_E41_RESETVAL     (0x00000000u)
00712 
00713 #define EDMA3_CCRL_EMRH_E40_MASK         (0x00000100u)
00714 #define EDMA3_CCRL_EMRH_E40_SHIFT        (0x00000008u)
00715 #define EDMA3_CCRL_EMRH_E40_RESETVAL     (0x00000000u)
00716 
00717 #define EDMA3_CCRL_EMRH_E39_MASK         (0x00000080u)
00718 #define EDMA3_CCRL_EMRH_E39_SHIFT        (0x00000007u)
00719 #define EDMA3_CCRL_EMRH_E39_RESETVAL     (0x00000000u)
00720 
00721 #define EDMA3_CCRL_EMRH_E38_MASK         (0x00000040u)
00722 #define EDMA3_CCRL_EMRH_E38_SHIFT        (0x00000006u)
00723 #define EDMA3_CCRL_EMRH_E38_RESETVAL     (0x00000000u)
00724 
00725 #define EDMA3_CCRL_EMRH_E37_MASK         (0x00000020u)
00726 #define EDMA3_CCRL_EMRH_E37_SHIFT        (0x00000005u)
00727 #define EDMA3_CCRL_EMRH_E37_RESETVAL     (0x00000000u)
00728 
00729 #define EDMA3_CCRL_EMRH_E36_MASK         (0x00000010u)
00730 #define EDMA3_CCRL_EMRH_E36_SHIFT        (0x00000004u)
00731 #define EDMA3_CCRL_EMRH_E36_RESETVAL     (0x00000000u)
00732 
00733 #define EDMA3_CCRL_EMRH_E35_MASK         (0x00000008u)
00734 #define EDMA3_CCRL_EMRH_E35_SHIFT        (0x00000003u)
00735 #define EDMA3_CCRL_EMRH_E35_RESETVAL     (0x00000000u)
00736 
00737 #define EDMA3_CCRL_EMRH_E34_MASK         (0x00000004u)
00738 #define EDMA3_CCRL_EMRH_E34_SHIFT        (0x00000002u)
00739 #define EDMA3_CCRL_EMRH_E34_RESETVAL     (0x00000000u)
00740 
00741 #define EDMA3_CCRL_EMRH_E33_MASK         (0x00000002u)
00742 #define EDMA3_CCRL_EMRH_E33_SHIFT        (0x00000001u)
00743 #define EDMA3_CCRL_EMRH_E33_RESETVAL     (0x00000000u)
00744 
00745 #define EDMA3_CCRL_EMRH_E32_MASK         (0x00000001u)
00746 #define EDMA3_CCRL_EMRH_E32_SHIFT        (0x00000000u)
00747 #define EDMA3_CCRL_EMRH_E32_RESETVAL     (0x00000000u)
00748 
00749 #define EDMA3_CCRL_EMRH_RESETVAL         (0x00000000u)
00750 
00751 /* EMCR */
00752 
00753 #define EDMA3_CCRL_EMCR_E31_MASK         (0x80000000u)
00754 #define EDMA3_CCRL_EMCR_E31_SHIFT        (0x0000001Fu)
00755 #define EDMA3_CCRL_EMCR_E31_RESETVAL     (0x00000000u)
00756 
00757 #define EDMA3_CCRL_EMCR_E30_MASK         (0x40000000u)
00758 #define EDMA3_CCRL_EMCR_E30_SHIFT        (0x0000001Eu)
00759 #define EDMA3_CCRL_EMCR_E30_RESETVAL     (0x00000000u)
00760 
00761 #define EDMA3_CCRL_EMCR_E29_MASK         (0x20000000u)
00762 #define EDMA3_CCRL_EMCR_E29_SHIFT        (0x0000001Du)
00763 #define EDMA3_CCRL_EMCR_E29_RESETVAL     (0x00000000u)
00764 
00765 #define EDMA3_CCRL_EMCR_E28_MASK         (0x10000000u)
00766 #define EDMA3_CCRL_EMCR_E28_SHIFT        (0x0000001Cu)
00767 #define EDMA3_CCRL_EMCR_E28_RESETVAL     (0x00000000u)
00768 
00769 #define EDMA3_CCRL_EMCR_E27_MASK         (0x08000000u)
00770 #define EDMA3_CCRL_EMCR_E27_SHIFT        (0x0000001Bu)
00771 #define EDMA3_CCRL_EMCR_E27_RESETVAL     (0x00000000u)
00772 
00773 #define EDMA3_CCRL_EMCR_E26_MASK         (0x04000000u)
00774 #define EDMA3_CCRL_EMCR_E26_SHIFT        (0x0000001Au)
00775 #define EDMA3_CCRL_EMCR_E26_RESETVAL     (0x00000000u)
00776 
00777 #define EDMA3_CCRL_EMCR_E25_MASK         (0x02000000u)
00778 #define EDMA3_CCRL_EMCR_E25_SHIFT        (0x00000019u)
00779 #define EDMA3_CCRL_EMCR_E25_RESETVAL     (0x00000000u)
00780 
00781 #define EDMA3_CCRL_EMCR_E24_MASK         (0x01000000u)
00782 #define EDMA3_CCRL_EMCR_E24_SHIFT        (0x00000018u)
00783 #define EDMA3_CCRL_EMCR_E24_RESETVAL     (0x00000000u)
00784 
00785 #define EDMA3_CCRL_EMCR_E23_MASK         (0x00800000u)
00786 #define EDMA3_CCRL_EMCR_E23_SHIFT        (0x00000017u)
00787 #define EDMA3_CCRL_EMCR_E23_RESETVAL     (0x00000000u)
00788 
00789 #define EDMA3_CCRL_EMCR_E22_MASK         (0x00400000u)
00790 #define EDMA3_CCRL_EMCR_E22_SHIFT        (0x00000016u)
00791 #define EDMA3_CCRL_EMCR_E22_RESETVAL     (0x00000000u)
00792 
00793 #define EDMA3_CCRL_EMCR_E21_MASK         (0x00200000u)
00794 #define EDMA3_CCRL_EMCR_E21_SHIFT        (0x00000015u)
00795 #define EDMA3_CCRL_EMCR_E21_RESETVAL     (0x00000000u)
00796 
00797 #define EDMA3_CCRL_EMCR_E20_MASK         (0x00100000u)
00798 #define EDMA3_CCRL_EMCR_E20_SHIFT        (0x00000014u)
00799 #define EDMA3_CCRL_EMCR_E20_RESETVAL     (0x00000000u)
00800 
00801 #define EDMA3_CCRL_EMCR_E19_MASK         (0x00080000u)
00802 #define EDMA3_CCRL_EMCR_E19_SHIFT        (0x00000013u)
00803 #define EDMA3_CCRL_EMCR_E19_RESETVAL     (0x00000000u)
00804 
00805 #define EDMA3_CCRL_EMCR_E18_MASK         (0x00040000u)
00806 #define EDMA3_CCRL_EMCR_E18_SHIFT        (0x00000012u)
00807 #define EDMA3_CCRL_EMCR_E18_RESETVAL     (0x00000000u)
00808 
00809 #define EDMA3_CCRL_EMCR_E17_MASK         (0x00020000u)
00810 #define EDMA3_CCRL_EMCR_E17_SHIFT        (0x00000011u)
00811 #define EDMA3_CCRL_EMCR_E17_RESETVAL     (0x00000000u)
00812 
00813 #define EDMA3_CCRL_EMCR_E16_MASK         (0x00010000u)
00814 #define EDMA3_CCRL_EMCR_E16_SHIFT        (0x00000010u)
00815 #define EDMA3_CCRL_EMCR_E16_RESETVAL     (0x00000000u)
00816 
00817 #define EDMA3_CCRL_EMCR_E15_MASK         (0x00008000u)
00818 #define EDMA3_CCRL_EMCR_E15_SHIFT        (0x0000000Fu)
00819 #define EDMA3_CCRL_EMCR_E15_RESETVAL     (0x00000000u)
00820 
00821 #define EDMA3_CCRL_EMCR_E14_MASK         (0x00004000u)
00822 #define EDMA3_CCRL_EMCR_E14_SHIFT        (0x0000000Eu)
00823 #define EDMA3_CCRL_EMCR_E14_RESETVAL     (0x00000000u)
00824 
00825 #define EDMA3_CCRL_EMCR_E13_MASK         (0x00002000u)
00826 #define EDMA3_CCRL_EMCR_E13_SHIFT        (0x0000000Du)
00827 #define EDMA3_CCRL_EMCR_E13_RESETVAL     (0x00000000u)
00828 
00829 #define EDMA3_CCRL_EMCR_E12_MASK         (0x00001000u)
00830 #define EDMA3_CCRL_EMCR_E12_SHIFT        (0x0000000Cu)
00831 #define EDMA3_CCRL_EMCR_E12_RESETVAL     (0x00000000u)
00832 
00833 #define EDMA3_CCRL_EMCR_E11_MASK         (0x00000800u)
00834 #define EDMA3_CCRL_EMCR_E11_SHIFT        (0x0000000Bu)
00835 #define EDMA3_CCRL_EMCR_E11_RESETVAL     (0x00000000u)
00836 
00837 #define EDMA3_CCRL_EMCR_E10_MASK         (0x00000400u)
00838 #define EDMA3_CCRL_EMCR_E10_SHIFT        (0x0000000Au)
00839 #define EDMA3_CCRL_EMCR_E10_RESETVAL     (0x00000000u)
00840 
00841 #define EDMA3_CCRL_EMCR_E9_MASK          (0x00000200u)
00842 #define EDMA3_CCRL_EMCR_E9_SHIFT         (0x00000009u)
00843 #define EDMA3_CCRL_EMCR_E9_RESETVAL      (0x00000000u)
00844 
00845 #define EDMA3_CCRL_EMCR_E8_MASK          (0x00000100u)
00846 #define EDMA3_CCRL_EMCR_E8_SHIFT         (0x00000008u)
00847 #define EDMA3_CCRL_EMCR_E8_RESETVAL      (0x00000000u)
00848 
00849 #define EDMA3_CCRL_EMCR_E7_MASK          (0x00000080u)
00850 #define EDMA3_CCRL_EMCR_E7_SHIFT         (0x00000007u)
00851 #define EDMA3_CCRL_EMCR_E7_RESETVAL      (0x00000000u)
00852 
00853 #define EDMA3_CCRL_EMCR_E6_MASK          (0x00000040u)
00854 #define EDMA3_CCRL_EMCR_E6_SHIFT         (0x00000006u)
00855 #define EDMA3_CCRL_EMCR_E6_RESETVAL      (0x00000000u)
00856 
00857 #define EDMA3_CCRL_EMCR_E5_MASK          (0x00000020u)
00858 #define EDMA3_CCRL_EMCR_E5_SHIFT         (0x00000005u)
00859 #define EDMA3_CCRL_EMCR_E5_RESETVAL      (0x00000000u)
00860 
00861 #define EDMA3_CCRL_EMCR_E4_MASK          (0x00000010u)
00862 #define EDMA3_CCRL_EMCR_E4_SHIFT         (0x00000004u)
00863 #define EDMA3_CCRL_EMCR_E4_RESETVAL      (0x00000000u)
00864 
00865 #define EDMA3_CCRL_EMCR_E3_MASK          (0x00000008u)
00866 #define EDMA3_CCRL_EMCR_E3_SHIFT         (0x00000003u)
00867 #define EDMA3_CCRL_EMCR_E3_RESETVAL      (0x00000000u)
00868 
00869 #define EDMA3_CCRL_EMCR_E2_MASK          (0x00000004u)
00870 #define EDMA3_CCRL_EMCR_E2_SHIFT         (0x00000002u)
00871 #define EDMA3_CCRL_EMCR_E2_RESETVAL      (0x00000000u)
00872 
00873 #define EDMA3_CCRL_EMCR_E1_MASK          (0x00000002u)
00874 #define EDMA3_CCRL_EMCR_E1_SHIFT         (0x00000001u)
00875 #define EDMA3_CCRL_EMCR_E1_RESETVAL      (0x00000000u)
00876 
00877 #define EDMA3_CCRL_EMCR_E0_MASK          (0x00000001u)
00878 #define EDMA3_CCRL_EMCR_E0_SHIFT         (0x00000000u)
00879 #define EDMA3_CCRL_EMCR_E0_RESETVAL      (0x00000000u)
00880 
00881 #define EDMA3_CCRL_EMCR_RESETVAL         (0x00000000u)
00882 
00883 /* EMCRH */
00884 
00885 #define EDMA3_CCRL_EMCRH_E63_MASK        (0x80000000u)
00886 #define EDMA3_CCRL_EMCRH_E63_SHIFT       (0x0000001Fu)
00887 #define EDMA3_CCRL_EMCRH_E63_RESETVAL    (0x00000000u)
00888 
00889 #define EDMA3_CCRL_EMCRH_E62_MASK        (0x40000000u)
00890 #define EDMA3_CCRL_EMCRH_E62_SHIFT       (0x0000001Eu)
00891 #define EDMA3_CCRL_EMCRH_E62_RESETVAL    (0x00000000u)
00892 
00893 #define EDMA3_CCRL_EMCRH_E61_MASK        (0x20000000u)
00894 #define EDMA3_CCRL_EMCRH_E61_SHIFT       (0x0000001Du)
00895 #define EDMA3_CCRL_EMCRH_E61_RESETVAL    (0x00000000u)
00896 
00897 #define EDMA3_CCRL_EMCRH_E60_MASK        (0x10000000u)
00898 #define EDMA3_CCRL_EMCRH_E60_SHIFT       (0x0000001Cu)
00899 #define EDMA3_CCRL_EMCRH_E60_RESETVAL    (0x00000000u)
00900 
00901 #define EDMA3_CCRL_EMCRH_E59_MASK        (0x08000000u)
00902 #define EDMA3_CCRL_EMCRH_E59_SHIFT       (0x0000001Bu)
00903 #define EDMA3_CCRL_EMCRH_E59_RESETVAL    (0x00000000u)
00904 
00905 #define EDMA3_CCRL_EMCRH_E58_MASK        (0x04000000u)
00906 #define EDMA3_CCRL_EMCRH_E58_SHIFT       (0x0000001Au)
00907 #define EDMA3_CCRL_EMCRH_E58_RESETVAL    (0x00000000u)
00908 
00909 #define EDMA3_CCRL_EMCRH_E57_MASK        (0x02000000u)
00910 #define EDMA3_CCRL_EMCRH_E57_SHIFT       (0x00000019u)
00911 #define EDMA3_CCRL_EMCRH_E57_RESETVAL    (0x00000000u)
00912 
00913 #define EDMA3_CCRL_EMCRH_E56_MASK        (0x01000000u)
00914 #define EDMA3_CCRL_EMCRH_E56_SHIFT       (0x00000018u)
00915 #define EDMA3_CCRL_EMCRH_E56_RESETVAL    (0x00000000u)
00916 
00917 #define EDMA3_CCRL_EMCRH_E55_MASK        (0x00800000u)
00918 #define EDMA3_CCRL_EMCRH_E55_SHIFT       (0x00000017u)
00919 #define EDMA3_CCRL_EMCRH_E55_RESETVAL    (0x00000000u)
00920 
00921 #define EDMA3_CCRL_EMCRH_E54_MASK        (0x00400000u)
00922 #define EDMA3_CCRL_EMCRH_E54_SHIFT       (0x00000016u)
00923 #define EDMA3_CCRL_EMCRH_E54_RESETVAL    (0x00000000u)
00924 
00925 #define EDMA3_CCRL_EMCRH_E53_MASK        (0x00200000u)
00926 #define EDMA3_CCRL_EMCRH_E53_SHIFT       (0x00000015u)
00927 #define EDMA3_CCRL_EMCRH_E53_RESETVAL    (0x00000000u)
00928 
00929 #define EDMA3_CCRL_EMCRH_E52_MASK        (0x00100000u)
00930 #define EDMA3_CCRL_EMCRH_E52_SHIFT       (0x00000014u)
00931 #define EDMA3_CCRL_EMCRH_E52_RESETVAL    (0x00000000u)
00932 
00933 #define EDMA3_CCRL_EMCRH_E51_MASK        (0x00080000u)
00934 #define EDMA3_CCRL_EMCRH_E51_SHIFT       (0x00000013u)
00935 #define EDMA3_CCRL_EMCRH_E51_RESETVAL    (0x00000000u)
00936 
00937 #define EDMA3_CCRL_EMCRH_E50_MASK        (0x00040000u)
00938 #define EDMA3_CCRL_EMCRH_E50_SHIFT       (0x00000012u)
00939 #define EDMA3_CCRL_EMCRH_E50_RESETVAL    (0x00000000u)
00940 
00941 #define EDMA3_CCRL_EMCRH_E49_MASK        (0x00020000u)
00942 #define EDMA3_CCRL_EMCRH_E49_SHIFT       (0x00000011u)
00943 #define EDMA3_CCRL_EMCRH_E49_RESETVAL    (0x00000000u)
00944 
00945 #define EDMA3_CCRL_EMCRH_E48_MASK        (0x00010000u)
00946 #define EDMA3_CCRL_EMCRH_E48_SHIFT       (0x00000010u)
00947 #define EDMA3_CCRL_EMCRH_E48_RESETVAL    (0x00000000u)
00948 
00949 #define EDMA3_CCRL_EMCRH_E47_MASK        (0x00008000u)
00950 #define EDMA3_CCRL_EMCRH_E47_SHIFT       (0x0000000Fu)
00951 #define EDMA3_CCRL_EMCRH_E47_RESETVAL    (0x00000000u)
00952 
00953 #define EDMA3_CCRL_EMCRH_E46_MASK        (0x00004000u)
00954 #define EDMA3_CCRL_EMCRH_E46_SHIFT       (0x0000000Eu)
00955 #define EDMA3_CCRL_EMCRH_E46_RESETVAL    (0x00000000u)
00956 
00957 #define EDMA3_CCRL_EMCRH_E45_MASK        (0x00002000u)
00958 #define EDMA3_CCRL_EMCRH_E45_SHIFT       (0x0000000Du)
00959 #define EDMA3_CCRL_EMCRH_E45_RESETVAL    (0x00000000u)
00960 
00961 #define EDMA3_CCRL_EMCRH_E44_MASK        (0x00001000u)
00962 #define EDMA3_CCRL_EMCRH_E44_SHIFT       (0x0000000Cu)
00963 #define EDMA3_CCRL_EMCRH_E44_RESETVAL    (0x00000000u)
00964 
00965 #define EDMA3_CCRL_EMCRH_E43_MASK        (0x00000800u)
00966 #define EDMA3_CCRL_EMCRH_E43_SHIFT       (0x0000000Bu)
00967 #define EDMA3_CCRL_EMCRH_E43_RESETVAL    (0x00000000u)
00968 
00969 #define EDMA3_CCRL_EMCRH_E42_MASK        (0x00000400u)
00970 #define EDMA3_CCRL_EMCRH_E42_SHIFT       (0x0000000Au)
00971 #define EDMA3_CCRL_EMCRH_E42_RESETVAL    (0x00000000u)
00972 
00973 #define EDMA3_CCRL_EMCRH_E41_MASK        (0x00000200u)
00974 #define EDMA3_CCRL_EMCRH_E41_SHIFT       (0x00000009u)
00975 #define EDMA3_CCRL_EMCRH_E41_RESETVAL    (0x00000000u)
00976 
00977 #define EDMA3_CCRL_EMCRH_E40_MASK        (0x00000100u)
00978 #define EDMA3_CCRL_EMCRH_E40_SHIFT       (0x00000008u)
00979 #define EDMA3_CCRL_EMCRH_E40_RESETVAL    (0x00000000u)
00980 
00981 #define EDMA3_CCRL_EMCRH_E39_MASK        (0x00000080u)
00982 #define EDMA3_CCRL_EMCRH_E39_SHIFT       (0x00000007u)
00983 #define EDMA3_CCRL_EMCRH_E39_RESETVAL    (0x00000000u)
00984 
00985 #define EDMA3_CCRL_EMCRH_E38_MASK        (0x00000040u)
00986 #define EDMA3_CCRL_EMCRH_E38_SHIFT       (0x00000006u)
00987 #define EDMA3_CCRL_EMCRH_E38_RESETVAL    (0x00000000u)
00988 
00989 #define EDMA3_CCRL_EMCRH_E37_MASK        (0x00000020u)
00990 #define EDMA3_CCRL_EMCRH_E37_SHIFT       (0x00000005u)
00991 #define EDMA3_CCRL_EMCRH_E37_RESETVAL    (0x00000000u)
00992 
00993 #define EDMA3_CCRL_EMCRH_E36_MASK        (0x00000010u)
00994 #define EDMA3_CCRL_EMCRH_E36_SHIFT       (0x00000004u)
00995 #define EDMA3_CCRL_EMCRH_E36_RESETVAL    (0x00000000u)
00996 
00997 #define EDMA3_CCRL_EMCRH_E35_MASK        (0x00000008u)
00998 #define EDMA3_CCRL_EMCRH_E35_SHIFT       (0x00000003u)
00999 #define EDMA3_CCRL_EMCRH_E35_RESETVAL    (0x00000000u)
01000 
01001 #define EDMA3_CCRL_EMCRH_E34_MASK        (0x00000004u)
01002 #define EDMA3_CCRL_EMCRH_E34_SHIFT       (0x00000002u)
01003 #define EDMA3_CCRL_EMCRH_E34_RESETVAL    (0x00000000u)
01004 
01005 #define EDMA3_CCRL_EMCRH_E33_MASK        (0x00000002u)
01006 #define EDMA3_CCRL_EMCRH_E33_SHIFT       (0x00000001u)
01007 #define EDMA3_CCRL_EMCRH_E33_RESETVAL    (0x00000000u)
01008 
01009 #define EDMA3_CCRL_EMCRH_E32_MASK        (0x00000001u)
01010 #define EDMA3_CCRL_EMCRH_E32_SHIFT       (0x00000000u)
01011 #define EDMA3_CCRL_EMCRH_E32_RESETVAL    (0x00000000u)
01012 
01013 #define EDMA3_CCRL_EMCRH_RESETVAL        (0x00000000u)
01014 
01015 /* QEMR */
01016 
01017 #define EDMA3_CCRL_QEMR_E7_MASK          (0x00000080u)
01018 #define EDMA3_CCRL_QEMR_E7_SHIFT         (0x00000007u)
01019 #define EDMA3_CCRL_QEMR_E7_RESETVAL      (0x00000000u)
01020 
01021 #define EDMA3_CCRL_QEMR_E6_MASK          (0x00000040u)
01022 #define EDMA3_CCRL_QEMR_E6_SHIFT         (0x00000006u)
01023 #define EDMA3_CCRL_QEMR_E6_RESETVAL      (0x00000000u)
01024 
01025 #define EDMA3_CCRL_QEMR_E5_MASK          (0x00000020u)
01026 #define EDMA3_CCRL_QEMR_E5_SHIFT         (0x00000005u)
01027 #define EDMA3_CCRL_QEMR_E5_RESETVAL      (0x00000000u)
01028 
01029 #define EDMA3_CCRL_QEMR_E4_MASK          (0x00000010u)
01030 #define EDMA3_CCRL_QEMR_E4_SHIFT         (0x00000004u)
01031 #define EDMA3_CCRL_QEMR_E4_RESETVAL      (0x00000000u)
01032 
01033 #define EDMA3_CCRL_QEMR_E3_MASK          (0x00000008u)
01034 #define EDMA3_CCRL_QEMR_E3_SHIFT         (0x00000003u)
01035 #define EDMA3_CCRL_QEMR_E3_RESETVAL      (0x00000000u)
01036 
01037 #define EDMA3_CCRL_QEMR_E2_MASK          (0x00000004u)
01038 #define EDMA3_CCRL_QEMR_E2_SHIFT         (0x00000002u)
01039 #define EDMA3_CCRL_QEMR_E2_RESETVAL      (0x00000000u)
01040 
01041 #define EDMA3_CCRL_QEMR_E1_MASK          (0x00000002u)
01042 #define EDMA3_CCRL_QEMR_E1_SHIFT         (0x00000001u)
01043 #define EDMA3_CCRL_QEMR_E1_RESETVAL      (0x00000000u)
01044 
01045 #define EDMA3_CCRL_QEMR_E0_MASK          (0x00000001u)
01046 #define EDMA3_CCRL_QEMR_E0_SHIFT         (0x00000000u)
01047 #define EDMA3_CCRL_QEMR_E0_RESETVAL      (0x00000000u)
01048 
01049 #define EDMA3_CCRL_QEMR_RESETVAL         (0x00000000u)
01050 
01051 /* QEMCR */
01052 
01053 #define EDMA3_CCRL_QEMCR_E7_MASK         (0x00000080u)
01054 #define EDMA3_CCRL_QEMCR_E7_SHIFT        (0x00000007u)
01055 #define EDMA3_CCRL_QEMCR_E7_RESETVAL     (0x00000000u)
01056 
01057 #define EDMA3_CCRL_QEMCR_E6_MASK         (0x00000040u)
01058 #define EDMA3_CCRL_QEMCR_E6_SHIFT        (0x00000006u)
01059 #define EDMA3_CCRL_QEMCR_E6_RESETVAL     (0x00000000u)
01060 
01061 #define EDMA3_CCRL_QEMCR_E5_MASK         (0x00000020u)
01062 #define EDMA3_CCRL_QEMCR_E5_SHIFT        (0x00000005u)
01063 #define EDMA3_CCRL_QEMCR_E5_RESETVAL     (0x00000000u)
01064 
01065 #define EDMA3_CCRL_QEMCR_E4_MASK         (0x00000010u)
01066 #define EDMA3_CCRL_QEMCR_E4_SHIFT        (0x00000004u)
01067 #define EDMA3_CCRL_QEMCR_E4_RESETVAL     (0x00000000u)
01068 
01069 #define EDMA3_CCRL_QEMCR_E3_MASK         (0x00000008u)
01070 #define EDMA3_CCRL_QEMCR_E3_SHIFT        (0x00000003u)
01071 #define EDMA3_CCRL_QEMCR_E3_RESETVAL     (0x00000000u)
01072 
01073 #define EDMA3_CCRL_QEMCR_E2_MASK         (0x00000004u)
01074 #define EDMA3_CCRL_QEMCR_E2_SHIFT        (0x00000002u)
01075 #define EDMA3_CCRL_QEMCR_E2_RESETVAL     (0x00000000u)
01076 
01077 #define EDMA3_CCRL_QEMCR_E1_MASK         (0x00000002u)
01078 #define EDMA3_CCRL_QEMCR_E1_SHIFT        (0x00000001u)
01079 #define EDMA3_CCRL_QEMCR_E1_RESETVAL     (0x00000000u)
01080 
01081 #define EDMA3_CCRL_QEMCR_E0_MASK         (0x00000001u)
01082 #define EDMA3_CCRL_QEMCR_E0_SHIFT        (0x00000000u)
01083 #define EDMA3_CCRL_QEMCR_E0_RESETVAL     (0x00000000u)
01084 
01085 #define EDMA3_CCRL_QEMCR_RESETVAL        (0x00000000u)
01086 
01087 /* CCERR */
01088 
01089 #define EDMA3_CCRL_CCERR_TCCERR_MASK     (0x00010000u)
01090 #define EDMA3_CCRL_CCERR_TCCERR_SHIFT    (0x00000010u)
01091 #define EDMA3_CCRL_CCERR_TCCERR_RESETVAL (0x00000000u)
01092 
01093 #define EDMA3_CCRL_CCERR_QTHRXCD7_MASK   (0x00000080u)
01094 #define EDMA3_CCRL_CCERR_QTHRXCD7_SHIFT  (0x00000007u)
01095 #define EDMA3_CCRL_CCERR_QTHRXCD7_RESETVAL (0x00000000u)
01096 
01097 #define EDMA3_CCRL_CCERR_QTHRXCD6_MASK   (0x00000040u)
01098 #define EDMA3_CCRL_CCERR_QTHRXCD6_SHIFT  (0x00000006u)
01099 #define EDMA3_CCRL_CCERR_QTHRXCD6_RESETVAL (0x00000000u)
01100 
01101 #define EDMA3_CCRL_CCERR_QTHRXCD5_MASK   (0x00000020u)
01102 #define EDMA3_CCRL_CCERR_QTHRXCD5_SHIFT  (0x00000005u)
01103 #define EDMA3_CCRL_CCERR_QTHRXCD5_RESETVAL (0x00000000u)
01104 
01105 #define EDMA3_CCRL_CCERR_QTHRXCD4_MASK   (0x00000010u)
01106 #define EDMA3_CCRL_CCERR_QTHRXCD4_SHIFT  (0x00000004u)
01107 #define EDMA3_CCRL_CCERR_QTHRXCD4_RESETVAL (0x00000000u)
01108 
01109 #define EDMA3_CCRL_CCERR_QTHRXCD3_MASK   (0x00000008u)
01110 #define EDMA3_CCRL_CCERR_QTHRXCD3_SHIFT  (0x00000003u)
01111 #define EDMA3_CCRL_CCERR_QTHRXCD3_RESETVAL (0x00000000u)
01112 
01113 #define EDMA3_CCRL_CCERR_QTHRXCD2_MASK   (0x00000004u)
01114 #define EDMA3_CCRL_CCERR_QTHRXCD2_SHIFT  (0x00000002u)
01115 #define EDMA3_CCRL_CCERR_QTHRXCD2_RESETVAL (0x00000000u)
01116 
01117 #define EDMA3_CCRL_CCERR_QTHRXCD1_MASK   (0x00000002u)
01118 #define EDMA3_CCRL_CCERR_QTHRXCD1_SHIFT  (0x00000001u)
01119 #define EDMA3_CCRL_CCERR_QTHRXCD1_RESETVAL (0x00000000u)
01120 
01121 #define EDMA3_CCRL_CCERR_QTHRXCD0_MASK   (0x00000001u)
01122 #define EDMA3_CCRL_CCERR_QTHRXCD0_SHIFT  (0x00000000u)
01123 #define EDMA3_CCRL_CCERR_QTHRXCD0_RESETVAL (0x00000000u)
01124 
01125 #define EDMA3_CCRL_CCERR_RESETVAL        (0x00000000u)
01126 
01127 /* CCERRCLR */
01128 
01129 #define EDMA3_CCRL_CCERRCLR_TCCERR_MASK  (0x00010000u)
01130 #define EDMA3_CCRL_CCERRCLR_TCCERR_SHIFT (0x00000010u)
01131 #define EDMA3_CCRL_CCERRCLR_TCCERR_RESETVAL (0x00000000u)
01132 
01133 #define EDMA3_CCRL_CCERRCLR_QTHRXCD7_MASK (0x00000080u)
01134 #define EDMA3_CCRL_CCERRCLR_QTHRXCD7_SHIFT (0x00000007u)
01135 #define EDMA3_CCRL_CCERRCLR_QTHRXCD7_RESETVAL (0x00000000u)
01136 
01137 #define EDMA3_CCRL_CCERRCLR_QTHRXCD6_MASK (0x00000040u)
01138 #define EDMA3_CCRL_CCERRCLR_QTHRXCD6_SHIFT (0x00000006u)
01139 #define EDMA3_CCRL_CCERRCLR_QTHRXCD6_RESETVAL (0x00000000u)
01140 
01141 #define EDMA3_CCRL_CCERRCLR_QTHRXCD5_MASK (0x00000020u)
01142 #define EDMA3_CCRL_CCERRCLR_QTHRXCD5_SHIFT (0x00000005u)
01143 #define EDMA3_CCRL_CCERRCLR_QTHRXCD5_RESETVAL (0x00000000u)
01144 
01145 #define EDMA3_CCRL_CCERRCLR_QTHRXCD4_MASK (0x00000010u)
01146 #define EDMA3_CCRL_CCERRCLR_QTHRXCD4_SHIFT (0x00000004u)
01147 #define EDMA3_CCRL_CCERRCLR_QTHRXCD4_RESETVAL (0x00000000u)
01148 
01149 #define EDMA3_CCRL_CCERRCLR_QTHRXCD3_MASK (0x00000008u)
01150 #define EDMA3_CCRL_CCERRCLR_QTHRXCD3_SHIFT (0x00000003u)
01151 #define EDMA3_CCRL_CCERRCLR_QTHRXCD3_RESETVAL (0x00000000u)
01152 
01153 #define EDMA3_CCRL_CCERRCLR_QTHRXCD2_MASK (0x00000004u)
01154 #define EDMA3_CCRL_CCERRCLR_QTHRXCD2_SHIFT (0x00000002u)
01155 #define EDMA3_CCRL_CCERRCLR_QTHRXCD2_RESETVAL (0x00000000u)
01156 
01157 #define EDMA3_CCRL_CCERRCLR_QTHRXCD1_MASK (0x00000002u)
01158 #define EDMA3_CCRL_CCERRCLR_QTHRXCD1_SHIFT (0x00000001u)
01159 #define EDMA3_CCRL_CCERRCLR_QTHRXCD1_RESETVAL (0x00000000u)
01160 
01161 #define EDMA3_CCRL_CCERRCLR_QTHRXCD0_MASK (0x00000001u)
01162 #define EDMA3_CCRL_CCERRCLR_QTHRXCD0_SHIFT (0x00000000u)
01163 #define EDMA3_CCRL_CCERRCLR_QTHRXCD0_RESETVAL (0x00000000u)
01164 
01165 #define EDMA3_CCRL_CCERRCLR_RESETVAL     (0x00000000u)
01166 
01167 /* EEVAL */
01168 
01169 #define EDMA3_CCRL_EEVAL_SET_MASK        (0x00000002u)
01170 #define EDMA3_CCRL_EEVAL_SET_SHIFT       (0x00000001u)
01171 #define EDMA3_CCRL_EEVAL_SET_RESETVAL    (0x00000000u)
01172 
01173 /*----SET Tokens----*/
01174 #define EDMA3_CCRL_EEVAL_SET_SET         (0x00000001u)
01175 
01176 #define EDMA3_CCRL_EEVAL_EVAL_MASK       (0x00000001u)
01177 #define EDMA3_CCRL_EEVAL_EVAL_SHIFT      (0x00000000u)
01178 #define EDMA3_CCRL_EEVAL_EVAL_RESETVAL   (0x00000000u)
01179 
01180 /*----EVAL Tokens----*/
01181 #define EDMA3_CCRL_EEVAL_EVAL_EVAL       (0x00000001u)
01182 
01183 #define EDMA3_CCRL_EEVAL_RESETVAL        (0x00000000u)
01184 
01185 /* DRAE */
01186 
01187 #define EDMA3_CCRL_DRAE_E31_MASK         (0x80000000u)
01188 #define EDMA3_CCRL_DRAE_E31_SHIFT        (0x0000001Fu)
01189 #define EDMA3_CCRL_DRAE_E31_RESETVAL     (0x00000000u)
01190 
01191 #define EDMA3_CCRL_DRAE_E30_MASK         (0x40000000u)
01192 #define EDMA3_CCRL_DRAE_E30_SHIFT        (0x0000001Eu)
01193 #define EDMA3_CCRL_DRAE_E30_RESETVAL     (0x00000000u)
01194 
01195 #define EDMA3_CCRL_DRAE_E29_MASK         (0x20000000u)
01196 #define EDMA3_CCRL_DRAE_E29_SHIFT        (0x0000001Du)
01197 #define EDMA3_CCRL_DRAE_E29_RESETVAL     (0x00000000u)
01198 
01199 #define EDMA3_CCRL_DRAE_E28_MASK         (0x10000000u)
01200 #define EDMA3_CCRL_DRAE_E28_SHIFT        (0x0000001Cu)
01201 #define EDMA3_CCRL_DRAE_E28_RESETVAL     (0x00000000u)
01202 
01203 #define EDMA3_CCRL_DRAE_E27_MASK         (0x08000000u)
01204 #define EDMA3_CCRL_DRAE_E27_SHIFT        (0x0000001Bu)
01205 #define EDMA3_CCRL_DRAE_E27_RESETVAL     (0x00000000u)
01206 
01207 #define EDMA3_CCRL_DRAE_E26_MASK         (0x04000000u)
01208 #define EDMA3_CCRL_DRAE_E26_SHIFT        (0x0000001Au)
01209 #define EDMA3_CCRL_DRAE_E26_RESETVAL     (0x00000000u)
01210 
01211 #define EDMA3_CCRL_DRAE_E25_MASK         (0x02000000u)
01212 #define EDMA3_CCRL_DRAE_E25_SHIFT        (0x00000019u)
01213 #define EDMA3_CCRL_DRAE_E25_RESETVAL     (0x00000000u)
01214 
01215 #define EDMA3_CCRL_DRAE_E24_MASK         (0x01000000u)
01216 #define EDMA3_CCRL_DRAE_E24_SHIFT        (0x00000018u)
01217 #define EDMA3_CCRL_DRAE_E24_RESETVAL     (0x00000000u)
01218 
01219 #define EDMA3_CCRL_DRAE_E23_MASK         (0x00800000u)
01220 #define EDMA3_CCRL_DRAE_E23_SHIFT        (0x00000017u)
01221 #define EDMA3_CCRL_DRAE_E23_RESETVAL     (0x00000000u)
01222 
01223 #define EDMA3_CCRL_DRAE_E22_MASK         (0x00400000u)
01224 #define EDMA3_CCRL_DRAE_E22_SHIFT        (0x00000016u)
01225 #define EDMA3_CCRL_DRAE_E22_RESETVAL     (0x00000000u)
01226 
01227 #define EDMA3_CCRL_DRAE_E21_MASK         (0x00200000u)
01228 #define EDMA3_CCRL_DRAE_E21_SHIFT        (0x00000015u)
01229 #define EDMA3_CCRL_DRAE_E21_RESETVAL     (0x00000000u)
01230 
01231 #define EDMA3_CCRL_DRAE_E20_MASK         (0x00100000u)
01232 #define EDMA3_CCRL_DRAE_E20_SHIFT        (0x00000014u)
01233 #define EDMA3_CCRL_DRAE_E20_RESETVAL     (0x00000000u)
01234 
01235 #define EDMA3_CCRL_DRAE_E19_MASK         (0x00080000u)
01236 #define EDMA3_CCRL_DRAE_E19_SHIFT        (0x00000013u)
01237 #define EDMA3_CCRL_DRAE_E19_RESETVAL     (0x00000000u)
01238 
01239 #define EDMA3_CCRL_DRAE_E18_MASK         (0x00040000u)
01240 #define EDMA3_CCRL_DRAE_E18_SHIFT        (0x00000012u)
01241 #define EDMA3_CCRL_DRAE_E18_RESETVAL     (0x00000000u)
01242 
01243 #define EDMA3_CCRL_DRAE_E17_MASK         (0x00020000u)
01244 #define EDMA3_CCRL_DRAE_E17_SHIFT        (0x00000011u)
01245 #define EDMA3_CCRL_DRAE_E17_RESETVAL     (0x00000000u)
01246 
01247 #define EDMA3_CCRL_DRAE_E16_MASK         (0x00010000u)
01248 #define EDMA3_CCRL_DRAE_E16_SHIFT        (0x00000010u)
01249 #define EDMA3_CCRL_DRAE_E16_RESETVAL     (0x00000000u)
01250 
01251 #define EDMA3_CCRL_DRAE_E15_MASK         (0x00008000u)
01252 #define EDMA3_CCRL_DRAE_E15_SHIFT        (0x0000000Fu)
01253 #define EDMA3_CCRL_DRAE_E15_RESETVAL     (0x00000000u)
01254 
01255 #define EDMA3_CCRL_DRAE_E14_MASK         (0x00004000u)
01256 #define EDMA3_CCRL_DRAE_E14_SHIFT        (0x0000000Eu)
01257 #define EDMA3_CCRL_DRAE_E14_RESETVAL     (0x00000000u)
01258 
01259 #define EDMA3_CCRL_DRAE_E13_MASK         (0x00002000u)
01260 #define EDMA3_CCRL_DRAE_E13_SHIFT        (0x0000000Du)
01261 #define EDMA3_CCRL_DRAE_E13_RESETVAL     (0x00000000u)
01262 
01263 #define EDMA3_CCRL_DRAE_E12_MASK         (0x00001000u)
01264 #define EDMA3_CCRL_DRAE_E12_SHIFT        (0x0000000Cu)
01265 #define EDMA3_CCRL_DRAE_E12_RESETVAL     (0x00000000u)
01266 
01267 #define EDMA3_CCRL_DRAE_E11_MASK         (0x00000800u)
01268 #define EDMA3_CCRL_DRAE_E11_SHIFT        (0x0000000Bu)
01269 #define EDMA3_CCRL_DRAE_E11_RESETVAL     (0x00000000u)
01270 
01271 #define EDMA3_CCRL_DRAE_E10_MASK         (0x00000400u)
01272 #define EDMA3_CCRL_DRAE_E10_SHIFT        (0x0000000Au)
01273 #define EDMA3_CCRL_DRAE_E10_RESETVAL     (0x00000000u)
01274 
01275 #define EDMA3_CCRL_DRAE_E9_MASK          (0x00000200u)
01276 #define EDMA3_CCRL_DRAE_E9_SHIFT         (0x00000009u)
01277 #define EDMA3_CCRL_DRAE_E9_RESETVAL      (0x00000000u)
01278 
01279 #define EDMA3_CCRL_DRAE_E8_MASK          (0x00000100u)
01280 #define EDMA3_CCRL_DRAE_E8_SHIFT         (0x00000008u)
01281 #define EDMA3_CCRL_DRAE_E8_RESETVAL      (0x00000000u)
01282 
01283 #define EDMA3_CCRL_DRAE_E7_MASK          (0x00000080u)
01284 #define EDMA3_CCRL_DRAE_E7_SHIFT         (0x00000007u)
01285 #define EDMA3_CCRL_DRAE_E7_RESETVAL      (0x00000000u)
01286 
01287 #define EDMA3_CCRL_DRAE_E6_MASK          (0x00000040u)
01288 #define EDMA3_CCRL_DRAE_E6_SHIFT         (0x00000006u)
01289 #define EDMA3_CCRL_DRAE_E6_RESETVAL      (0x00000000u)
01290 
01291 #define EDMA3_CCRL_DRAE_E5_MASK          (0x00000020u)
01292 #define EDMA3_CCRL_DRAE_E5_SHIFT         (0x00000005u)
01293 #define EDMA3_CCRL_DRAE_E5_RESETVAL      (0x00000000u)
01294 
01295 #define EDMA3_CCRL_DRAE_E4_MASK          (0x00000010u)
01296 #define EDMA3_CCRL_DRAE_E4_SHIFT         (0x00000004u)
01297 #define EDMA3_CCRL_DRAE_E4_RESETVAL      (0x00000000u)
01298 
01299 #define EDMA3_CCRL_DRAE_E3_MASK          (0x00000008u)
01300 #define EDMA3_CCRL_DRAE_E3_SHIFT         (0x00000003u)
01301 #define EDMA3_CCRL_DRAE_E3_RESETVAL      (0x00000000u)
01302 
01303 #define EDMA3_CCRL_DRAE_E2_MASK          (0x00000004u)
01304 #define EDMA3_CCRL_DRAE_E2_SHIFT         (0x00000002u)
01305 #define EDMA3_CCRL_DRAE_E2_RESETVAL      (0x00000000u)
01306 
01307 #define EDMA3_CCRL_DRAE_E1_MASK          (0x00000002u)
01308 #define EDMA3_CCRL_DRAE_E1_SHIFT         (0x00000001u)
01309 #define EDMA3_CCRL_DRAE_E1_RESETVAL      (0x00000000u)
01310 
01311 #define EDMA3_CCRL_DRAE_E0_MASK          (0x00000001u)
01312 #define EDMA3_CCRL_DRAE_E0_SHIFT         (0x00000000u)
01313 #define EDMA3_CCRL_DRAE_E0_RESETVAL      (0x00000000u)
01314 
01315 #define EDMA3_CCRL_DRAE_RESETVAL         (0x00000000u)
01316 
01317 /* DRAEH */
01318 
01319 #define EDMA3_CCRL_DRAEH_E63_MASK        (0x80000000u)
01320 #define EDMA3_CCRL_DRAEH_E63_SHIFT       (0x0000001Fu)
01321 #define EDMA3_CCRL_DRAEH_E63_RESETVAL    (0x00000000u)
01322 
01323 #define EDMA3_CCRL_DRAEH_E62_MASK        (0x40000000u)
01324 #define EDMA3_CCRL_DRAEH_E62_SHIFT       (0x0000001Eu)
01325 #define EDMA3_CCRL_DRAEH_E62_RESETVAL    (0x00000000u)
01326 
01327 #define EDMA3_CCRL_DRAEH_E61_MASK        (0x20000000u)
01328 #define EDMA3_CCRL_DRAEH_E61_SHIFT       (0x0000001Du)
01329 #define EDMA3_CCRL_DRAEH_E61_RESETVAL    (0x00000000u)
01330 
01331 #define EDMA3_CCRL_DRAEH_E60_MASK        (0x10000000u)
01332 #define EDMA3_CCRL_DRAEH_E60_SHIFT       (0x0000001Cu)
01333 #define EDMA3_CCRL_DRAEH_E60_RESETVAL    (0x00000000u)
01334 
01335 #define EDMA3_CCRL_DRAEH_E59_MASK        (0x08000000u)
01336 #define EDMA3_CCRL_DRAEH_E59_SHIFT       (0x0000001Bu)
01337 #define EDMA3_CCRL_DRAEH_E59_RESETVAL    (0x00000000u)
01338 
01339 #define EDMA3_CCRL_DRAEH_E58_MASK        (0x04000000u)
01340 #define EDMA3_CCRL_DRAEH_E58_SHIFT       (0x0000001Au)
01341 #define EDMA3_CCRL_DRAEH_E58_RESETVAL    (0x00000000u)
01342 
01343 #define EDMA3_CCRL_DRAEH_E57_MASK        (0x02000000u)
01344 #define EDMA3_CCRL_DRAEH_E57_SHIFT       (0x00000019u)
01345 #define EDMA3_CCRL_DRAEH_E57_RESETVAL    (0x00000000u)
01346 
01347 #define EDMA3_CCRL_DRAEH_E56_MASK        (0x01000000u)
01348 #define EDMA3_CCRL_DRAEH_E56_SHIFT       (0x00000018u)
01349 #define EDMA3_CCRL_DRAEH_E56_RESETVAL    (0x00000000u)
01350 
01351 #define EDMA3_CCRL_DRAEH_E55_MASK        (0x00800000u)
01352 #define EDMA3_CCRL_DRAEH_E55_SHIFT       (0x00000017u)
01353 #define EDMA3_CCRL_DRAEH_E55_RESETVAL    (0x00000000u)
01354 
01355 #define EDMA3_CCRL_DRAEH_E54_MASK        (0x00400000u)
01356 #define EDMA3_CCRL_DRAEH_E54_SHIFT       (0x00000016u)
01357 #define EDMA3_CCRL_DRAEH_E54_RESETVAL    (0x00000000u)
01358 
01359 #define EDMA3_CCRL_DRAEH_E53_MASK        (0x00200000u)
01360 #define EDMA3_CCRL_DRAEH_E53_SHIFT       (0x00000015u)
01361 #define EDMA3_CCRL_DRAEH_E53_RESETVAL    (0x00000000u)
01362 
01363 #define EDMA3_CCRL_DRAEH_E52_MASK        (0x00100000u)
01364 #define EDMA3_CCRL_DRAEH_E52_SHIFT       (0x00000014u)
01365 #define EDMA3_CCRL_DRAEH_E52_RESETVAL    (0x00000000u)
01366 
01367 #define EDMA3_CCRL_DRAEH_E51_MASK        (0x00080000u)
01368 #define EDMA3_CCRL_DRAEH_E51_SHIFT       (0x00000013u)
01369 #define EDMA3_CCRL_DRAEH_E51_RESETVAL    (0x00000000u)
01370 
01371 #define EDMA3_CCRL_DRAEH_E50_MASK        (0x00040000u)
01372 #define EDMA3_CCRL_DRAEH_E50_SHIFT       (0x00000012u)
01373 #define EDMA3_CCRL_DRAEH_E50_RESETVAL    (0x00000000u)
01374 
01375 #define EDMA3_CCRL_DRAEH_E49_MASK        (0x00020000u)
01376 #define EDMA3_CCRL_DRAEH_E49_SHIFT       (0x00000011u)
01377 #define EDMA3_CCRL_DRAEH_E49_RESETVAL    (0x00000000u)
01378 
01379 #define EDMA3_CCRL_DRAEH_E48_MASK        (0x00010000u)
01380 #define EDMA3_CCRL_DRAEH_E48_SHIFT       (0x00000010u)
01381 #define EDMA3_CCRL_DRAEH_E48_RESETVAL    (0x00000000u)
01382 
01383 #define EDMA3_CCRL_DRAEH_E47_MASK        (0x00008000u)
01384 #define EDMA3_CCRL_DRAEH_E47_SHIFT       (0x0000000Fu)
01385 #define EDMA3_CCRL_DRAEH_E47_RESETVAL    (0x00000000u)
01386 
01387 #define EDMA3_CCRL_DRAEH_E46_MASK        (0x00004000u)
01388 #define EDMA3_CCRL_DRAEH_E46_SHIFT       (0x0000000Eu)
01389 #define EDMA3_CCRL_DRAEH_E46_RESETVAL    (0x00000000u)
01390 
01391 #define EDMA3_CCRL_DRAEH_E45_MASK        (0x00002000u)
01392 #define EDMA3_CCRL_DRAEH_E45_SHIFT       (0x0000000Du)
01393 #define EDMA3_CCRL_DRAEH_E45_RESETVAL    (0x00000000u)
01394 
01395 #define EDMA3_CCRL_DRAEH_E44_MASK        (0x00001000u)
01396 #define EDMA3_CCRL_DRAEH_E44_SHIFT       (0x0000000Cu)
01397 #define EDMA3_CCRL_DRAEH_E44_RESETVAL    (0x00000000u)
01398 
01399 #define EDMA3_CCRL_DRAEH_E43_MASK        (0x00000800u)
01400 #define EDMA3_CCRL_DRAEH_E43_SHIFT       (0x0000000Bu)
01401 #define EDMA3_CCRL_DRAEH_E43_RESETVAL    (0x00000000u)
01402 
01403 #define EDMA3_CCRL_DRAEH_E42_MASK        (0x00000400u)
01404 #define EDMA3_CCRL_DRAEH_E42_SHIFT       (0x0000000Au)
01405 #define EDMA3_CCRL_DRAEH_E42_RESETVAL    (0x00000000u)
01406 
01407 #define EDMA3_CCRL_DRAEH_E41_MASK        (0x00000200u)
01408 #define EDMA3_CCRL_DRAEH_E41_SHIFT       (0x00000009u)
01409 #define EDMA3_CCRL_DRAEH_E41_RESETVAL    (0x00000000u)
01410 
01411 #define EDMA3_CCRL_DRAEH_E40_MASK        (0x00000100u)
01412 #define EDMA3_CCRL_DRAEH_E40_SHIFT       (0x00000008u)
01413 #define EDMA3_CCRL_DRAEH_E40_RESETVAL    (0x00000000u)
01414 
01415 #define EDMA3_CCRL_DRAEH_E39_MASK        (0x00000080u)
01416 #define EDMA3_CCRL_DRAEH_E39_SHIFT       (0x00000007u)
01417 #define EDMA3_CCRL_DRAEH_E39_RESETVAL    (0x00000000u)
01418 
01419 #define EDMA3_CCRL_DRAEH_E38_MASK        (0x00000040u)
01420 #define EDMA3_CCRL_DRAEH_E38_SHIFT       (0x00000006u)
01421 #define EDMA3_CCRL_DRAEH_E38_RESETVAL    (0x00000000u)
01422 
01423 #define EDMA3_CCRL_DRAEH_E37_MASK        (0x00000020u)
01424 #define EDMA3_CCRL_DRAEH_E37_SHIFT       (0x00000005u)
01425 #define EDMA3_CCRL_DRAEH_E37_RESETVAL    (0x00000000u)
01426 
01427 #define EDMA3_CCRL_DRAEH_E36_MASK        (0x00000010u)
01428 #define EDMA3_CCRL_DRAEH_E36_SHIFT       (0x00000004u)
01429 #define EDMA3_CCRL_DRAEH_E36_RESETVAL    (0x00000000u)
01430 
01431 #define EDMA3_CCRL_DRAEH_E35_MASK        (0x00000008u)
01432 #define EDMA3_CCRL_DRAEH_E35_SHIFT       (0x00000003u)
01433 #define EDMA3_CCRL_DRAEH_E35_RESETVAL    (0x00000000u)
01434 
01435 #define EDMA3_CCRL_DRAEH_E34_MASK        (0x00000004u)
01436 #define EDMA3_CCRL_DRAEH_E34_SHIFT       (0x00000002u)
01437 #define EDMA3_CCRL_DRAEH_E34_RESETVAL    (0x00000000u)
01438 
01439 #define EDMA3_CCRL_DRAEH_E33_MASK        (0x00000002u)
01440 #define EDMA3_CCRL_DRAEH_E33_SHIFT       (0x00000001u)
01441 #define EDMA3_CCRL_DRAEH_E33_RESETVAL    (0x00000000u)
01442 
01443 #define EDMA3_CCRL_DRAEH_E32_MASK        (0x00000001u)
01444 #define EDMA3_CCRL_DRAEH_E32_SHIFT       (0x00000000u)
01445 #define EDMA3_CCRL_DRAEH_E32_RESETVAL    (0x00000000u)
01446 
01447 #define EDMA3_CCRL_DRAEH_RESETVAL        (0x00000000u)
01448 
01449 /* QRAE */
01450 
01451 #define EDMA3_CCRL_QRAE_E7_MASK          (0x00000080u)
01452 #define EDMA3_CCRL_QRAE_E7_SHIFT         (0x00000007u)
01453 #define EDMA3_CCRL_QRAE_E7_RESETVAL      (0x00000000u)
01454 
01455 #define EDMA3_CCRL_QRAE_E6_MASK          (0x00000080u)
01456 #define EDMA3_CCRL_QRAE_E6_SHIFT         (0x00000007u)
01457 #define EDMA3_CCRL_QRAE_E6_RESETVAL      (0x00000000u)
01458 
01459 #define EDMA3_CCRL_QRAE_E5_MASK          (0x00000080u)
01460 #define EDMA3_CCRL_QRAE_E5_SHIFT         (0x00000007u)
01461 #define EDMA3_CCRL_QRAE_E5_RESETVAL      (0x00000000u)
01462 
01463 #define EDMA3_CCRL_QRAE_E4_MASK          (0x00000080u)
01464 #define EDMA3_CCRL_QRAE_E4_SHIFT         (0x00000007u)
01465 #define EDMA3_CCRL_QRAE_E4_RESETVAL      (0x00000000u)
01466 
01467 #define EDMA3_CCRL_QRAE_E3_MASK          (0x00000080u)
01468 #define EDMA3_CCRL_QRAE_E3_SHIFT         (0x00000007u)
01469 #define EDMA3_CCRL_QRAE_E3_RESETVAL      (0x00000000u)
01470 
01471 #define EDMA3_CCRL_QRAE_E2_MASK          (0x00000080u)
01472 #define EDMA3_CCRL_QRAE_E2_SHIFT         (0x00000007u)
01473 #define EDMA3_CCRL_QRAE_E2_RESETVAL      (0x00000000u)
01474 
01475 #define EDMA3_CCRL_QRAE_E1_MASK          (0x00000080u)
01476 #define EDMA3_CCRL_QRAE_E1_SHIFT         (0x00000007u)
01477 #define EDMA3_CCRL_QRAE_E1_RESETVAL      (0x00000000u)
01478 
01479 #define EDMA3_CCRL_QRAE_E0_MASK          (0x00000080u)
01480 #define EDMA3_CCRL_QRAE_E0_SHIFT         (0x00000007u)
01481 #define EDMA3_CCRL_QRAE_E0_RESETVAL      (0x00000000u)
01482 
01483 #define EDMA3_CCRL_QRAE_RESERVED_MASK    (0x0000007Fu)
01484 #define EDMA3_CCRL_QRAE_RESERVED_SHIFT   (0x00000000u)
01485 #define EDMA3_CCRL_QRAE_RESERVED_RESETVAL (0x00000000u)
01486 
01487 #define EDMA3_CCRL_QRAE_RESETVAL         (0x00000000u)
01488 
01489 /* QUEEVT_ENTRY */
01490 
01491 #define EDMA3_CCRL_QUEEVT_ENTRY_RESV_MASK (0xFFFFFF00u)
01492 #define EDMA3_CCRL_QUEEVT_ENTRY_RESV_SHIFT (0x00000008u)
01493 #define EDMA3_CCRL_QUEEVT_ENTRY_RESV_RESETVAL (0x00000000u)
01494 
01495 #define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_MASK (0x000000C0u)
01496 #define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_SHIFT (0x00000006u)
01497 #define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SRC_RESETVAL (0x00000000u)
01498 
01499 #define EDMA3_CCRL_QUEEVT_ENTRY_EVT_MASK (0x0000003Fu)
01500 #define EDMA3_CCRL_QUEEVT_ENTRY_EVT_SHIFT (0x00000000u)
01501 #define EDMA3_CCRL_QUEEVT_ENTRY_EVT_RESETVAL (0x00000000u)
01502 
01503 #define EDMA3_CCRL_QUEEVT_ENTRY_RESETVAL (0x00000000u)
01504 
01505 /* QSTAT */
01506 
01507 #define EDMA3_CCRL_QSTAT_THRXD_MASK      (0x01000000u)
01508 #define EDMA3_CCRL_QSTAT_THRXD_SHIFT     (0x00000018u)
01509 #define EDMA3_CCRL_QSTAT_THRXD_RESETVAL  (0x00000000u)
01510 
01511 #define EDMA3_CCRL_QSTAT_RESERVED_MASK   (0x00600000u)
01512 #define EDMA3_CCRL_QSTAT_RESERVED_SHIFT  (0x00000015u)
01513 #define EDMA3_CCRL_QSTAT_RESERVED_RESETVAL (0x00000000u)
01514 
01515 #define EDMA3_CCRL_QSTAT_WM_MASK         (0x001F0000u)
01516 #define EDMA3_CCRL_QSTAT_WM_SHIFT        (0x00000010u)
01517 #define EDMA3_CCRL_QSTAT_WM_RESETVAL     (0x00000000u)
01518 
01519 #define EDMA3_CCRL_QSTAT_NUMVAL_MASK     (0x00001F00u)
01520 #define EDMA3_CCRL_QSTAT_NUMVAL_SHIFT    (0x00000008u)
01521 #define EDMA3_CCRL_QSTAT_NUMVAL_RESETVAL (0x00000000u)
01522 
01523 #define EDMA3_CCRL_QSTAT_STRTPTR_MASK    (0x0000000Fu)
01524 #define EDMA3_CCRL_QSTAT_STRTPTR_SHIFT   (0x00000000u)
01525 #define EDMA3_CCRL_QSTAT_STRTPTR_RESETVAL (0x00000000u)
01526 
01527 #define EDMA3_CCRL_QSTAT_RESETVAL        (0x00000000u)
01528 
01529 /* QWMTHRA */
01530 
01531 #define EDMA3_CCRL_QWMTHRA_Q3_MASK       (0x1F000000u)
01532 #define EDMA3_CCRL_QWMTHRA_Q3_SHIFT      (0x00000018u)
01533 #define EDMA3_CCRL_QWMTHRA_Q3_RESETVAL   (0x00000010u)
01534 
01535 #define EDMA3_CCRL_QWMTHRA_Q2_MASK       (0x001F0000u)
01536 #define EDMA3_CCRL_QWMTHRA_Q2_SHIFT      (0x00000010u)
01537 #define EDMA3_CCRL_QWMTHRA_Q2_RESETVAL   (0x00000010u)
01538 
01539 #define EDMA3_CCRL_QWMTHRA_Q1_MASK       (0x00001F00u)
01540 #define EDMA3_CCRL_QWMTHRA_Q1_SHIFT      (0x00000008u)
01541 #define EDMA3_CCRL_QWMTHRA_Q1_RESETVAL   (0x00000010u)
01542 
01543 #define EDMA3_CCRL_QWMTHRA_Q0_MASK       (0x0000001Fu)
01544 #define EDMA3_CCRL_QWMTHRA_Q0_SHIFT      (0x00000000u)
01545 #define EDMA3_CCRL_QWMTHRA_Q0_RESETVAL   (0x00000010u)
01546 
01547 #define EDMA3_CCRL_QWMTHRA_RESETVAL      (0x10101010u)
01548 
01549 /* QWMTHRB */
01550 
01551 #define EDMA3_CCRL_QWMTHRB_Q7_MASK       (0x1F000000u)
01552 #define EDMA3_CCRL_QWMTHRB_Q7_SHIFT      (0x00000018u)
01553 #define EDMA3_CCRL_QWMTHRB_Q7_RESETVAL   (0x00000010u)
01554 
01555 #define EDMA3_CCRL_QWMTHRB_Q6_MASK       (0x001F0000u)
01556 #define EDMA3_CCRL_QWMTHRB_Q6_SHIFT      (0x00000010u)
01557 #define EDMA3_CCRL_QWMTHRB_Q6_RESETVAL   (0x00000010u)
01558 
01559 #define EDMA3_CCRL_QWMTHRB_Q5_MASK       (0x00001F00u)
01560 #define EDMA3_CCRL_QWMTHRB_Q5_SHIFT      (0x00000008u)
01561 #define EDMA3_CCRL_QWMTHRB_Q5_RESETVAL   (0x00000010u)
01562 
01563 #define EDMA3_CCRL_QWMTHRB_Q4_MASK       (0x0000001Fu)
01564 #define EDMA3_CCRL_QWMTHRB_Q4_SHIFT      (0x00000000u)
01565 #define EDMA3_CCRL_QWMTHRB_Q4_RESETVAL   (0x00000010u)
01566 
01567 #define EDMA3_CCRL_QWMTHRB_RESETVAL      (0x10101010u)
01568 
01569 /* CCSTAT */
01570 
01571 #define EDMA3_CCRL_CCSTAT_QUEACTV7_MASK  (0x00800000u)
01572 #define EDMA3_CCRL_CCSTAT_QUEACTV7_SHIFT (0x00000017u)
01573 #define EDMA3_CCRL_CCSTAT_QUEACTV7_RESETVAL (0x00000000u)
01574 
01575 /*----QUEACTV7 Tokens----*/
01576 #define EDMA3_CCRL_CCSTAT_QUEACTV7_NONE  (0x00000000u)
01577 #define EDMA3_CCRL_CCSTAT_QUEACTV7_ACTIVE (0x00000001u)
01578 
01579 #define EDMA3_CCRL_CCSTAT_QUEACTV6_MASK  (0x00400000u)
01580 #define EDMA3_CCRL_CCSTAT_QUEACTV6_SHIFT (0x00000016u)
01581 #define EDMA3_CCRL_CCSTAT_QUEACTV6_RESETVAL (0x00000000u)
01582 
01583 /*----QUEACTV6 Tokens----*/
01584 #define EDMA3_CCRL_CCSTAT_QUEACTV6_NONE  (0x00000000u)
01585 #define EDMA3_CCRL_CCSTAT_QUEACTV6_ACTIVE (0x00000001u)
01586 
01587 #define EDMA3_CCRL_CCSTAT_QUEACTV5_MASK  (0x00200000u)
01588 #define EDMA3_CCRL_CCSTAT_QUEACTV5_SHIFT (0x00000015u)
01589 #define EDMA3_CCRL_CCSTAT_QUEACTV5_RESETVAL (0x00000000u)
01590 
01591 /*----QUEACTV5 Tokens----*/
01592 #define EDMA3_CCRL_CCSTAT_QUEACTV5_NONE  (0x00000000u)
01593 #define EDMA3_CCRL_CCSTAT_QUEACTV5_ACTIVE (0x00000001u)
01594 
01595 #define EDMA3_CCRL_CCSTAT_QUEACTV4_MASK  (0x00100000u)
01596 #define EDMA3_CCRL_CCSTAT_QUEACTV4_SHIFT (0x00000014u)
01597 #define EDMA3_CCRL_CCSTAT_QUEACTV4_RESETVAL (0x00000000u)
01598 
01599 /*----QUEACTV4 Tokens----*/
01600 #define EDMA3_CCRL_CCSTAT_QUEACTV4_NONE  (0x00000000u)
01601 #define EDMA3_CCRL_CCSTAT_QUEACTV4_ACTIVE (0x00000001u)
01602 
01603 #define EDMA3_CCRL_CCSTAT_QUEACTV3_MASK  (0x00080000u)
01604 #define EDMA3_CCRL_CCSTAT_QUEACTV3_SHIFT (0x00000013u)
01605 #define EDMA3_CCRL_CCSTAT_QUEACTV3_RESETVAL (0x00000000u)
01606 
01607 /*----QUEACTV3 Tokens----*/
01608 #define EDMA3_CCRL_CCSTAT_QUEACTV3_NONE  (0x00000000u)
01609 #define EDMA3_CCRL_CCSTAT_QUEACTV3_ACTIVE (0x00000001u)
01610 
01611 #define EDMA3_CCRL_CCSTAT_QUEACTV2_MASK  (0x00040000u)
01612 #define EDMA3_CCRL_CCSTAT_QUEACTV2_SHIFT (0x00000012u)
01613 #define EDMA3_CCRL_CCSTAT_QUEACTV2_RESETVAL (0x00000000u)
01614 
01615 /*----QUEACTV2 Tokens----*/
01616 #define EDMA3_CCRL_CCSTAT_QUEACTV2_NONE  (0x00000000u)
01617 #define EDMA3_CCRL_CCSTAT_QUEACTV2_ACTIVE (0x00000001u)
01618 
01619 #define EDMA3_CCRL_CCSTAT_QUEACTV1_MASK  (0x00020000u)
01620 #define EDMA3_CCRL_CCSTAT_QUEACTV1_SHIFT (0x00000011u)
01621 #define EDMA3_CCRL_CCSTAT_QUEACTV1_RESETVAL (0x00000000u)
01622 
01623 /*----QUEACTV1 Tokens----*/
01624 #define EDMA3_CCRL_CCSTAT_QUEACTV1_NONE  (0x00000000u)
01625 #define EDMA3_CCRL_CCSTAT_QUEACTV1_ACTIVE (0x00000001u)
01626 
01627 #define EDMA3_CCRL_CCSTAT_QUEACTV0_MASK  (0x00010000u)
01628 #define EDMA3_CCRL_CCSTAT_QUEACTV0_SHIFT (0x00000010u)
01629 #define EDMA3_CCRL_CCSTAT_QUEACTV0_RESETVAL (0x00000000u)
01630 
01631 /*----QUEACTV0 Tokens----*/
01632 #define EDMA3_CCRL_CCSTAT_QUEACTV0_NONE  (0x00000000u)
01633 #define EDMA3_CCRL_CCSTAT_QUEACTV0_ACTIVE (0x00000001u)
01634 
01635 #define EDMA3_CCRL_CCSTAT_COMPACT_MASK   (0x00003F00u)
01636 #define EDMA3_CCRL_CCSTAT_COMPACT_SHIFT  (0x00000008u)
01637 #define EDMA3_CCRL_CCSTAT_COMPACT_RESETVAL (0x00000000u)
01638 
01639 /*----COMPACT Tokens----*/
01640 #define EDMA3_CCRL_CCSTAT_COMPACT_NONE   (0x00000000u)
01641 
01642 #define EDMA3_CCRL_CCSTAT_ACTV_MASK      (0x00000010u)
01643 #define EDMA3_CCRL_CCSTAT_ACTV_SHIFT     (0x00000004u)
01644 #define EDMA3_CCRL_CCSTAT_ACTV_RESETVAL  (0x00000000u)
01645 
01646 /*----ACTV Tokens----*/
01647 #define EDMA3_CCRL_CCSTAT_ACTV_IDLE      (0x00000000u)
01648 #define EDMA3_CCRL_CCSTAT_ACTV_BUSY      (0x00000001u)
01649 
01650 #define EDMA3_CCRL_CCSTAT_TRACTV_MASK    (0x00000004u)
01651 #define EDMA3_CCRL_CCSTAT_TRACTV_SHIFT   (0x00000002u)
01652 #define EDMA3_CCRL_CCSTAT_TRACTV_RESETVAL (0x00000000u)
01653 
01654 /*----TRACTV Tokens----*/
01655 #define EDMA3_CCRL_CCSTAT_TRACTV_NONE    (0x00000000u)
01656 #define EDMA3_CCRL_CCSTAT_TRACTV_ACTIVE  (0x00000001u)
01657 
01658 #define EDMA3_CCRL_CCSTAT_QEVTACTV_MASK  (0x00000002u)
01659 #define EDMA3_CCRL_CCSTAT_QEVTACTV_SHIFT (0x00000001u)
01660 #define EDMA3_CCRL_CCSTAT_QEVTACTV_RESETVAL (0x00000000u)
01661 
01662 /*----QEVTACTV Tokens----*/
01663 #define EDMA3_CCRL_CCSTAT_QEVTACTV_NONE  (0x00000000u)
01664 #define EDMA3_CCRL_CCSTAT_QEVTACTV_ACTIVE (0x00000001u)
01665 
01666 #define EDMA3_CCRL_CCSTAT_EVTACTV_MASK   (0x00000001u)
01667 #define EDMA3_CCRL_CCSTAT_EVTACTV_SHIFT  (0x00000000u)
01668 #define EDMA3_CCRL_CCSTAT_EVTACTV_RESETVAL (0x00000000u)
01669 
01670 /*----EVTACTV Tokens----*/
01671 #define EDMA3_CCRL_CCSTAT_EVTACTV_NONE   (0x00000000u)
01672 #define EDMA3_CCRL_CCSTAT_EVTACTV_ACTIVE (0x00000001u)
01673 
01674 #define EDMA3_CCRL_CCSTAT_RESETVAL       (0x00000000u)
01675 
01676 /* AETCTL */
01677 
01678 #define EDMA3_CCRL_AETCTL_EN_MASK        (0x80000000u)
01679 #define EDMA3_CCRL_AETCTL_EN_SHIFT       (0x0000001Fu)
01680 #define EDMA3_CCRL_AETCTL_EN_RESETVAL    (0x00000000u)
01681 
01682 /*----EN Tokens----*/
01683 #define EDMA3_CCRL_AETCTL_EN_DISABLE     (0x00000000u)
01684 #define EDMA3_CCRL_AETCTL_EN_ENABLE      (0x00000001u)
01685 
01686 #define EDMA3_CCRL_AETCTL_ENDINT_MASK    (0x00003F00u)
01687 #define EDMA3_CCRL_AETCTL_ENDINT_SHIFT   (0x00000008u)
01688 #define EDMA3_CCRL_AETCTL_ENDINT_RESETVAL (0x00000000u)
01689 
01690 #define EDMA3_CCRL_AETCTL_TYPE_MASK      (0x00000040u)
01691 #define EDMA3_CCRL_AETCTL_TYPE_SHIFT     (0x00000006u)
01692 #define EDMA3_CCRL_AETCTL_TYPE_RESETVAL  (0x00000000u)
01693 
01694 /*----TYPE Tokens----*/
01695 #define EDMA3_CCRL_AETCTL_TYPE_DMA       (0x00000000u)
01696 #define EDMA3_CCRL_AETCTL_TYPE_QDMA      (0x00000001u)
01697 
01698 #define EDMA3_CCRL_AETCTL_STRTEVT_MASK   (0x0000003Fu)
01699 #define EDMA3_CCRL_AETCTL_STRTEVT_SHIFT  (0x00000000u)
01700 #define EDMA3_CCRL_AETCTL_STRTEVT_RESETVAL (0x00000000u)
01701 
01702 #define EDMA3_CCRL_AETCTL_RESETVAL       (0x00000000u)
01703 
01704 /* AETSTAT */
01705 
01706 #define EDMA3_CCRL_AETSTAT_STAT_MASK     (0x00000001u)
01707 #define EDMA3_CCRL_AETSTAT_STAT_SHIFT    (0x00000000u)
01708 #define EDMA3_CCRL_AETSTAT_STAT_RESETVAL (0x00000000u)
01709 
01710 /*----STAT Tokens----*/
01711 #define EDMA3_CCRL_AETSTAT_STAT_LOW      (0x00000000u)
01712 #define EDMA3_CCRL_AETSTAT_STAT_HIGH     (0x00000001u)
01713 
01714 #define EDMA3_CCRL_AETSTAT_RESETVAL      (0x00000000u)
01715 
01716 /* AETCMD */
01717 
01718 #define EDMA3_CCRL_AETCMD_CLR_MASK       (0x00000001u)
01719 #define EDMA3_CCRL_AETCMD_CLR_SHIFT      (0x00000000u)
01720 #define EDMA3_CCRL_AETCMD_CLR_RESETVAL   (0x00000000u)
01721 
01722 /*----CLR Tokens----*/
01723 #define EDMA3_CCRL_AETCMD_CLR_CLEAR      (0x00000001u)
01724 
01725 #define EDMA3_CCRL_AETCMD_RESETVAL       (0x00000000u)
01726 
01727 /* MPFAR */
01728 
01729 #define EDMA3_CCRL_MPFAR_FADDR_MASK      (0xFFFFFFFFu)
01730 #define EDMA3_CCRL_MPFAR_FADDR_SHIFT     (0x00000000u)
01731 #define EDMA3_CCRL_MPFAR_FADDR_RESETVAL  (0x00000000u)
01732 
01733 #define EDMA3_CCRL_MPFAR_RESETVAL        (0x00000000u)
01734 
01735 /* MPFSR */
01736 
01737 #define EDMA3_CCRL_MPFSR_FID_MASK        (0x00001E00u)
01738 #define EDMA3_CCRL_MPFSR_FID_SHIFT       (0x00000009u)
01739 #define EDMA3_CCRL_MPFSR_FID_RESETVAL    (0x00000009u)
01740 
01741 #define EDMA3_CCRL_MPFSR_SECE_MASK       (0x00000080u)
01742 #define EDMA3_CCRL_MPFSR_SECE_SHIFT      (0x00000007u)
01743 #define EDMA3_CCRL_MPFSR_SECE_RESETVAL   (0x00000000u)
01744 
01745 #define EDMA3_CCRL_MPFSR_SRE_MASK        (0x00000020u)
01746 #define EDMA3_CCRL_MPFSR_SRE_SHIFT       (0x00000005u)
01747 #define EDMA3_CCRL_MPFSR_SRE_RESETVAL    (0x00000000u)
01748 
01749 #define EDMA3_CCRL_MPFSR_SWE_MASK        (0x00000010u)
01750 #define EDMA3_CCRL_MPFSR_SWE_SHIFT       (0x00000004u)
01751 #define EDMA3_CCRL_MPFSR_SWE_RESETVAL    (0x00000000u)
01752 
01753 #define EDMA3_CCRL_MPFSR_SXE_MASK        (0x00000008u)
01754 #define EDMA3_CCRL_MPFSR_SXE_SHIFT       (0x00000003u)
01755 #define EDMA3_CCRL_MPFSR_SXE_RESETVAL    (0x00000000u)
01756 
01757 #define EDMA3_CCRL_MPFSR_URE_MASK        (0x00000004u)
01758 #define EDMA3_CCRL_MPFSR_URE_SHIFT       (0x00000002u)
01759 #define EDMA3_CCRL_MPFSR_URE_RESETVAL    (0x00000000u)
01760 
01761 #define EDMA3_CCRL_MPFSR_UWE_MASK        (0x00000002u)
01762 #define EDMA3_CCRL_MPFSR_UWE_SHIFT       (0x00000001u)
01763 #define EDMA3_CCRL_MPFSR_UWE_RESETVAL    (0x00000000u)
01764 
01765 #define EDMA3_CCRL_MPFSR_UXE_MASK        (0x00000001u)
01766 #define EDMA3_CCRL_MPFSR_UXE_SHIFT       (0x00000000u)
01767 #define EDMA3_CCRL_MPFSR_UXE_RESETVAL    (0x00000000u)
01768 
01769 #define EDMA3_CCRL_MPFSR_RESETVAL        (0x00001200u)
01770 
01771 /* MPFCR */
01772 
01773 #define EDMA3_CCRL_MPFCR_MPFCLR_MASK     (0x00000001u)
01774 #define EDMA3_CCRL_MPFCR_MPFCLR_SHIFT    (0x00000000u)
01775 #define EDMA3_CCRL_MPFCR_MPFCLR_RESETVAL (0x00000000u)
01776 
01777 #define EDMA3_CCRL_MPFCR_RESETVAL        (0x00000000u)
01778 
01779 /* MPPAG */
01780 
01781 #define EDMA3_CCRL_MPPAG_AID5_MASK       (0x00008000u)
01782 #define EDMA3_CCRL_MPPAG_AID5_SHIFT      (0x0000000Fu)
01783 #define EDMA3_CCRL_MPPAG_AID5_RESETVAL   (0x00000000u)
01784 
01785 /*----AID5 Tokens----*/
01786 #define EDMA3_CCRL_MPPAG_AID5_BLOCK      (0x00000000u)
01787 #define EDMA3_CCRL_MPPAG_AID5_PERMIT     (0x00000001u)
01788 
01789 #define EDMA3_CCRL_MPPAG_AID4_MASK       (0x00004000u)
01790 #define EDMA3_CCRL_MPPAG_AID4_SHIFT      (0x0000000Eu)
01791 #define EDMA3_CCRL_MPPAG_AID4_RESETVAL   (0x00000000u)
01792 
01793 /*----AID4 Tokens----*/
01794 #define EDMA3_CCRL_MPPAG_AID4_BLOCK      (0x00000000u)
01795 #define EDMA3_CCRL_MPPAG_AID4_PERMIT     (0x00000001u)
01796 
01797 #define EDMA3_CCRL_MPPAG_AID3_MASK       (0x00002000u)
01798 #define EDMA3_CCRL_MPPAG_AID3_SHIFT      (0x0000000Du)
01799 #define EDMA3_CCRL_MPPAG_AID3_RESETVAL   (0x00000000u)
01800 
01801 /*----AID3 Tokens----*/
01802 #define EDMA3_CCRL_MPPAG_AID3_BLOCK      (0x00000000u)
01803 #define EDMA3_CCRL_MPPAG_AID3_PERMIT     (0x00000001u)
01804 
01805 #define EDMA3_CCRL_MPPAG_AID2_MASK       (0x00001000u)
01806 #define EDMA3_CCRL_MPPAG_AID2_SHIFT      (0x0000000Cu)
01807 #define EDMA3_CCRL_MPPAG_AID2_RESETVAL   (0x00000000u)
01808 
01809 /*----AID2 Tokens----*/
01810 #define EDMA3_CCRL_MPPAG_AID2_BLOCK      (0x00000000u)
01811 #define EDMA3_CCRL_MPPAG_AID2_PERMIT     (0x00000001u)
01812 
01813 #define EDMA3_CCRL_MPPAG_AID1_MASK       (0x00000800u)
01814 #define EDMA3_CCRL_MPPAG_AID1_SHIFT      (0x0000000Bu)
01815 #define EDMA3_CCRL_MPPAG_AID1_RESETVAL   (0x00000000u)
01816 
01817 /*----AID1 Tokens----*/
01818 #define EDMA3_CCRL_MPPAG_AID1_BLOCK      (0x00000000u)
01819 #define EDMA3_CCRL_MPPAG_AID1_PERMIT     (0x00000001u)
01820 
01821 #define EDMA3_CCRL_MPPAG_AID0_MASK       (0x00000400u)
01822 #define EDMA3_CCRL_MPPAG_AID0_SHIFT      (0x0000000Au)
01823 #define EDMA3_CCRL_MPPAG_AID0_RESETVAL   (0x00000000u)
01824 
01825 /*----AID0 Tokens----*/
01826 #define EDMA3_CCRL_MPPAG_AID0_BLOCK      (0x00000000u)
01827 #define EDMA3_CCRL_MPPAG_AID0_PERMIT     (0x00000001u)
01828 
01829 #define EDMA3_CCRL_MPPAG_EXT_MASK        (0x00000200u)
01830 #define EDMA3_CCRL_MPPAG_EXT_SHIFT       (0x00000009u)
01831 #define EDMA3_CCRL_MPPAG_EXT_RESETVAL    (0x00000000u)
01832 
01833 /*----EXT Tokens----*/
01834 #define EDMA3_CCRL_MPPAG_EXT_BLOCK       (0x00000000u)
01835 #define EDMA3_CCRL_MPPAG_EXT_PERMIT      (0x00000001u)
01836 
01837 #define EDMA3_CCRL_MPPAG_LCL_MASK        (0x00000100u)
01838 #define EDMA3_CCRL_MPPAG_LCL_SHIFT       (0x00000008u)
01839 #define EDMA3_CCRL_MPPAG_LCL_RESETVAL    (0x00000000u)
01840 
01841 #define EDMA3_CCRL_MPPAG_NS_MASK         (0x00000080u)
01842 #define EDMA3_CCRL_MPPAG_NS_SHIFT        (0x00000007u)
01843 #define EDMA3_CCRL_MPPAG_NS_RESETVAL     (0x00000000u)
01844 
01845 /*----NS Tokens----*/
01846 #define EDMA3_CCRL_MPPAG_NS_SECURE       (0x00000000u)
01847 #define EDMA3_CCRL_MPPAG_NS_NONSECURE    (0x00000001u)
01848 
01849 #define EDMA3_CCRL_MPPAG_EMU_MASK        (0x00000040u)
01850 #define EDMA3_CCRL_MPPAG_EMU_SHIFT       (0x00000006u)
01851 #define EDMA3_CCRL_MPPAG_EMU_RESETVAL    (0x00000000u)
01852 
01853 /*----EMU Tokens----*/
01854 #define EDMA3_CCRL_MPPAG_EMU_BLOCK       (0x00000000u)
01855 #define EDMA3_CCRL_MPPAG_EMU_PERMIT      (0x00000001u)
01856 
01857 #define EDMA3_CCRL_MPPAG_SR_MASK         (0x00000020u)
01858 #define EDMA3_CCRL_MPPAG_SR_SHIFT        (0x00000005u)
01859 #define EDMA3_CCRL_MPPAG_SR_RESETVAL     (0x00000000u)
01860 
01861 /*----SR Tokens----*/
01862 #define EDMA3_CCRL_MPPAG_SR_BLOCK        (0x00000000u)
01863 #define EDMA3_CCRL_MPPAG_SR_PERMIT       (0x00000001u)
01864 
01865 #define EDMA3_CCRL_MPPAG_SW_MASK         (0x00000010u)
01866 #define EDMA3_CCRL_MPPAG_SW_SHIFT        (0x00000004u)
01867 #define EDMA3_CCRL_MPPAG_SW_RESETVAL     (0x00000000u)
01868 
01869 /*----SW Tokens----*/
01870 #define EDMA3_CCRL_MPPAG_SW_BLOCK        (0x00000000u)
01871 #define EDMA3_CCRL_MPPAG_SW_PERMIT       (0x00000001u)
01872 
01873 #define EDMA3_CCRL_MPPAG_SX_MASK         (0x00000008u)
01874 #define EDMA3_CCRL_MPPAG_SX_SHIFT        (0x00000003u)
01875 #define EDMA3_CCRL_MPPAG_SX_RESETVAL     (0x00000000u)
01876 
01877 /*----SX Tokens----*/
01878 #define EDMA3_CCRL_MPPAG_SX_BLOCK        (0x00000000u)
01879 #define EDMA3_CCRL_MPPAG_SX_PERMIT       (0x00000001u)
01880 
01881 #define EDMA3_CCRL_MPPAG_UR_MASK         (0x00000004u)
01882 #define EDMA3_CCRL_MPPAG_UR_SHIFT        (0x00000002u)
01883 #define EDMA3_CCRL_MPPAG_UR_RESETVAL     (0x00000000u)
01884 
01885 /*----UR Tokens----*/
01886 #define EDMA3_CCRL_MPPAG_UR_BLOCK        (0x00000000u)
01887 #define EDMA3_CCRL_MPPAG_UR_PERMIT       (0x00000001u)
01888 
01889 #define EDMA3_CCRL_MPPAG_UW_MASK         (0x00000002u)
01890 #define EDMA3_CCRL_MPPAG_UW_SHIFT        (0x00000001u)
01891 #define EDMA3_CCRL_MPPAG_UW_RESETVAL     (0x00000000u)
01892 
01893 /*----UW Tokens----*/
01894 #define EDMA3_CCRL_MPPAG_UW_BLOCK        (0x00000000u)
01895 #define EDMA3_CCRL_MPPAG_UW_PERMIT       (0x00000001u)
01896 
01897 #define EDMA3_CCRL_MPPAG_UX_MASK         (0x00000001u)
01898 #define EDMA3_CCRL_MPPAG_UX_SHIFT        (0x00000000u)
01899 #define EDMA3_CCRL_MPPAG_UX_RESETVAL     (0x00000000u)
01900 
01901 /*----UX Tokens----*/
01902 #define EDMA3_CCRL_MPPAG_UX_BLOCK        (0x00000000u)
01903 #define EDMA3_CCRL_MPPAG_UX_PERMIT       (0x00000001u)
01904 
01905 #define EDMA3_CCRL_MPPAG_RESETVAL        (0x00000000u)
01906 
01907 /* MPPA */
01908 
01909 #define EDMA3_CCRL_MPPA_AID5_MASK        (0x00008000u)
01910 #define EDMA3_CCRL_MPPA_AID5_SHIFT       (0x0000000Fu)
01911 #define EDMA3_CCRL_MPPA_AID5_RESETVAL    (0x00000000u)
01912 
01913 /*----AID5 Tokens----*/
01914 #define EDMA3_CCRL_MPPA_AID5_BLOCK       (0x00000000u)
01915 #define EDMA3_CCRL_MPPA_AID5_PERMIT      (0x00000001u)
01916 
01917 #define EDMA3_CCRL_MPPA_AID4_MASK        (0x00004000u)
01918 #define EDMA3_CCRL_MPPA_AID4_SHIFT       (0x0000000Eu)
01919 #define EDMA3_CCRL_MPPA_AID4_RESETVAL    (0x00000000u)
01920 
01921 /*----AID4 Tokens----*/
01922 #define EDMA3_CCRL_MPPA_AID4_BLOCK       (0x00000000u)
01923 #define EDMA3_CCRL_MPPA_AID4_PERMIT      (0x00000001u)
01924 
01925 #define EDMA3_CCRL_MPPA_AID3_MASK        (0x00002000u)
01926 #define EDMA3_CCRL_MPPA_AID3_SHIFT       (0x0000000Du)
01927 #define EDMA3_CCRL_MPPA_AID3_RESETVAL    (0x00000000u)
01928 
01929 /*----AID3 Tokens----*/
01930 #define EDMA3_CCRL_MPPA_AID3_BLOCK       (0x00000000u)
01931 #define EDMA3_CCRL_MPPA_AID3_PERMIT      (0x00000001u)
01932 
01933 #define EDMA3_CCRL_MPPA_AID2_MASK        (0x00001000u)
01934 #define EDMA3_CCRL_MPPA_AID2_SHIFT       (0x0000000Cu)
01935 #define EDMA3_CCRL_MPPA_AID2_RESETVAL    (0x00000000u)
01936 
01937 /*----AID2 Tokens----*/
01938 #define EDMA3_CCRL_MPPA_AID2_BLOCK       (0x00000000u)
01939 #define EDMA3_CCRL_MPPA_AID2_PERMIT      (0x00000001u)
01940 
01941 #define EDMA3_CCRL_MPPA_AID1_MASK        (0x00000800u)
01942 #define EDMA3_CCRL_MPPA_AID1_SHIFT       (0x0000000Bu)
01943 #define EDMA3_CCRL_MPPA_AID1_RESETVAL    (0x00000000u)
01944 
01945 /*----AID1 Tokens----*/
01946 #define EDMA3_CCRL_MPPA_AID1_BLOCK       (0x00000000u)
01947 #define EDMA3_CCRL_MPPA_AID1_PERMIT      (0x00000001u)
01948 
01949 #define EDMA3_CCRL_MPPA_AID0_MASK        (0x00000400u)
01950 #define EDMA3_CCRL_MPPA_AID0_SHIFT       (0x0000000Au)
01951 #define EDMA3_CCRL_MPPA_AID0_RESETVAL    (0x00000000u)
01952 
01953 /*----AID0 Tokens----*/
01954 #define EDMA3_CCRL_MPPA_AID0_BLOCK       (0x00000000u)
01955 #define EDMA3_CCRL_MPPA_AID0_PERMIT      (0x00000001u)
01956 
01957 #define EDMA3_CCRL_MPPA_EXT_MASK         (0x00000200u)
01958 #define EDMA3_CCRL_MPPA_EXT_SHIFT        (0x00000009u)
01959 #define EDMA3_CCRL_MPPA_EXT_RESETVAL     (0x00000000u)
01960 
01961 /*----EXT Tokens----*/
01962 #define EDMA3_CCRL_MPPA_EXT_BLOCK        (0x00000000u)
01963 #define EDMA3_CCRL_MPPA_EXT_PERMIT       (0x00000001u)
01964 
01965 #define EDMA3_CCRL_MPPA_LCL_MASK         (0x00000100u)
01966 #define EDMA3_CCRL_MPPA_LCL_SHIFT        (0x00000008u)
01967 #define EDMA3_CCRL_MPPA_LCL_RESETVAL     (0x00000000u)
01968 
01969 #define EDMA3_CCRL_MPPA_NS_MASK          (0x00000080u)
01970 #define EDMA3_CCRL_MPPA_NS_SHIFT         (0x00000007u)
01971 #define EDMA3_CCRL_MPPA_NS_RESETVAL      (0x00000000u)
01972 
01973 /*----NS Tokens----*/
01974 #define EDMA3_CCRL_MPPA_NS_SECURE        (0x00000000u)
01975 #define EDMA3_CCRL_MPPA_NS_NONSECURE     (0x00000001u)
01976 
01977 #define EDMA3_CCRL_MPPA_EMU_MASK         (0x00000040u)
01978 #define EDMA3_CCRL_MPPA_EMU_SHIFT        (0x00000006u)
01979 #define EDMA3_CCRL_MPPA_EMU_RESETVAL     (0x00000000u)
01980 
01981 /*----EMU Tokens----*/
01982 #define EDMA3_CCRL_MPPA_EMU_BLOCK        (0x00000000u)
01983 #define EDMA3_CCRL_MPPA_EMU_PERMIT       (0x00000001u)
01984 
01985 #define EDMA3_CCRL_MPPA_SR_MASK          (0x00000020u)
01986 #define EDMA3_CCRL_MPPA_SR_SHIFT         (0x00000005u)
01987 #define EDMA3_CCRL_MPPA_SR_RESETVAL      (0x00000000u)
01988 
01989 /*----SR Tokens----*/
01990 #define EDMA3_CCRL_MPPA_SR_BLOCK         (0x00000000u)
01991 #define EDMA3_CCRL_MPPA_SR_PERMIT        (0x00000001u)
01992 
01993 #define EDMA3_CCRL_MPPA_SW_MASK          (0x00000010u)
01994 #define EDMA3_CCRL_MPPA_SW_SHIFT         (0x00000004u)
01995 #define EDMA3_CCRL_MPPA_SW_RESETVAL      (0x00000000u)
01996 
01997 /*----SW Tokens----*/
01998 #define EDMA3_CCRL_MPPA_SW_BLOCK         (0x00000000u)
01999 #define EDMA3_CCRL_MPPA_SW_PERMIT        (0x00000001u)
02000 
02001 #define EDMA3_CCRL_MPPA_SX_MASK          (0x00000008u)
02002 #define EDMA3_CCRL_MPPA_SX_SHIFT         (0x00000003u)
02003 #define EDMA3_CCRL_MPPA_SX_RESETVAL      (0x00000000u)
02004 
02005 /*----SX Tokens----*/
02006 #define EDMA3_CCRL_MPPA_SX_BLOCK         (0x00000000u)
02007 #define EDMA3_CCRL_MPPA_SX_PERMIT        (0x00000001u)
02008 
02009 #define EDMA3_CCRL_MPPA_UR_MASK          (0x00000004u)
02010 #define EDMA3_CCRL_MPPA_UR_SHIFT         (0x00000002u)
02011 #define EDMA3_CCRL_MPPA_UR_RESETVAL      (0x00000000u)
02012 
02013 /*----UR Tokens----*/
02014 #define EDMA3_CCRL_MPPA_UR_BLOCK         (0x00000000u)
02015 #define EDMA3_CCRL_MPPA_UR_PERMIT        (0x00000001u)
02016 
02017 #define EDMA3_CCRL_MPPA_UW_MASK          (0x00000002u)
02018 #define EDMA3_CCRL_MPPA_UW_SHIFT         (0x00000001u)
02019 #define EDMA3_CCRL_MPPA_UW_RESETVAL      (0x00000000u)
02020 
02021 /*----UW Tokens----*/
02022 #define EDMA3_CCRL_MPPA_UW_BLOCK         (0x00000000u)
02023 #define EDMA3_CCRL_MPPA_UW_PERMIT        (0x00000001u)
02024 
02025 #define EDMA3_CCRL_MPPA_UX_MASK          (0x00000001u)
02026 #define EDMA3_CCRL_MPPA_UX_SHIFT         (0x00000000u)
02027 #define EDMA3_CCRL_MPPA_UX_RESETVAL      (0x00000000u)
02028 
02029 /*----UX Tokens----*/
02030 #define EDMA3_CCRL_MPPA_UX_BLOCK         (0x00000000u)
02031 #define EDMA3_CCRL_MPPA_UX_PERMIT        (0x00000001u)
02032 
02033 #define EDMA3_CCRL_MPPA_RESETVAL         (0x00000000u)
02034 
02035 /* ER */
02036 
02037 #define EDMA3_CCRL_ER_E31_MASK           (0x80000000u)
02038 #define EDMA3_CCRL_ER_E31_SHIFT          (0x0000001Fu)
02039 #define EDMA3_CCRL_ER_E31_RESETVAL       (0x00000000u)
02040 
02041 #define EDMA3_CCRL_ER_E30_MASK           (0x40000000u)
02042 #define EDMA3_CCRL_ER_E30_SHIFT          (0x0000001Eu)
02043 #define EDMA3_CCRL_ER_E30_RESETVAL       (0x00000000u)
02044 
02045 #define EDMA3_CCRL_ER_E29_MASK           (0x20000000u)
02046 #define EDMA3_CCRL_ER_E29_SHIFT          (0x0000001Du)
02047 #define EDMA3_CCRL_ER_E29_RESETVAL       (0x00000000u)
02048 
02049 #define EDMA3_CCRL_ER_E28_MASK           (0x10000000u)
02050 #define EDMA3_CCRL_ER_E28_SHIFT          (0x0000001Cu)
02051 #define EDMA3_CCRL_ER_E28_RESETVAL       (0x00000000u)
02052 
02053 #define EDMA3_CCRL_ER_E27_MASK           (0x08000000u)
02054 #define EDMA3_CCRL_ER_E27_SHIFT          (0x0000001Bu)
02055 #define EDMA3_CCRL_ER_E27_RESETVAL       (0x00000000u)
02056 
02057 #define EDMA3_CCRL_ER_E26_MASK           (0x04000000u)
02058 #define EDMA3_CCRL_ER_E26_SHIFT          (0x0000001Au)
02059 #define EDMA3_CCRL_ER_E26_RESETVAL       (0x00000000u)
02060 
02061 #define EDMA3_CCRL_ER_E25_MASK           (0x02000000u)
02062 #define EDMA3_CCRL_ER_E25_SHIFT          (0x00000019u)
02063 #define EDMA3_CCRL_ER_E25_RESETVAL       (0x00000000u)
02064 
02065 #define EDMA3_CCRL_ER_E24_MASK           (0x01000000u)
02066 #define EDMA3_CCRL_ER_E24_SHIFT          (0x00000018u)
02067 #define EDMA3_CCRL_ER_E24_RESETVAL       (0x00000000u)
02068 
02069 #define EDMA3_CCRL_ER_E23_MASK           (0x00800000u)
02070 #define EDMA3_CCRL_ER_E23_SHIFT          (0x00000017u)
02071 #define EDMA3_CCRL_ER_E23_RESETVAL       (0x00000000u)
02072 
02073 #define EDMA3_CCRL_ER_E22_MASK           (0x00400000u)
02074 #define EDMA3_CCRL_ER_E22_SHIFT          (0x00000016u)
02075 #define EDMA3_CCRL_ER_E22_RESETVAL       (0x00000000u)
02076 
02077 #define EDMA3_CCRL_ER_E21_MASK           (0x00200000u)
02078 #define EDMA3_CCRL_ER_E21_SHIFT          (0x00000015u)
02079 #define EDMA3_CCRL_ER_E21_RESETVAL       (0x00000000u)
02080 
02081 #define EDMA3_CCRL_ER_E20_MASK           (0x00100000u)
02082 #define EDMA3_CCRL_ER_E20_SHIFT          (0x00000014u)
02083 #define EDMA3_CCRL_ER_E20_RESETVAL       (0x00000000u)
02084 
02085 #define EDMA3_CCRL_ER_E19_MASK           (0x00080000u)
02086 #define EDMA3_CCRL_ER_E19_SHIFT          (0x00000013u)
02087 #define EDMA3_CCRL_ER_E19_RESETVAL       (0x00000000u)
02088 
02089 #define EDMA3_CCRL_ER_E18_MASK           (0x00040000u)
02090 #define EDMA3_CCRL_ER_E18_SHIFT          (0x00000012u)
02091 #define EDMA3_CCRL_ER_E18_RESETVAL       (0x00000000u)
02092 
02093 #define EDMA3_CCRL_ER_E17_MASK           (0x00020000u)
02094 #define EDMA3_CCRL_ER_E17_SHIFT          (0x00000011u)
02095 #define EDMA3_CCRL_ER_E17_RESETVAL       (0x00000000u)
02096 
02097 #define EDMA3_CCRL_ER_E16_MASK           (0x00010000u)
02098 #define EDMA3_CCRL_ER_E16_SHIFT          (0x00000010u)
02099 #define EDMA3_CCRL_ER_E16_RESETVAL       (0x00000000u)
02100 
02101 #define EDMA3_CCRL_ER_E15_MASK           (0x00008000u)
02102 #define EDMA3_CCRL_ER_E15_SHIFT          (0x0000000Fu)
02103 #define EDMA3_CCRL_ER_E15_RESETVAL       (0x00000000u)
02104 
02105 #define EDMA3_CCRL_ER_E14_MASK           (0x00004000u)
02106 #define EDMA3_CCRL_ER_E14_SHIFT          (0x0000000Eu)
02107 #define EDMA3_CCRL_ER_E14_RESETVAL       (0x00000000u)
02108 
02109 #define EDMA3_CCRL_ER_E13_MASK           (0x00002000u)
02110 #define EDMA3_CCRL_ER_E13_SHIFT          (0x0000000Du)
02111 #define EDMA3_CCRL_ER_E13_RESETVAL       (0x00000000u)
02112 
02113 #define EDMA3_CCRL_ER_E12_MASK           (0x00001000u)
02114 #define EDMA3_CCRL_ER_E12_SHIFT          (0x0000000Cu)
02115 #define EDMA3_CCRL_ER_E12_RESETVAL       (0x00000000u)
02116 
02117 #define EDMA3_CCRL_ER_E11_MASK           (0x00000800u)
02118 #define EDMA3_CCRL_ER_E11_SHIFT          (0x0000000Bu)
02119 #define EDMA3_CCRL_ER_E11_RESETVAL       (0x00000000u)
02120 
02121 #define EDMA3_CCRL_ER_E10_MASK           (0x00000400u)
02122 #define EDMA3_CCRL_ER_E10_SHIFT          (0x0000000Au)
02123 #define EDMA3_CCRL_ER_E10_RESETVAL       (0x00000000u)
02124 
02125 #define EDMA3_CCRL_ER_E9_MASK            (0x00000200u)
02126 #define EDMA3_CCRL_ER_E9_SHIFT           (0x00000009u)
02127 #define EDMA3_CCRL_ER_E9_RESETVAL        (0x00000000u)
02128 
02129 #define EDMA3_CCRL_ER_E8_MASK            (0x00000100u)
02130 #define EDMA3_CCRL_ER_E8_SHIFT           (0x00000008u)
02131 #define EDMA3_CCRL_ER_E8_RESETVAL        (0x00000000u)
02132 
02133 #define EDMA3_CCRL_ER_E7_MASK            (0x00000080u)
02134 #define EDMA3_CCRL_ER_E7_SHIFT           (0x00000007u)
02135 #define EDMA3_CCRL_ER_E7_RESETVAL        (0x00000000u)
02136 
02137 #define EDMA3_CCRL_ER_E6_MASK            (0x00000040u)
02138 #define EDMA3_CCRL_ER_E6_SHIFT           (0x00000006u)
02139 #define EDMA3_CCRL_ER_E6_RESETVAL        (0x00000000u)
02140 
02141 #define EDMA3_CCRL_ER_E5_MASK            (0x00000020u)
02142 #define EDMA3_CCRL_ER_E5_SHIFT           (0x00000005u)
02143 #define EDMA3_CCRL_ER_E5_RESETVAL        (0x00000000u)
02144 
02145 #define EDMA3_CCRL_ER_E4_MASK            (0x00000010u)
02146 #define EDMA3_CCRL_ER_E4_SHIFT           (0x00000004u)
02147 #define EDMA3_CCRL_ER_E4_RESETVAL        (0x00000000u)
02148 
02149 #define EDMA3_CCRL_ER_E3_MASK            (0x00000008u)
02150 #define EDMA3_CCRL_ER_E3_SHIFT           (0x00000003u)
02151 #define EDMA3_CCRL_ER_E3_RESETVAL        (0x00000000u)
02152 
02153 #define EDMA3_CCRL_ER_E2_MASK            (0x00000004u)
02154 #define EDMA3_CCRL_ER_E2_SHIFT           (0x00000002u)
02155 #define EDMA3_CCRL_ER_E2_RESETVAL        (0x00000000u)
02156 
02157 #define EDMA3_CCRL_ER_E1_MASK            (0x00000002u)
02158 #define EDMA3_CCRL_ER_E1_SHIFT           (0x00000001u)
02159 #define EDMA3_CCRL_ER_E1_RESETVAL        (0x00000000u)
02160 
02161 #define EDMA3_CCRL_ER_E0_MASK            (0x00000001u)
02162 #define EDMA3_CCRL_ER_E0_SHIFT           (0x00000000u)
02163 #define EDMA3_CCRL_ER_E0_RESETVAL        (0x00000000u)
02164 
02165 #define EDMA3_CCRL_ER_RESETVAL           (0x00000000u)
02166 
02167 /* ERH */
02168 
02169 #define EDMA3_CCRL_ERH_E63_MASK          (0x80000000u)
02170 #define EDMA3_CCRL_ERH_E63_SHIFT         (0x0000001Fu)
02171 #define EDMA3_CCRL_ERH_E63_RESETVAL      (0x00000000u)
02172 
02173 #define EDMA3_CCRL_ERH_E62_MASK          (0x40000000u)
02174 #define EDMA3_CCRL_ERH_E62_SHIFT         (0x0000001Eu)
02175 #define EDMA3_CCRL_ERH_E62_RESETVAL      (0x00000000u)
02176 
02177 #define EDMA3_CCRL_ERH_E61_MASK          (0x20000000u)
02178 #define EDMA3_CCRL_ERH_E61_SHIFT         (0x0000001Du)
02179 #define EDMA3_CCRL_ERH_E61_RESETVAL      (0x00000000u)
02180 
02181 #define EDMA3_CCRL_ERH_E60_MASK          (0x10000000u)
02182 #define EDMA3_CCRL_ERH_E60_SHIFT         (0x0000001Cu)
02183 #define EDMA3_CCRL_ERH_E60_RESETVAL      (0x00000000u)
02184 
02185 #define EDMA3_CCRL_ERH_E59_MASK          (0x08000000u)
02186 #define EDMA3_CCRL_ERH_E59_SHIFT         (0x0000001Bu)
02187 #define EDMA3_CCRL_ERH_E59_RESETVAL      (0x00000000u)
02188 
02189 #define EDMA3_CCRL_ERH_E58_MASK          (0x04000000u)
02190 #define EDMA3_CCRL_ERH_E58_SHIFT         (0x0000001Au)
02191 #define EDMA3_CCRL_ERH_E58_RESETVAL      (0x00000000u)
02192 
02193 #define EDMA3_CCRL_ERH_E57_MASK          (0x02000000u)
02194 #define EDMA3_CCRL_ERH_E57_SHIFT         (0x00000019u)
02195 #define EDMA3_CCRL_ERH_E57_RESETVAL      (0x00000000u)
02196 
02197 #define EDMA3_CCRL_ERH_E56_MASK          (0x01000000u)
02198 #define EDMA3_CCRL_ERH_E56_SHIFT         (0x00000018u)
02199 #define EDMA3_CCRL_ERH_E56_RESETVAL      (0x00000000u)
02200 
02201 #define EDMA3_CCRL_ERH_E55_MASK          (0x00800000u)
02202 #define EDMA3_CCRL_ERH_E55_SHIFT         (0x00000017u)
02203 #define EDMA3_CCRL_ERH_E55_RESETVAL      (0x00000000u)
02204 
02205 #define EDMA3_CCRL_ERH_E54_MASK          (0x00400000u)
02206 #define EDMA3_CCRL_ERH_E54_SHIFT         (0x00000016u)
02207 #define EDMA3_CCRL_ERH_E54_RESETVAL      (0x00000000u)
02208 
02209 #define EDMA3_CCRL_ERH_E53_MASK          (0x00200000u)
02210 #define EDMA3_CCRL_ERH_E53_SHIFT         (0x00000015u)
02211 #define EDMA3_CCRL_ERH_E53_RESETVAL      (0x00000000u)
02212 
02213 #define EDMA3_CCRL_ERH_E52_MASK          (0x00100000u)
02214 #define EDMA3_CCRL_ERH_E52_SHIFT         (0x00000014u)
02215 #define EDMA3_CCRL_ERH_E52_RESETVAL      (0x00000000u)
02216 
02217 #define EDMA3_CCRL_ERH_E51_MASK          (0x00080000u)
02218 #define EDMA3_CCRL_ERH_E51_SHIFT         (0x00000013u)
02219 #define EDMA3_CCRL_ERH_E51_RESETVAL      (0x00000000u)
02220 
02221 #define EDMA3_CCRL_ERH_E50_MASK          (0x00040000u)
02222 #define EDMA3_CCRL_ERH_E50_SHIFT         (0x00000012u)
02223 #define EDMA3_CCRL_ERH_E50_RESETVAL      (0x00000000u)
02224 
02225 #define EDMA3_CCRL_ERH_E49_MASK          (0x00020000u)
02226 #define EDMA3_CCRL_ERH_E49_SHIFT         (0x00000011u)
02227 #define EDMA3_CCRL_ERH_E49_RESETVAL      (0x00000000u)
02228 
02229 #define EDMA3_CCRL_ERH_E48_MASK          (0x00010000u)
02230 #define EDMA3_CCRL_ERH_E48_SHIFT         (0x00000010u)
02231 #define EDMA3_CCRL_ERH_E48_RESETVAL      (0x00000000u)
02232 
02233 #define EDMA3_CCRL_ERH_E47_MASK          (0x00008000u)
02234 #define EDMA3_CCRL_ERH_E47_SHIFT         (0x0000000Fu)
02235 #define EDMA3_CCRL_ERH_E47_RESETVAL      (0x00000000u)
02236 
02237 #define EDMA3_CCRL_ERH_E46_MASK          (0x00004000u)
02238 #define EDMA3_CCRL_ERH_E46_SHIFT         (0x0000000Eu)
02239 #define EDMA3_CCRL_ERH_E46_RESETVAL      (0x00000000u)
02240 
02241 #define EDMA3_CCRL_ERH_E45_MASK          (0x00002000u)
02242 #define EDMA3_CCRL_ERH_E45_SHIFT         (0x0000000Du)
02243 #define EDMA3_CCRL_ERH_E45_RESETVAL      (0x00000000u)
02244 
02245 #define EDMA3_CCRL_ERH_E44_MASK          (0x00001000u)
02246 #define EDMA3_CCRL_ERH_E44_SHIFT         (0x0000000Cu)
02247 #define EDMA3_CCRL_ERH_E44_RESETVAL      (0x00000000u)
02248 
02249 #define EDMA3_CCRL_ERH_E43_MASK          (0x00000800u)
02250 #define EDMA3_CCRL_ERH_E43_SHIFT         (0x0000000Bu)
02251 #define EDMA3_CCRL_ERH_E43_RESETVAL      (0x00000000u)
02252 
02253 #define EDMA3_CCRL_ERH_E42_MASK          (0x00000400u)
02254 #define EDMA3_CCRL_ERH_E42_SHIFT         (0x0000000Au)
02255 #define EDMA3_CCRL_ERH_E42_RESETVAL      (0x00000000u)
02256 
02257 #define EDMA3_CCRL_ERH_E41_MASK          (0x00000200u)
02258 #define EDMA3_CCRL_ERH_E41_SHIFT         (0x00000009u)
02259 #define EDMA3_CCRL_ERH_E41_RESETVAL      (0x00000000u)
02260 
02261 #define EDMA3_CCRL_ERH_E40_MASK          (0x00000100u)
02262 #define EDMA3_CCRL_ERH_E40_SHIFT         (0x00000008u)
02263 #define EDMA3_CCRL_ERH_E40_RESETVAL      (0x00000000u)
02264 
02265 #define EDMA3_CCRL_ERH_E39_MASK          (0x00000080u)
02266 #define EDMA3_CCRL_ERH_E39_SHIFT         (0x00000007u)
02267 #define EDMA3_CCRL_ERH_E39_RESETVAL      (0x00000000u)
02268 
02269 #define EDMA3_CCRL_ERH_E38_MASK          (0x00000040u)
02270 #define EDMA3_CCRL_ERH_E38_SHIFT         (0x00000006u)
02271 #define EDMA3_CCRL_ERH_E38_RESETVAL      (0x00000000u)
02272 
02273 #define EDMA3_CCRL_ERH_E37_MASK          (0x00000020u)
02274 #define EDMA3_CCRL_ERH_E37_SHIFT         (0x00000005u)
02275 #define EDMA3_CCRL_ERH_E37_RESETVAL      (0x00000000u)
02276 
02277 #define EDMA3_CCRL_ERH_E36_MASK          (0x00000010u)
02278 #define EDMA3_CCRL_ERH_E36_SHIFT         (0x00000004u)
02279 #define EDMA3_CCRL_ERH_E36_RESETVAL      (0x00000000u)
02280 
02281 #define EDMA3_CCRL_ERH_E35_MASK          (0x00000008u)
02282 #define EDMA3_CCRL_ERH_E35_SHIFT         (0x00000003u)
02283 #define EDMA3_CCRL_ERH_E35_RESETVAL      (0x00000000u)
02284 
02285 #define EDMA3_CCRL_ERH_E34_MASK          (0x00000004u)
02286 #define EDMA3_CCRL_ERH_E34_SHIFT         (0x00000002u)
02287 #define EDMA3_CCRL_ERH_E34_RESETVAL      (0x00000000u)
02288 
02289 #define EDMA3_CCRL_ERH_E33_MASK          (0x00000002u)
02290 #define EDMA3_CCRL_ERH_E33_SHIFT         (0x00000001u)
02291 #define EDMA3_CCRL_ERH_E33_RESETVAL      (0x00000000u)
02292 
02293 #define EDMA3_CCRL_ERH_E32_MASK          (0x00000001u)
02294 #define EDMA3_CCRL_ERH_E32_SHIFT         (0x00000000u)
02295 #define EDMA3_CCRL_ERH_E32_RESETVAL      (0x00000000u)
02296 
02297 #define EDMA3_CCRL_ERH_RESETVAL          (0x00000000u)
02298 
02299 /* ECR */
02300 
02301 #define EDMA3_CCRL_ECR_E31_MASK          (0x80000000u)
02302 #define EDMA3_CCRL_ECR_E31_SHIFT         (0x0000001Fu)
02303 #define EDMA3_CCRL_ECR_E31_RESETVAL      (0x00000000u)
02304 
02305 /*----E31 Tokens----*/
02306 #define EDMA3_CCRL_ECR_E31_CLEAR         (0x00000001u)
02307 
02308 #define EDMA3_CCRL_ECR_E30_MASK          (0x40000000u)
02309 #define EDMA3_CCRL_ECR_E30_SHIFT         (0x0000001Eu)
02310 #define EDMA3_CCRL_ECR_E30_RESETVAL      (0x00000000u)
02311 
02312 /*----E30 Tokens----*/
02313 #define EDMA3_CCRL_ECR_E30_CLEAR         (0x00000001u)
02314 
02315 #define EDMA3_CCRL_ECR_E29_MASK          (0x20000000u)
02316 #define EDMA3_CCRL_ECR_E29_SHIFT         (0x0000001Du)
02317 #define EDMA3_CCRL_ECR_E29_RESETVAL      (0x00000000u)
02318 
02319 /*----E29 Tokens----*/
02320 #define EDMA3_CCRL_ECR_E29_CLEAR         (0x00000001u)
02321 
02322 #define EDMA3_CCRL_ECR_E28_MASK          (0x10000000u)
02323 #define EDMA3_CCRL_ECR_E28_SHIFT         (0x0000001Cu)
02324 #define EDMA3_CCRL_ECR_E28_RESETVAL      (0x00000000u)
02325 
02326 /*----E28 Tokens----*/
02327 #define EDMA3_CCRL_ECR_E28_CLEAR         (0x00000001u)
02328 
02329 #define EDMA3_CCRL_ECR_E27_MASK          (0x08000000u)
02330 #define EDMA3_CCRL_ECR_E27_SHIFT         (0x0000001Bu)
02331 #define EDMA3_CCRL_ECR_E27_RESETVAL      (0x00000000u)
02332 
02333 /*----E27 Tokens----*/
02334 #define EDMA3_CCRL_ECR_E27_CLEAR         (0x00000001u)
02335 
02336 #define EDMA3_CCRL_ECR_E26_MASK          (0x04000000u)
02337 #define EDMA3_CCRL_ECR_E26_SHIFT         (0x0000001Au)
02338 #define EDMA3_CCRL_ECR_E26_RESETVAL      (0x00000000u)
02339 
02340 /*----E26 Tokens----*/
02341 #define EDMA3_CCRL_ECR_E26_CLEAR         (0x00000001u)
02342 
02343 #define EDMA3_CCRL_ECR_E25_MASK          (0x02000000u)
02344 #define EDMA3_CCRL_ECR_E25_SHIFT         (0x00000019u)
02345 #define EDMA3_CCRL_ECR_E25_RESETVAL      (0x00000000u)
02346 
02347 /*----E25 Tokens----*/
02348 #define EDMA3_CCRL_ECR_E25_CLEAR         (0x00000001u)
02349 
02350 #define EDMA3_CCRL_ECR_E24_MASK          (0x01000000u)
02351 #define EDMA3_CCRL_ECR_E24_SHIFT         (0x00000018u)
02352 #define EDMA3_CCRL_ECR_E24_RESETVAL      (0x00000000u)
02353 
02354 /*----E24 Tokens----*/
02355 #define EDMA3_CCRL_ECR_E24_CLEAR         (0x00000001u)
02356 
02357 #define EDMA3_CCRL_ECR_E23_MASK          (0x00800000u)
02358 #define EDMA3_CCRL_ECR_E23_SHIFT         (0x00000017u)
02359 #define EDMA3_CCRL_ECR_E23_RESETVAL      (0x00000000u)
02360 
02361 /*----E23 Tokens----*/
02362 #define EDMA3_CCRL_ECR_E23_CLEAR         (0x00000001u)
02363 
02364 #define EDMA3_CCRL_ECR_E22_MASK          (0x00400000u)
02365 #define EDMA3_CCRL_ECR_E22_SHIFT         (0x00000016u)
02366 #define EDMA3_CCRL_ECR_E22_RESETVAL      (0x00000000u)
02367 
02368 /*----E22 Tokens----*/
02369 #define EDMA3_CCRL_ECR_E22_CLEAR         (0x00000001u)
02370 
02371 #define EDMA3_CCRL_ECR_E21_MASK          (0x00200000u)
02372 #define EDMA3_CCRL_ECR_E21_SHIFT         (0x00000015u)
02373 #define EDMA3_CCRL_ECR_E21_RESETVAL      (0x00000000u)
02374 
02375 /*----E21 Tokens----*/
02376 #define EDMA3_CCRL_ECR_E21_CLEAR         (0x00000001u)
02377 
02378 #define EDMA3_CCRL_ECR_E20_MASK          (0x00100000u)
02379 #define EDMA3_CCRL_ECR_E20_SHIFT         (0x00000014u)
02380 #define EDMA3_CCRL_ECR_E20_RESETVAL      (0x00000000u)
02381 
02382 /*----E20 Tokens----*/
02383 #define EDMA3_CCRL_ECR_E20_CLEAR         (0x00000001u)
02384 
02385 #define EDMA3_CCRL_ECR_E19_MASK          (0x00080000u)
02386 #define EDMA3_CCRL_ECR_E19_SHIFT         (0x00000013u)
02387 #define EDMA3_CCRL_ECR_E19_RESETVAL      (0x00000000u)
02388 
02389 /*----E19 Tokens----*/
02390 #define EDMA3_CCRL_ECR_E19_CLEAR         (0x00000001u)
02391 
02392 #define EDMA3_CCRL_ECR_E18_MASK          (0x00040000u)
02393 #define EDMA3_CCRL_ECR_E18_SHIFT         (0x00000012u)
02394 #define EDMA3_CCRL_ECR_E18_RESETVAL      (0x00000000u)
02395 
02396 /*----E18 Tokens----*/
02397 #define EDMA3_CCRL_ECR_E18_CLEAR         (0x00000001u)
02398 
02399 #define EDMA3_CCRL_ECR_E17_MASK          (0x00020000u)
02400 #define EDMA3_CCRL_ECR_E17_SHIFT         (0x00000011u)
02401 #define EDMA3_CCRL_ECR_E17_RESETVAL      (0x00000000u)
02402 
02403 /*----E17 Tokens----*/
02404 #define EDMA3_CCRL_ECR_E17_CLEAR         (0x00000001u)
02405 
02406 #define EDMA3_CCRL_ECR_E16_MASK          (0x00010000u)
02407 #define EDMA3_CCRL_ECR_E16_SHIFT         (0x00000010u)
02408 #define EDMA3_CCRL_ECR_E16_RESETVAL      (0x00000000u)
02409 
02410 /*----E16 Tokens----*/
02411 #define EDMA3_CCRL_ECR_E16_CLEAR         (0x00000001u)
02412 
02413 #define EDMA3_CCRL_ECR_E15_MASK          (0x00008000u)
02414 #define EDMA3_CCRL_ECR_E15_SHIFT         (0x0000000Fu)
02415 #define EDMA3_CCRL_ECR_E15_RESETVAL      (0x00000000u)
02416 
02417 /*----E15 Tokens----*/
02418 #define EDMA3_CCRL_ECR_E15_CLEAR         (0x00000001u)
02419 
02420 #define EDMA3_CCRL_ECR_E14_MASK          (0x00004000u)
02421 #define EDMA3_CCRL_ECR_E14_SHIFT         (0x0000000Eu)
02422 #define EDMA3_CCRL_ECR_E14_RESETVAL      (0x00000000u)
02423 
02424 /*----E14 Tokens----*/
02425 #define EDMA3_CCRL_ECR_E14_CLEAR         (0x00000001u)
02426 
02427 #define EDMA3_CCRL_ECR_E13_MASK          (0x00002000u)
02428 #define EDMA3_CCRL_ECR_E13_SHIFT         (0x0000000Du)
02429 #define EDMA3_CCRL_ECR_E13_RESETVAL      (0x00000000u)
02430 
02431 /*----E13 Tokens----*/
02432 #define EDMA3_CCRL_ECR_E13_CLEAR         (0x00000001u)
02433 
02434 #define EDMA3_CCRL_ECR_E12_MASK          (0x00001000u)
02435 #define EDMA3_CCRL_ECR_E12_SHIFT         (0x0000000Cu)
02436 #define EDMA3_CCRL_ECR_E12_RESETVAL      (0x00000000u)
02437 
02438 /*----E12 Tokens----*/
02439 #define EDMA3_CCRL_ECR_E12_CLEAR         (0x00000001u)
02440 
02441 #define EDMA3_CCRL_ECR_E11_MASK          (0x00000800u)
02442 #define EDMA3_CCRL_ECR_E11_SHIFT         (0x0000000Bu)
02443 #define EDMA3_CCRL_ECR_E11_RESETVAL      (0x00000000u)
02444 
02445 /*----E11 Tokens----*/
02446 #define EDMA3_CCRL_ECR_E11_CLEAR         (0x00000001u)
02447 
02448 #define EDMA3_CCRL_ECR_E10_MASK          (0x00000400u)
02449 #define EDMA3_CCRL_ECR_E10_SHIFT         (0x0000000Au)
02450 #define EDMA3_CCRL_ECR_E10_RESETVAL      (0x00000000u)
02451 
02452 /*----E10 Tokens----*/
02453 #define EDMA3_CCRL_ECR_E10_CLEAR         (0x00000001u)
02454 
02455 #define EDMA3_CCRL_ECR_E9_MASK           (0x00000200u)
02456 #define EDMA3_CCRL_ECR_E9_SHIFT          (0x00000009u)
02457 #define EDMA3_CCRL_ECR_E9_RESETVAL       (0x00000000u)
02458 
02459 /*----E9 Tokens----*/
02460 #define EDMA3_CCRL_ECR_E9_CLEAR          (0x00000001u)
02461 
02462 #define EDMA3_CCRL_ECR_E8_MASK           (0x00000100u)
02463 #define EDMA3_CCRL_ECR_E8_SHIFT          (0x00000008u)
02464 #define EDMA3_CCRL_ECR_E8_RESETVAL       (0x00000000u)
02465 
02466 /*----E8 Tokens----*/
02467 #define EDMA3_CCRL_ECR_E8_CLEAR          (0x00000001u)
02468 
02469 #define EDMA3_CCRL_ECR_E7_MASK           (0x00000080u)
02470 #define EDMA3_CCRL_ECR_E7_SHIFT          (0x00000007u)
02471 #define EDMA3_CCRL_ECR_E7_RESETVAL       (0x00000000u)
02472 
02473 /*----E7 Tokens----*/
02474 #define EDMA3_CCRL_ECR_E7_CLEAR          (0x00000001u)
02475 
02476 #define EDMA3_CCRL_ECR_E6_MASK           (0x00000040u)
02477 #define EDMA3_CCRL_ECR_E6_SHIFT          (0x00000006u)
02478 #define EDMA3_CCRL_ECR_E6_RESETVAL       (0x00000000u)
02479 
02480 /*----E6 Tokens----*/
02481 #define EDMA3_CCRL_ECR_E6_CLEAR          (0x00000001u)
02482 
02483 #define EDMA3_CCRL_ECR_E5_MASK           (0x00000020u)
02484 #define EDMA3_CCRL_ECR_E5_SHIFT          (0x00000005u)
02485 #define EDMA3_CCRL_ECR_E5_RESETVAL       (0x00000000u)
02486 
02487 /*----E5 Tokens----*/
02488 #define EDMA3_CCRL_ECR_E5_CLEAR          (0x00000001u)
02489 
02490 #define EDMA3_CCRL_ECR_E4_MASK           (0x00000010u)
02491 #define EDMA3_CCRL_ECR_E4_SHIFT          (0x00000004u)
02492 #define EDMA3_CCRL_ECR_E4_RESETVAL       (0x00000000u)
02493 
02494 /*----E4 Tokens----*/
02495 #define EDMA3_CCRL_ECR_E4_CLEAR          (0x00000001u)
02496 
02497 #define EDMA3_CCRL_ECR_E3_MASK           (0x00000008u)
02498 #define EDMA3_CCRL_ECR_E3_SHIFT          (0x00000003u)
02499 #define EDMA3_CCRL_ECR_E3_RESETVAL       (0x00000000u)
02500 
02501 /*----E3 Tokens----*/
02502 #define EDMA3_CCRL_ECR_E3_CLEAR          (0x00000001u)
02503 
02504 #define EDMA3_CCRL_ECR_E2_MASK           (0x00000004u)
02505 #define EDMA3_CCRL_ECR_E2_SHIFT          (0x00000002u)
02506 #define EDMA3_CCRL_ECR_E2_RESETVAL       (0x00000000u)
02507 
02508 /*----E2 Tokens----*/
02509 #define EDMA3_CCRL_ECR_E2_CLEAR          (0x00000001u)
02510 
02511 #define EDMA3_CCRL_ECR_E1_MASK           (0x00000002u)
02512 #define EDMA3_CCRL_ECR_E1_SHIFT          (0x00000001u)
02513 #define EDMA3_CCRL_ECR_E1_RESETVAL       (0x00000000u)
02514 
02515 /*----E1 Tokens----*/
02516 #define EDMA3_CCRL_ECR_E1_CLEAR          (0x00000001u)
02517 
02518 #define EDMA3_CCRL_ECR_E0_MASK           (0x00000001u)
02519 #define EDMA3_CCRL_ECR_E0_SHIFT          (0x00000000u)
02520 #define EDMA3_CCRL_ECR_E0_RESETVAL       (0x00000000u)
02521 
02522 /*----E0 Tokens----*/
02523 #define EDMA3_CCRL_ECR_E0_CLEAR          (0x00000001u)
02524 
02525 #define EDMA3_CCRL_ECR_RESETVAL          (0x00000000u)
02526 
02527 /* ECRH */
02528 
02529 #define EDMA3_CCRL_ECRH_E63_MASK         (0x80000000u)
02530 #define EDMA3_CCRL_ECRH_E63_SHIFT        (0x0000001Fu)
02531 #define EDMA3_CCRL_ECRH_E63_RESETVAL     (0x00000000u)
02532 
02533 /*----E63 Tokens----*/
02534 #define EDMA3_CCRL_ECRH_E63_CLEAR        (0x00000001u)
02535 
02536 #define EDMA3_CCRL_ECRH_E62_MASK         (0x40000000u)
02537 #define EDMA3_CCRL_ECRH_E62_SHIFT        (0x0000001Eu)
02538 #define EDMA3_CCRL_ECRH_E62_RESETVAL     (0x00000000u)
02539 
02540 /*----E62 Tokens----*/
02541 #define EDMA3_CCRL_ECRH_E62_CLEAR        (0x00000001u)
02542 
02543 #define EDMA3_CCRL_ECRH_E61_MASK         (0x20000000u)
02544 #define EDMA3_CCRL_ECRH_E61_SHIFT        (0x0000001Du)
02545 #define EDMA3_CCRL_ECRH_E61_RESETVAL     (0x00000000u)
02546 
02547 /*----E61 Tokens----*/
02548 #define EDMA3_CCRL_ECRH_E61_CLEAR        (0x00000001u)
02549 
02550 #define EDMA3_CCRL_ECRH_E60_MASK         (0x10000000u)
02551 #define EDMA3_CCRL_ECRH_E60_SHIFT        (0x0000001Cu)
02552 #define EDMA3_CCRL_ECRH_E60_RESETVAL     (0x00000000u)
02553 
02554 /*----E60 Tokens----*/
02555 #define EDMA3_CCRL_ECRH_E60_CLEAR        (0x00000001u)
02556 
02557 #define EDMA3_CCRL_ECRH_E59_MASK         (0x08000000u)
02558 #define EDMA3_CCRL_ECRH_E59_SHIFT        (0x0000001Bu)
02559 #define EDMA3_CCRL_ECRH_E59_RESETVAL     (0x00000000u)
02560 
02561 /*----E59 Tokens----*/
02562 #define EDMA3_CCRL_ECRH_E59_CLEAR        (0x00000001u)
02563 
02564 #define EDMA3_CCRL_ECRH_E58_MASK         (0x04000000u)
02565 #define EDMA3_CCRL_ECRH_E58_SHIFT        (0x0000001Au)
02566 #define EDMA3_CCRL_ECRH_E58_RESETVAL     (0x00000000u)
02567 
02568 /*----E58 Tokens----*/
02569 #define EDMA3_CCRL_ECRH_E58_CLEAR        (0x00000001u)
02570 
02571 #define EDMA3_CCRL_ECRH_E57_MASK         (0x02000000u)
02572 #define EDMA3_CCRL_ECRH_E57_SHIFT        (0x00000019u)
02573 #define EDMA3_CCRL_ECRH_E57_RESETVAL     (0x00000000u)
02574 
02575 /*----E57 Tokens----*/
02576 #define EDMA3_CCRL_ECRH_E57_CLEAR        (0x00000001u)
02577 
02578 #define EDMA3_CCRL_ECRH_E56_MASK         (0x01000000u)
02579 #define EDMA3_CCRL_ECRH_E56_SHIFT        (0x00000018u)
02580 #define EDMA3_CCRL_ECRH_E56_RESETVAL     (0x00000000u)
02581 
02582 /*----E56 Tokens----*/
02583 #define EDMA3_CCRL_ECRH_E56_CLEAR        (0x00000001u)
02584 
02585 #define EDMA3_CCRL_ECRH_E55_MASK         (0x00800000u)
02586 #define EDMA3_CCRL_ECRH_E55_SHIFT        (0x00000017u)
02587 #define EDMA3_CCRL_ECRH_E55_RESETVAL     (0x00000000u)
02588 
02589 /*----E55 Tokens----*/
02590 #define EDMA3_CCRL_ECRH_E55_CLEAR        (0x00000001u)
02591 
02592 #define EDMA3_CCRL_ECRH_E54_MASK         (0x00400000u)
02593 #define EDMA3_CCRL_ECRH_E54_SHIFT        (0x00000016u)
02594 #define EDMA3_CCRL_ECRH_E54_RESETVAL     (0x00000000u)
02595 
02596 /*----E54 Tokens----*/
02597 #define EDMA3_CCRL_ECRH_E54_CLEAR        (0x00000001u)
02598 
02599 #define EDMA3_CCRL_ECRH_E53_MASK         (0x00200000u)
02600 #define EDMA3_CCRL_ECRH_E53_SHIFT        (0x00000015u)
02601 #define EDMA3_CCRL_ECRH_E53_RESETVAL     (0x00000000u)
02602 
02603 /*----E53 Tokens----*/
02604 #define EDMA3_CCRL_ECRH_E53_CLEAR        (0x00000001u)
02605 
02606 #define EDMA3_CCRL_ECRH_E52_MASK         (0x00100000u)
02607 #define EDMA3_CCRL_ECRH_E52_SHIFT        (0x00000014u)
02608 #define EDMA3_CCRL_ECRH_E52_RESETVAL     (0x00000000u)
02609 
02610 /*----E52 Tokens----*/
02611 #define EDMA3_CCRL_ECRH_E52_CLEAR        (0x00000001u)
02612 
02613 #define EDMA3_CCRL_ECRH_E51_MASK         (0x00080000u)
02614 #define EDMA3_CCRL_ECRH_E51_SHIFT        (0x00000013u)
02615 #define EDMA3_CCRL_ECRH_E51_RESETVAL     (0x00000000u)
02616 
02617 /*----E51 Tokens----*/
02618 #define EDMA3_CCRL_ECRH_E51_CLEAR        (0x00000001u)
02619 
02620 #define EDMA3_CCRL_ECRH_E50_MASK         (0x00040000u)
02621 #define EDMA3_CCRL_ECRH_E50_SHIFT        (0x00000012u)
02622 #define EDMA3_CCRL_ECRH_E50_RESETVAL     (0x00000000u)
02623 
02624 /*----E50 Tokens----*/
02625 #define EDMA3_CCRL_ECRH_E50_CLEAR        (0x00000001u)
02626 
02627 #define EDMA3_CCRL_ECRH_E49_MASK         (0x00020000u)
02628 #define EDMA3_CCRL_ECRH_E49_SHIFT        (0x00000011u)
02629 #define EDMA3_CCRL_ECRH_E49_RESETVAL     (0x00000000u)
02630 
02631 /*----E49 Tokens----*/
02632 #define EDMA3_CCRL_ECRH_E49_CLEAR        (0x00000001u)
02633 
02634 #define EDMA3_CCRL_ECRH_E48_MASK         (0x00010000u)
02635 #define EDMA3_CCRL_ECRH_E48_SHIFT        (0x00000010u)
02636 #define EDMA3_CCRL_ECRH_E48_RESETVAL     (0x00000000u)
02637 
02638 /*----E48 Tokens----*/
02639 #define EDMA3_CCRL_ECRH_E48_CLEAR        (0x00000001u)
02640 
02641 #define EDMA3_CCRL_ECRH_E47_MASK         (0x00008000u)
02642 #define EDMA3_CCRL_ECRH_E47_SHIFT        (0x0000000Fu)
02643 #define EDMA3_CCRL_ECRH_E47_RESETVAL     (0x00000000u)
02644 
02645 /*----E47 Tokens----*/
02646 #define EDMA3_CCRL_ECRH_E47_CLEAR        (0x00000001u)
02647 
02648 #define EDMA3_CCRL_ECRH_E46_MASK         (0x00004000u)
02649 #define EDMA3_CCRL_ECRH_E46_SHIFT        (0x0000000Eu)
02650 #define EDMA3_CCRL_ECRH_E46_RESETVAL     (0x00000000u)
02651 
02652 /*----E46 Tokens----*/
02653 #define EDMA3_CCRL_ECRH_E46_CLEAR        (0x00000001u)
02654 
02655 #define EDMA3_CCRL_ECRH_E45_MASK         (0x00002000u)
02656 #define EDMA3_CCRL_ECRH_E45_SHIFT        (0x0000000Du)
02657 #define EDMA3_CCRL_ECRH_E45_RESETVAL     (0x00000000u)
02658 
02659 /*----E45 Tokens----*/
02660 #define EDMA3_CCRL_ECRH_E45_CLEAR        (0x00000001u)
02661 
02662 #define EDMA3_CCRL_ECRH_E44_MASK         (0x00001000u)
02663 #define EDMA3_CCRL_ECRH_E44_SHIFT        (0x0000000Cu)
02664 #define EDMA3_CCRL_ECRH_E44_RESETVAL     (0x00000000u)
02665 
02666 /*----E44 Tokens----*/
02667 #define EDMA3_CCRL_ECRH_E44_CLEAR        (0x00000001u)
02668 
02669 #define EDMA3_CCRL_ECRH_E43_MASK         (0x00000800u)
02670 #define EDMA3_CCRL_ECRH_E43_SHIFT        (0x0000000Bu)
02671 #define EDMA3_CCRL_ECRH_E43_RESETVAL     (0x00000000u)
02672 
02673 /*----E43 Tokens----*/
02674 #define EDMA3_CCRL_ECRH_E43_CLEAR        (0x00000001u)
02675 
02676 #define EDMA3_CCRL_ECRH_E42_MASK         (0x00000400u)
02677 #define EDMA3_CCRL_ECRH_E42_SHIFT        (0x0000000Au)
02678 #define EDMA3_CCRL_ECRH_E42_RESETVAL     (0x00000000u)
02679 
02680 /*----E42 Tokens----*/
02681 #define EDMA3_CCRL_ECRH_E42_CLEAR        (0x00000001u)
02682 
02683 #define EDMA3_CCRL_ECRH_E41_MASK         (0x00000200u)
02684 #define EDMA3_CCRL_ECRH_E41_SHIFT        (0x00000009u)
02685 #define EDMA3_CCRL_ECRH_E41_RESETVAL     (0x00000000u)
02686 
02687 /*----E41 Tokens----*/
02688 #define EDMA3_CCRL_ECRH_E41_CLEAR        (0x00000001u)
02689 
02690 #define EDMA3_CCRL_ECRH_E40_MASK         (0x00000100u)
02691 #define EDMA3_CCRL_ECRH_E40_SHIFT        (0x00000008u)
02692 #define EDMA3_CCRL_ECRH_E40_RESETVAL     (0x00000000u)
02693 
02694 /*----E40 Tokens----*/
02695 #define EDMA3_CCRL_ECRH_E40_CLEAR        (0x00000001u)
02696 
02697 #define EDMA3_CCRL_ECRH_E39_MASK         (0x00000080u)
02698 #define EDMA3_CCRL_ECRH_E39_SHIFT        (0x00000007u)
02699 #define EDMA3_CCRL_ECRH_E39_RESETVAL     (0x00000000u)
02700 
02701 /*----E39 Tokens----*/
02702 #define EDMA3_CCRL_ECRH_E39_CLEAR        (0x00000001u)
02703 
02704 #define EDMA3_CCRL_ECRH_E38_MASK         (0x00000040u)
02705 #define EDMA3_CCRL_ECRH_E38_SHIFT        (0x00000006u)
02706 #define EDMA3_CCRL_ECRH_E38_RESETVAL     (0x00000000u)
02707 
02708 /*----E38 Tokens----*/
02709 #define EDMA3_CCRL_ECRH_E38_CLEAR        (0x00000001u)
02710 
02711 #define EDMA3_CCRL_ECRH_E37_MASK         (0x00000020u)
02712 #define EDMA3_CCRL_ECRH_E37_SHIFT        (0x00000005u)
02713 #define EDMA3_CCRL_ECRH_E37_RESETVAL     (0x00000000u)
02714 
02715 /*----E37 Tokens----*/
02716 #define EDMA3_CCRL_ECRH_E37_CLEAR        (0x00000001u)
02717 
02718 #define EDMA3_CCRL_ECRH_E36_MASK         (0x00000010u)
02719 #define EDMA3_CCRL_ECRH_E36_SHIFT        (0x00000004u)
02720 #define EDMA3_CCRL_ECRH_E36_RESETVAL     (0x00000000u)
02721 
02722 /*----E36 Tokens----*/
02723 #define EDMA3_CCRL_ECRH_E36_CLEAR        (0x00000001u)
02724 
02725 #define EDMA3_CCRL_ECRH_E35_MASK         (0x00000008u)
02726 #define EDMA3_CCRL_ECRH_E35_SHIFT        (0x00000003u)
02727 #define EDMA3_CCRL_ECRH_E35_RESETVAL     (0x00000000u)
02728 
02729 /*----E35 Tokens----*/
02730 #define EDMA3_CCRL_ECRH_E35_CLEAR        (0x00000001u)
02731 
02732 #define EDMA3_CCRL_ECRH_E34_MASK         (0x00000004u)
02733 #define EDMA3_CCRL_ECRH_E34_SHIFT        (0x00000002u)
02734 #define EDMA3_CCRL_ECRH_E34_RESETVAL     (0x00000000u)
02735 
02736 /*----E34 Tokens----*/
02737 #define EDMA3_CCRL_ECRH_E34_CLEAR        (0x00000001u)
02738 
02739 #define EDMA3_CCRL_ECRH_E33_MASK         (0x00000002u)
02740 #define EDMA3_CCRL_ECRH_E33_SHIFT        (0x00000001u)
02741 #define EDMA3_CCRL_ECRH_E33_RESETVAL     (0x00000000u)
02742 
02743 /*----E33 Tokens----*/
02744 #define EDMA3_CCRL_ECRH_E33_CLEAR        (0x00000001u)
02745 
02746 #define EDMA3_CCRL_ECRH_E32_MASK         (0x00000001u)
02747 #define EDMA3_CCRL_ECRH_E32_SHIFT        (0x00000000u)
02748 #define EDMA3_CCRL_ECRH_E32_RESETVAL     (0x00000000u)
02749 
02750 /*----E32 Tokens----*/
02751 #define EDMA3_CCRL_ECRH_E32_CLEAR        (0x00000001u)
02752 
02753 #define EDMA3_CCRL_ECRH_RESETVAL         (0x00000000u)
02754 
02755 /* ESR */
02756 
02757 #define EDMA3_CCRL_ESR_E31_MASK          (0x80000000u)
02758 #define EDMA3_CCRL_ESR_E31_SHIFT         (0x0000001Fu)
02759 #define EDMA3_CCRL_ESR_E31_RESETVAL      (0x00000000u)
02760 
02761 /*----E31 Tokens----*/
02762 #define EDMA3_CCRL_ESR_E31_SET           (0x00000001u)
02763 
02764 #define EDMA3_CCRL_ESR_E30_MASK          (0x40000000u)
02765 #define EDMA3_CCRL_ESR_E30_SHIFT         (0x0000001Eu)
02766 #define EDMA3_CCRL_ESR_E30_RESETVAL      (0x00000000u)
02767 
02768 /*----E30 Tokens----*/
02769 #define EDMA3_CCRL_ESR_E30_SET           (0x00000001u)
02770 
02771 #define EDMA3_CCRL_ESR_E29_MASK          (0x20000000u)
02772 #define EDMA3_CCRL_ESR_E29_SHIFT         (0x0000001Du)
02773 #define EDMA3_CCRL_ESR_E29_RESETVAL      (0x00000000u)
02774 
02775 /*----E29 Tokens----*/
02776 #define EDMA3_CCRL_ESR_E29_SET           (0x00000001u)
02777 
02778 #define EDMA3_CCRL_ESR_E28_MASK          (0x10000000u)
02779 #define EDMA3_CCRL_ESR_E28_SHIFT         (0x0000001Cu)
02780 #define EDMA3_CCRL_ESR_E28_RESETVAL      (0x00000000u)
02781 
02782 /*----E28 Tokens----*/
02783 #define EDMA3_CCRL_ESR_E28_SET           (0x00000001u)
02784 
02785 #define EDMA3_CCRL_ESR_E27_MASK          (0x08000000u)
02786 #define EDMA3_CCRL_ESR_E27_SHIFT         (0x0000001Bu)
02787 #define EDMA3_CCRL_ESR_E27_RESETVAL      (0x00000000u)
02788 
02789 /*----E27 Tokens----*/
02790 #define EDMA3_CCRL_ESR_E27_SET           (0x00000001u)
02791 
02792 #define EDMA3_CCRL_ESR_E26_MASK          (0x04000000u)
02793 #define EDMA3_CCRL_ESR_E26_SHIFT         (0x0000001Au)
02794 #define EDMA3_CCRL_ESR_E26_RESETVAL      (0x00000000u)
02795 
02796 /*----E26 Tokens----*/
02797 #define EDMA3_CCRL_ESR_E26_SET           (0x00000001u)
02798 
02799 #define EDMA3_CCRL_ESR_E25_MASK          (0x02000000u)
02800 #define EDMA3_CCRL_ESR_E25_SHIFT         (0x00000019u)
02801 #define EDMA3_CCRL_ESR_E25_RESETVAL      (0x00000000u)
02802 
02803 /*----E25 Tokens----*/
02804 #define EDMA3_CCRL_ESR_E25_SET           (0x00000001u)
02805 
02806 #define EDMA3_CCRL_ESR_E24_MASK          (0x01000000u)
02807 #define EDMA3_CCRL_ESR_E24_SHIFT         (0x00000018u)
02808 #define EDMA3_CCRL_ESR_E24_RESETVAL      (0x00000000u)
02809 
02810 /*----E24 Tokens----*/
02811 #define EDMA3_CCRL_ESR_E24_SET           (0x00000001u)
02812 
02813 #define EDMA3_CCRL_ESR_E23_MASK          (0x00800000u)
02814 #define EDMA3_CCRL_ESR_E23_SHIFT         (0x00000017u)
02815 #define EDMA3_CCRL_ESR_E23_RESETVAL      (0x00000000u)
02816 
02817 /*----E23 Tokens----*/
02818 #define EDMA3_CCRL_ESR_E23_SET           (0x00000001u)
02819 
02820 #define EDMA3_CCRL_ESR_E22_MASK          (0x00400000u)
02821 #define EDMA3_CCRL_ESR_E22_SHIFT         (0x00000016u)
02822 #define EDMA3_CCRL_ESR_E22_RESETVAL      (0x00000000u)
02823 
02824 /*----E22 Tokens----*/
02825 #define EDMA3_CCRL_ESR_E22_SET           (0x00000001u)
02826 
02827 #define EDMA3_CCRL_ESR_E21_MASK          (0x00200000u)
02828 #define EDMA3_CCRL_ESR_E21_SHIFT         (0x00000015u)
02829 #define EDMA3_CCRL_ESR_E21_RESETVAL      (0x00000000u)
02830 
02831 /*----E21 Tokens----*/
02832 #define EDMA3_CCRL_ESR_E21_SET           (0x00000001u)
02833 
02834 #define EDMA3_CCRL_ESR_E20_MASK          (0x00100000u)
02835 #define EDMA3_CCRL_ESR_E20_SHIFT         (0x00000014u)
02836 #define EDMA3_CCRL_ESR_E20_RESETVAL      (0x00000000u)
02837 
02838 /*----E20 Tokens----*/
02839 #define EDMA3_CCRL_ESR_E20_SET           (0x00000001u)
02840 
02841 #define EDMA3_CCRL_ESR_E19_MASK          (0x00080000u)
02842 #define EDMA3_CCRL_ESR_E19_SHIFT         (0x00000013u)
02843 #define EDMA3_CCRL_ESR_E19_RESETVAL      (0x00000000u)
02844 
02845 /*----E19 Tokens----*/
02846 #define EDMA3_CCRL_ESR_E19_SET           (0x00000001u)
02847 
02848 #define EDMA3_CCRL_ESR_E18_MASK          (0x00040000u)
02849 #define EDMA3_CCRL_ESR_E18_SHIFT         (0x00000012u)
02850 #define EDMA3_CCRL_ESR_E18_RESETVAL      (0x00000000u)
02851 
02852 /*----E18 Tokens----*/
02853 #define EDMA3_CCRL_ESR_E18_SET           (0x00000001u)
02854 
02855 #define EDMA3_CCRL_ESR_E17_MASK          (0x00020000u)
02856 #define EDMA3_CCRL_ESR_E17_SHIFT         (0x00000011u)
02857 #define EDMA3_CCRL_ESR_E17_RESETVAL      (0x00000000u)
02858 
02859 /*----E17 Tokens----*/
02860 #define EDMA3_CCRL_ESR_E17_SET           (0x00000001u)
02861 
02862 #define EDMA3_CCRL_ESR_E16_MASK          (0x00010000u)
02863 #define EDMA3_CCRL_ESR_E16_SHIFT         (0x00000010u)
02864 #define EDMA3_CCRL_ESR_E16_RESETVAL      (0x00000000u)
02865 
02866 /*----E16 Tokens----*/
02867 #define EDMA3_CCRL_ESR_E16_SET           (0x00000001u)
02868 
02869 #define EDMA3_CCRL_ESR_E15_MASK          (0x00008000u)
02870 #define EDMA3_CCRL_ESR_E15_SHIFT         (0x0000000Fu)
02871 #define EDMA3_CCRL_ESR_E15_RESETVAL      (0x00000000u)
02872 
02873 /*----E15 Tokens----*/
02874 #define EDMA3_CCRL_ESR_E15_SET           (0x00000001u)
02875 
02876 #define EDMA3_CCRL_ESR_E14_MASK          (0x00004000u)
02877 #define EDMA3_CCRL_ESR_E14_SHIFT         (0x0000000Eu)
02878 #define EDMA3_CCRL_ESR_E14_RESETVAL      (0x00000000u)
02879 
02880 /*----E14 Tokens----*/
02881 #define EDMA3_CCRL_ESR_E14_SET           (0x00000001u)
02882 
02883 #define EDMA3_CCRL_ESR_E13_MASK          (0x00002000u)
02884 #define EDMA3_CCRL_ESR_E13_SHIFT         (0x0000000Du)
02885 #define EDMA3_CCRL_ESR_E13_RESETVAL      (0x00000000u)
02886 
02887 /*----E13 Tokens----*/
02888 #define EDMA3_CCRL_ESR_E13_SET           (0x00000001u)
02889 
02890 #define EDMA3_CCRL_ESR_E12_MASK          (0x00001000u)
02891 #define EDMA3_CCRL_ESR_E12_SHIFT         (0x0000000Cu)
02892 #define EDMA3_CCRL_ESR_E12_RESETVAL      (0x00000000u)
02893 
02894 /*----E12 Tokens----*/
02895 #define EDMA3_CCRL_ESR_E12_SET           (0x00000001u)
02896 
02897 #define EDMA3_CCRL_ESR_E11_MASK          (0x00000800u)
02898 #define EDMA3_CCRL_ESR_E11_SHIFT         (0x0000000Bu)
02899 #define EDMA3_CCRL_ESR_E11_RESETVAL      (0x00000000u)
02900 
02901 /*----E11 Tokens----*/
02902 #define EDMA3_CCRL_ESR_E11_SET           (0x00000001u)
02903 
02904 #define EDMA3_CCRL_ESR_E10_MASK          (0x00000400u)
02905 #define EDMA3_CCRL_ESR_E10_SHIFT         (0x0000000Au)
02906 #define EDMA3_CCRL_ESR_E10_RESETVAL      (0x00000000u)
02907 
02908 /*----E10 Tokens----*/
02909 #define EDMA3_CCRL_ESR_E10_SET           (0x00000001u)
02910 
02911 #define EDMA3_CCRL_ESR_E9_MASK           (0x00000200u)
02912 #define EDMA3_CCRL_ESR_E9_SHIFT          (0x00000009u)
02913 #define EDMA3_CCRL_ESR_E9_RESETVAL       (0x00000000u)
02914 
02915 /*----E9 Tokens----*/
02916 #define EDMA3_CCRL_ESR_E9_SET            (0x00000001u)
02917 
02918 #define EDMA3_CCRL_ESR_E8_MASK           (0x00000100u)
02919 #define EDMA3_CCRL_ESR_E8_SHIFT          (0x00000008u)
02920 #define EDMA3_CCRL_ESR_E8_RESETVAL       (0x00000000u)
02921 
02922 /*----E8 Tokens----*/
02923 #define EDMA3_CCRL_ESR_E8_SET            (0x00000001u)
02924 
02925 #define EDMA3_CCRL_ESR_E7_MASK           (0x00000080u)
02926 #define EDMA3_CCRL_ESR_E7_SHIFT          (0x00000007u)
02927 #define EDMA3_CCRL_ESR_E7_RESETVAL       (0x00000000u)
02928 
02929 /*----E7 Tokens----*/
02930 #define EDMA3_CCRL_ESR_E7_SET            (0x00000001u)
02931 
02932 #define EDMA3_CCRL_ESR_E6_MASK           (0x00000040u)
02933 #define EDMA3_CCRL_ESR_E6_SHIFT          (0x00000006u)
02934 #define EDMA3_CCRL_ESR_E6_RESETVAL       (0x00000000u)
02935 
02936 /*----E6 Tokens----*/
02937 #define EDMA3_CCRL_ESR_E6_SET            (0x00000001u)
02938 
02939 #define EDMA3_CCRL_ESR_E5_MASK           (0x00000020u)
02940 #define EDMA3_CCRL_ESR_E5_SHIFT          (0x00000005u)
02941 #define EDMA3_CCRL_ESR_E5_RESETVAL       (0x00000000u)
02942 
02943 /*----E5 Tokens----*/
02944 #define EDMA3_CCRL_ESR_E5_SET            (0x00000001u)
02945 
02946 #define EDMA3_CCRL_ESR_E4_MASK           (0x00000010u)
02947 #define EDMA3_CCRL_ESR_E4_SHIFT          (0x00000004u)
02948 #define EDMA3_CCRL_ESR_E4_RESETVAL       (0x00000000u)
02949 
02950 /*----E4 Tokens----*/
02951 #define EDMA3_CCRL_ESR_E4_SET            (0x00000001u)
02952 
02953 #define EDMA3_CCRL_ESR_E3_MASK           (0x00000008u)
02954 #define EDMA3_CCRL_ESR_E3_SHIFT          (0x00000003u)
02955 #define EDMA3_CCRL_ESR_E3_RESETVAL       (0x00000000u)
02956 
02957 /*----E3 Tokens----*/
02958 #define EDMA3_CCRL_ESR_E3_SET            (0x00000001u)
02959 
02960 #define EDMA3_CCRL_ESR_E2_MASK           (0x00000004u)
02961 #define EDMA3_CCRL_ESR_E2_SHIFT          (0x00000002u)
02962 #define EDMA3_CCRL_ESR_E2_RESETVAL       (0x00000000u)
02963 
02964 /*----E2 Tokens----*/
02965 #define EDMA3_CCRL_ESR_E2_SET            (0x00000001u)
02966 
02967 #define EDMA3_CCRL_ESR_E1_MASK           (0x00000002u)
02968 #define EDMA3_CCRL_ESR_E1_SHIFT          (0x00000001u)
02969 #define EDMA3_CCRL_ESR_E1_RESETVAL       (0x00000000u)
02970 
02971 /*----E1 Tokens----*/
02972 #define EDMA3_CCRL_ESR_E1_SET            (0x00000001u)
02973 
02974 #define EDMA3_CCRL_ESR_E0_MASK           (0x00000001u)
02975 #define EDMA3_CCRL_ESR_E0_SHIFT          (0x00000000u)
02976 #define EDMA3_CCRL_ESR_E0_RESETVAL       (0x00000000u)
02977 
02978 /*----E0 Tokens----*/
02979 #define EDMA3_CCRL_ESR_E0_SET            (0x00000001u)
02980 
02981 #define EDMA3_CCRL_ESR_RESETVAL          (0x00000000u)
02982 
02983 /* ESRH */
02984 
02985 #define EDMA3_CCRL_ESRH_E63_MASK         (0x80000000u)
02986 #define EDMA3_CCRL_ESRH_E63_SHIFT        (0x0000001Fu)
02987 #define EDMA3_CCRL_ESRH_E63_RESETVAL     (0x00000000u)
02988 
02989 /*----E63 Tokens----*/
02990 #define EDMA3_CCRL_ESRH_E63_SET          (0x00000001u)
02991 
02992 #define EDMA3_CCRL_ESRH_E62_MASK         (0x40000000u)
02993 #define EDMA3_CCRL_ESRH_E62_SHIFT        (0x0000001Eu)
02994 #define EDMA3_CCRL_ESRH_E62_RESETVAL     (0x00000000u)
02995 
02996 /*----E62 Tokens----*/
02997 #define EDMA3_CCRL_ESRH_E62_SET          (0x00000001u)
02998 
02999 #define EDMA3_CCRL_ESRH_E61_MASK         (0x20000000u)
03000 #define EDMA3_CCRL_ESRH_E61_SHIFT        (0x0000001Du)
03001 #define EDMA3_CCRL_ESRH_E61_RESETVAL     (0x00000000u)
03002 
03003 /*----E61 Tokens----*/
03004 #define EDMA3_CCRL_ESRH_E61_SET          (0x00000001u)
03005 
03006 #define EDMA3_CCRL_ESRH_E60_MASK         (0x10000000u)
03007 #define EDMA3_CCRL_ESRH_E60_SHIFT        (0x0000001Cu)
03008 #define EDMA3_CCRL_ESRH_E60_RESETVAL     (0x00000000u)
03009 
03010 /*----E60 Tokens----*/
03011 #define EDMA3_CCRL_ESRH_E60_SET          (0x00000001u)
03012 
03013 #define EDMA3_CCRL_ESRH_E59_MASK         (0x08000000u)
03014 #define EDMA3_CCRL_ESRH_E59_SHIFT        (0x0000001Bu)
03015 #define EDMA3_CCRL_ESRH_E59_RESETVAL     (0x00000000u)
03016 
03017 /*----E59 Tokens----*/
03018 #define EDMA3_CCRL_ESRH_E59_SET          (0x00000001u)
03019 
03020 #define EDMA3_CCRL_ESRH_E58_MASK         (0x04000000u)
03021 #define EDMA3_CCRL_ESRH_E58_SHIFT        (0x0000001Au)
03022 #define EDMA3_CCRL_ESRH_E58_RESETVAL     (0x00000000u)
03023 
03024 /*----E58 Tokens----*/
03025 #define EDMA3_CCRL_ESRH_E58_SET          (0x00000001u)
03026 
03027 #define EDMA3_CCRL_ESRH_E57_MASK         (0x02000000u)
03028 #define EDMA3_CCRL_ESRH_E57_SHIFT        (0x00000019u)
03029 #define EDMA3_CCRL_ESRH_E57_RESETVAL     (0x00000000u)
03030 
03031 /*----E57 Tokens----*/
03032 #define EDMA3_CCRL_ESRH_E57_SET          (0x00000001u)
03033 
03034 #define EDMA3_CCRL_ESRH_E56_MASK         (0x01000000u)
03035 #define EDMA3_CCRL_ESRH_E56_SHIFT        (0x00000018u)
03036 #define EDMA3_CCRL_ESRH_E56_RESETVAL     (0x00000000u)
03037 
03038 /*----E56 Tokens----*/
03039 #define EDMA3_CCRL_ESRH_E56_SET          (0x00000001u)
03040 
03041 #define EDMA3_CCRL_ESRH_E55_MASK         (0x00800000u)
03042 #define EDMA3_CCRL_ESRH_E55_SHIFT        (0x00000017u)
03043 #define EDMA3_CCRL_ESRH_E55_RESETVAL     (0x00000000u)
03044 
03045 /*----E55 Tokens----*/
03046 #define EDMA3_CCRL_ESRH_E55_SET          (0x00000001u)
03047 
03048 #define EDMA3_CCRL_ESRH_E54_MASK         (0x00400000u)
03049 #define EDMA3_CCRL_ESRH_E54_SHIFT        (0x00000016u)
03050 #define EDMA3_CCRL_ESRH_E54_RESETVAL     (0x00000000u)
03051 
03052 /*----E54 Tokens----*/
03053 #define EDMA3_CCRL_ESRH_E54_SET          (0x00000001u)
03054 
03055 #define EDMA3_CCRL_ESRH_E53_MASK         (0x00200000u)
03056 #define EDMA3_CCRL_ESRH_E53_SHIFT        (0x00000015u)
03057 #define EDMA3_CCRL_ESRH_E53_RESETVAL     (0x00000000u)
03058 
03059 /*----E53 Tokens----*/
03060 #define EDMA3_CCRL_ESRH_E53_SET          (0x00000001u)
03061 
03062 #define EDMA3_CCRL_ESRH_E52_MASK         (0x00100000u)
03063 #define EDMA3_CCRL_ESRH_E52_SHIFT        (0x00000014u)
03064 #define EDMA3_CCRL_ESRH_E52_RESETVAL     (0x00000000u)
03065 
03066 /*----E52 Tokens----*/
03067 #define EDMA3_CCRL_ESRH_E52_SET          (0x00000001u)
03068 
03069 #define EDMA3_CCRL_ESRH_E51_MASK         (0x00080000u)
03070 #define EDMA3_CCRL_ESRH_E51_SHIFT        (0x00000013u)
03071 #define EDMA3_CCRL_ESRH_E51_RESETVAL     (0x00000000u)
03072 
03073 /*----E51 Tokens----*/
03074 #define EDMA3_CCRL_ESRH_E51_SET          (0x00000001u)
03075 
03076 #define EDMA3_CCRL_ESRH_E50_MASK         (0x00040000u)
03077 #define EDMA3_CCRL_ESRH_E50_SHIFT        (0x00000012u)
03078 #define EDMA3_CCRL_ESRH_E50_RESETVAL     (0x00000000u)
03079 
03080 /*----E50 Tokens----*/
03081 #define EDMA3_CCRL_ESRH_E50_SET          (0x00000001u)
03082 
03083 #define EDMA3_CCRL_ESRH_E49_MASK         (0x00020000u)
03084 #define EDMA3_CCRL_ESRH_E49_SHIFT        (0x00000011u)
03085 #define EDMA3_CCRL_ESRH_E49_RESETVAL     (0x00000000u)
03086 
03087 /*----E49 Tokens----*/
03088 #define EDMA3_CCRL_ESRH_E49_SET          (0x00000001u)
03089 
03090 #define EDMA3_CCRL_ESRH_E48_MASK         (0x00010000u)
03091 #define EDMA3_CCRL_ESRH_E48_SHIFT        (0x00000010u)
03092 #define EDMA3_CCRL_ESRH_E48_RESETVAL     (0x00000000u)
03093 
03094 /*----E48 Tokens----*/
03095 #define EDMA3_CCRL_ESRH_E48_SET          (0x00000001u)
03096 
03097 #define EDMA3_CCRL_ESRH_E47_MASK         (0x00008000u)
03098 #define EDMA3_CCRL_ESRH_E47_SHIFT        (0x0000000Fu)
03099 #define EDMA3_CCRL_ESRH_E47_RESETVAL     (0x00000000u)
03100 
03101 /*----E47 Tokens----*/
03102 #define EDMA3_CCRL_ESRH_E47_SET          (0x00000001u)
03103 
03104 #define EDMA3_CCRL_ESRH_E46_MASK         (0x00004000u)
03105 #define EDMA3_CCRL_ESRH_E46_SHIFT        (0x0000000Eu)
03106 #define EDMA3_CCRL_ESRH_E46_RESETVAL     (0x00000000u)
03107 
03108 /*----E46 Tokens----*/
03109 #define EDMA3_CCRL_ESRH_E46_SET          (0x00000001u)
03110 
03111 #define EDMA3_CCRL_ESRH_E45_MASK         (0x00002000u)
03112 #define EDMA3_CCRL_ESRH_E45_SHIFT        (0x0000000Du)
03113 #define EDMA3_CCRL_ESRH_E45_RESETVAL     (0x00000000u)
03114 
03115 /*----E45 Tokens----*/
03116 #define EDMA3_CCRL_ESRH_E45_SET          (0x00000001u)
03117 
03118 #define EDMA3_CCRL_ESRH_E44_MASK         (0x00001000u)
03119 #define EDMA3_CCRL_ESRH_E44_SHIFT        (0x0000000Cu)
03120 #define EDMA3_CCRL_ESRH_E44_RESETVAL     (0x00000000u)
03121 
03122 /*----E44 Tokens----*/
03123 #define EDMA3_CCRL_ESRH_E44_SET          (0x00000001u)
03124 
03125 #define EDMA3_CCRL_ESRH_E43_MASK         (0x00000800u)
03126 #define EDMA3_CCRL_ESRH_E43_SHIFT        (0x0000000Bu)
03127 #define EDMA3_CCRL_ESRH_E43_RESETVAL     (0x00000000u)
03128 
03129 /*----E43 Tokens----*/
03130 #define EDMA3_CCRL_ESRH_E43_SET          (0x00000001u)
03131 
03132 #define EDMA3_CCRL_ESRH_E42_MASK         (0x00000400u)
03133 #define EDMA3_CCRL_ESRH_E42_SHIFT        (0x0000000Au)
03134 #define EDMA3_CCRL_ESRH_E42_RESETVAL     (0x00000000u)
03135 
03136 /*----E42 Tokens----*/
03137 #define EDMA3_CCRL_ESRH_E42_SET          (0x00000001u)
03138 
03139 #define EDMA3_CCRL_ESRH_E41_MASK         (0x00000200u)
03140 #define EDMA3_CCRL_ESRH_E41_SHIFT        (0x00000009u)
03141 #define EDMA3_CCRL_ESRH_E41_RESETVAL     (0x00000000u)
03142 
03143 /*----E41 Tokens----*/
03144 #define EDMA3_CCRL_ESRH_E41_SET          (0x00000001u)
03145 
03146 #define EDMA3_CCRL_ESRH_E40_MASK         (0x00000100u)
03147 #define EDMA3_CCRL_ESRH_E40_SHIFT        (0x00000008u)
03148 #define EDMA3_CCRL_ESRH_E40_RESETVAL     (0x00000000u)
03149 
03150 /*----E40 Tokens----*/
03151 #define EDMA3_CCRL_ESRH_E40_SET          (0x00000001u)
03152 
03153 #define EDMA3_CCRL_ESRH_E39_MASK         (0x00000080u)
03154 #define EDMA3_CCRL_ESRH_E39_SHIFT        (0x00000007u)
03155 #define EDMA3_CCRL_ESRH_E39_RESETVAL     (0x00000000u)
03156 
03157 /*----E39 Tokens----*/
03158 #define EDMA3_CCRL_ESRH_E39_SET          (0x00000001u)
03159 
03160 #define EDMA3_CCRL_ESRH_E38_MASK         (0x00000040u)
03161 #define EDMA3_CCRL_ESRH_E38_SHIFT        (0x00000006u)
03162 #define EDMA3_CCRL_ESRH_E38_RESETVAL     (0x00000000u)
03163 
03164 /*----E38 Tokens----*/
03165 #define EDMA3_CCRL_ESRH_E38_SET          (0x00000001u)
03166 
03167 #define EDMA3_CCRL_ESRH_E37_MASK         (0x00000020u)
03168 #define EDMA3_CCRL_ESRH_E37_SHIFT        (0x00000005u)
03169 #define EDMA3_CCRL_ESRH_E37_RESETVAL     (0x00000000u)
03170 
03171 /*----E37 Tokens----*/
03172 #define EDMA3_CCRL_ESRH_E37_SET          (0x00000001u)
03173 
03174 #define EDMA3_CCRL_ESRH_E36_MASK         (0x00000010u)
03175 #define EDMA3_CCRL_ESRH_E36_SHIFT        (0x00000004u)
03176 #define EDMA3_CCRL_ESRH_E36_RESETVAL     (0x00000000u)
03177 
03178 /*----E36 Tokens----*/
03179 #define EDMA3_CCRL_ESRH_E36_SET          (0x00000001u)
03180 
03181 #define EDMA3_CCRL_ESRH_E35_MASK         (0x00000008u)
03182 #define EDMA3_CCRL_ESRH_E35_SHIFT        (0x00000003u)
03183 #define EDMA3_CCRL_ESRH_E35_RESETVAL     (0x00000000u)
03184 
03185 /*----E35 Tokens----*/
03186 #define EDMA3_CCRL_ESRH_E35_SET          (0x00000001u)
03187 
03188 #define EDMA3_CCRL_ESRH_E34_MASK         (0x00000004u)
03189 #define EDMA3_CCRL_ESRH_E34_SHIFT        (0x00000002u)
03190 #define EDMA3_CCRL_ESRH_E34_RESETVAL     (0x00000000u)
03191 
03192 /*----E34 Tokens----*/
03193 #define EDMA3_CCRL_ESRH_E34_SET          (0x00000001u)
03194 
03195 #define EDMA3_CCRL_ESRH_E33_MASK         (0x00000002u)
03196 #define EDMA3_CCRL_ESRH_E33_SHIFT        (0x00000001u)
03197 #define EDMA3_CCRL_ESRH_E33_RESETVAL     (0x00000000u)
03198 
03199 /*----E33 Tokens----*/
03200 #define EDMA3_CCRL_ESRH_E33_SET          (0x00000001u)
03201 
03202 #define EDMA3_CCRL_ESRH_E32_MASK         (0x00000001u)
03203 #define EDMA3_CCRL_ESRH_E32_SHIFT        (0x00000000u)
03204 #define EDMA3_CCRL_ESRH_E32_RESETVAL     (0x00000000u)
03205 
03206 /*----E32 Tokens----*/
03207 #define EDMA3_CCRL_ESRH_E32_SET          (0x00000001u)
03208 
03209 #define EDMA3_CCRL_ESRH_RESETVAL         (0x00000000u)
03210 
03211 /* CER */
03212 
03213 #define EDMA3_CCRL_CER_E31_MASK          (0x80000000u)
03214 #define EDMA3_CCRL_CER_E31_SHIFT         (0x0000001Fu)
03215 #define EDMA3_CCRL_CER_E31_RESETVAL      (0x00000000u)
03216 
03217 #define EDMA3_CCRL_CER_E30_MASK          (0x40000000u)
03218 #define EDMA3_CCRL_CER_E30_SHIFT         (0x0000001Eu)
03219 #define EDMA3_CCRL_CER_E30_RESETVAL      (0x00000000u)
03220 
03221 #define EDMA3_CCRL_CER_E29_MASK          (0x20000000u)
03222 #define EDMA3_CCRL_CER_E29_SHIFT         (0x0000001Du)
03223 #define EDMA3_CCRL_CER_E29_RESETVAL      (0x00000000u)
03224 
03225 #define EDMA3_CCRL_CER_E28_MASK          (0x10000000u)
03226 #define EDMA3_CCRL_CER_E28_SHIFT         (0x0000001Cu)
03227 #define EDMA3_CCRL_CER_E28_RESETVAL      (0x00000000u)
03228 
03229 #define EDMA3_CCRL_CER_E27_MASK          (0x08000000u)
03230 #define EDMA3_CCRL_CER_E27_SHIFT         (0x0000001Bu)
03231 #define EDMA3_CCRL_CER_E27_RESETVAL      (0x00000000u)
03232 
03233 #define EDMA3_CCRL_CER_E26_MASK          (0x04000000u)
03234 #define EDMA3_CCRL_CER_E26_SHIFT         (0x0000001Au)
03235 #define EDMA3_CCRL_CER_E26_RESETVAL      (0x00000000u)
03236 
03237 #define EDMA3_CCRL_CER_E25_MASK          (0x02000000u)
03238 #define EDMA3_CCRL_CER_E25_SHIFT         (0x00000019u)
03239 #define EDMA3_CCRL_CER_E25_RESETVAL      (0x00000000u)
03240 
03241 #define EDMA3_CCRL_CER_E24_MASK          (0x01000000u)
03242 #define EDMA3_CCRL_CER_E24_SHIFT         (0x00000018u)
03243 #define EDMA3_CCRL_CER_E24_RESETVAL      (0x00000000u)
03244 
03245 #define EDMA3_CCRL_CER_E23_MASK          (0x00800000u)
03246 #define EDMA3_CCRL_CER_E23_SHIFT         (0x00000017u)
03247 #define EDMA3_CCRL_CER_E23_RESETVAL      (0x00000000u)
03248 
03249 #define EDMA3_CCRL_CER_E22_MASK          (0x00400000u)
03250 #define EDMA3_CCRL_CER_E22_SHIFT         (0x00000016u)
03251 #define EDMA3_CCRL_CER_E22_RESETVAL      (0x00000000u)
03252 
03253 #define EDMA3_CCRL_CER_E21_MASK          (0x00200000u)
03254 #define EDMA3_CCRL_CER_E21_SHIFT         (0x00000015u)
03255 #define EDMA3_CCRL_CER_E21_RESETVAL      (0x00000000u)
03256 
03257 #define EDMA3_CCRL_CER_E20_MASK          (0x00100000u)
03258 #define EDMA3_CCRL_CER_E20_SHIFT         (0x00000014u)
03259 #define EDMA3_CCRL_CER_E20_RESETVAL      (0x00000000u)
03260 
03261 #define EDMA3_CCRL_CER_E19_MASK          (0x00080000u)
03262 #define EDMA3_CCRL_CER_E19_SHIFT         (0x00000013u)
03263 #define EDMA3_CCRL_CER_E19_RESETVAL      (0x00000000u)
03264 
03265 #define EDMA3_CCRL_CER_E18_MASK          (0x00040000u)
03266 #define EDMA3_CCRL_CER_E18_SHIFT         (0x00000012u)
03267 #define EDMA3_CCRL_CER_E18_RESETVAL      (0x00000000u)
03268 
03269 #define EDMA3_CCRL_CER_E17_MASK          (0x00020000u)
03270 #define EDMA3_CCRL_CER_E17_SHIFT         (0x00000011u)
03271 #define EDMA3_CCRL_CER_E17_RESETVAL      (0x00000000u)
03272 
03273 #define EDMA3_CCRL_CER_E16_MASK          (0x00010000u)
03274 #define EDMA3_CCRL_CER_E16_SHIFT         (0x00000010u)
03275 #define EDMA3_CCRL_CER_E16_RESETVAL      (0x00000000u)
03276 
03277 #define EDMA3_CCRL_CER_E15_MASK          (0x00008000u)
03278 #define EDMA3_CCRL_CER_E15_SHIFT         (0x0000000Fu)
03279 #define EDMA3_CCRL_CER_E15_RESETVAL      (0x00000000u)
03280 
03281 #define EDMA3_CCRL_CER_E14_MASK          (0x00004000u)
03282 #define EDMA3_CCRL_CER_E14_SHIFT         (0x0000000Eu)
03283 #define EDMA3_CCRL_CER_E14_RESETVAL      (0x00000000u)
03284 
03285 #define EDMA3_CCRL_CER_E13_MASK          (0x00002000u)
03286 #define EDMA3_CCRL_CER_E13_SHIFT         (0x0000000Du)
03287 #define EDMA3_CCRL_CER_E13_RESETVAL      (0x00000000u)
03288 
03289 #define EDMA3_CCRL_CER_E12_MASK          (0x00001000u)
03290 #define EDMA3_CCRL_CER_E12_SHIFT         (0x0000000Cu)
03291 #define EDMA3_CCRL_CER_E12_RESETVAL      (0x00000000u)
03292 
03293 #define EDMA3_CCRL_CER_E11_MASK          (0x00000800u)
03294 #define EDMA3_CCRL_CER_E11_SHIFT         (0x0000000Bu)
03295 #define EDMA3_CCRL_CER_E11_RESETVAL      (0x00000000u)
03296 
03297 #define EDMA3_CCRL_CER_E10_MASK          (0x00000400u)
03298 #define EDMA3_CCRL_CER_E10_SHIFT         (0x0000000Au)
03299 #define EDMA3_CCRL_CER_E10_RESETVAL      (0x00000000u)
03300 
03301 #define EDMA3_CCRL_CER_E9_MASK           (0x00000200u)
03302 #define EDMA3_CCRL_CER_E9_SHIFT          (0x00000009u)
03303 #define EDMA3_CCRL_CER_E9_RESETVAL       (0x00000000u)
03304 
03305 #define EDMA3_CCRL_CER_E8_MASK           (0x00000100u)
03306 #define EDMA3_CCRL_CER_E8_SHIFT          (0x00000008u)
03307 #define EDMA3_CCRL_CER_E8_RESETVAL       (0x00000000u)
03308 
03309 #define EDMA3_CCRL_CER_E7_MASK           (0x00000080u)
03310 #define EDMA3_CCRL_CER_E7_SHIFT          (0x00000007u)
03311 #define EDMA3_CCRL_CER_E7_RESETVAL       (0x00000000u)
03312 
03313 #define EDMA3_CCRL_CER_E6_MASK           (0x00000040u)
03314 #define EDMA3_CCRL_CER_E6_SHIFT          (0x00000006u)
03315 #define EDMA3_CCRL_CER_E6_RESETVAL       (0x00000000u)
03316 
03317 #define EDMA3_CCRL_CER_E5_MASK           (0x00000020u)
03318 #define EDMA3_CCRL_CER_E5_SHIFT          (0x00000005u)
03319 #define EDMA3_CCRL_CER_E5_RESETVAL       (0x00000000u)
03320 
03321 #define EDMA3_CCRL_CER_E4_MASK           (0x00000010u)
03322 #define EDMA3_CCRL_CER_E4_SHIFT          (0x00000004u)
03323 #define EDMA3_CCRL_CER_E4_RESETVAL       (0x00000000u)
03324 
03325 #define EDMA3_CCRL_CER_E3_MASK           (0x00000008u)
03326 #define EDMA3_CCRL_CER_E3_SHIFT          (0x00000003u)
03327 #define EDMA3_CCRL_CER_E3_RESETVAL       (0x00000000u)
03328 
03329 #define EDMA3_CCRL_CER_E2_MASK           (0x00000004u)
03330 #define EDMA3_CCRL_CER_E2_SHIFT          (0x00000002u)
03331 #define EDMA3_CCRL_CER_E2_RESETVAL       (0x00000000u)
03332 
03333 #define EDMA3_CCRL_CER_E1_MASK           (0x00000002u)
03334 #define EDMA3_CCRL_CER_E1_SHIFT          (0x00000001u)
03335 #define EDMA3_CCRL_CER_E1_RESETVAL       (0x00000000u)
03336 
03337 #define EDMA3_CCRL_CER_E0_MASK           (0x00000001u)
03338 #define EDMA3_CCRL_CER_E0_SHIFT          (0x00000000u)
03339 #define EDMA3_CCRL_CER_E0_RESETVAL       (0x00000000u)
03340 
03341 #define EDMA3_CCRL_CER_RESETVAL          (0x00000000u)
03342 
03343 /* CERH */
03344 
03345 #define EDMA3_CCRL_CERH_E63_MASK         (0x80000000u)
03346 #define EDMA3_CCRL_CERH_E63_SHIFT        (0x0000001Fu)
03347 #define EDMA3_CCRL_CERH_E63_RESETVAL     (0x00000000u)
03348 
03349 #define EDMA3_CCRL_CERH_E62_MASK         (0x40000000u)
03350 #define EDMA3_CCRL_CERH_E62_SHIFT        (0x0000001Eu)
03351 #define EDMA3_CCRL_CERH_E62_RESETVAL     (0x00000000u)
03352 
03353 #define EDMA3_CCRL_CERH_E61_MASK         (0x20000000u)
03354 #define EDMA3_CCRL_CERH_E61_SHIFT        (0x0000001Du)
03355 #define EDMA3_CCRL_CERH_E61_RESETVAL     (0x00000000u)
03356 
03357 #define EDMA3_CCRL_CERH_E60_MASK         (0x10000000u)
03358 #define EDMA3_CCRL_CERH_E60_SHIFT        (0x0000001Cu)
03359 #define EDMA3_CCRL_CERH_E60_RESETVAL     (0x00000000u)
03360 
03361 #define EDMA3_CCRL_CERH_E59_MASK         (0x08000000u)
03362 #define EDMA3_CCRL_CERH_E59_SHIFT        (0x0000001Bu)
03363 #define EDMA3_CCRL_CERH_E59_RESETVAL     (0x00000000u)
03364 
03365 #define EDMA3_CCRL_CERH_E58_MASK         (0x04000000u)
03366 #define EDMA3_CCRL_CERH_E58_SHIFT        (0x0000001Au)
03367 #define EDMA3_CCRL_CERH_E58_RESETVAL     (0x00000000u)
03368 
03369 #define EDMA3_CCRL_CERH_E57_MASK         (0x02000000u)
03370 #define EDMA3_CCRL_CERH_E57_SHIFT        (0x00000019u)
03371 #define EDMA3_CCRL_CERH_E57_RESETVAL     (0x00000000u)
03372 
03373 #define EDMA3_CCRL_CERH_E56_MASK         (0x01000000u)
03374 #define EDMA3_CCRL_CERH_E56_SHIFT        (0x00000018u)
03375 #define EDMA3_CCRL_CERH_E56_RESETVAL     (0x00000000u)
03376 
03377 #define EDMA3_CCRL_CERH_E55_MASK         (0x00800000u)
03378 #define EDMA3_CCRL_CERH_E55_SHIFT        (0x00000017u)
03379 #define EDMA3_CCRL_CERH_E55_RESETVAL     (0x00000000u)
03380 
03381 #define EDMA3_CCRL_CERH_E54_MASK         (0x00400000u)
03382 #define EDMA3_CCRL_CERH_E54_SHIFT        (0x00000016u)
03383 #define EDMA3_CCRL_CERH_E54_RESETVAL     (0x00000000u)
03384 
03385 #define EDMA3_CCRL_CERH_E53_MASK         (0x00200000u)
03386 #define EDMA3_CCRL_CERH_E53_SHIFT        (0x00000015u)
03387 #define EDMA3_CCRL_CERH_E53_RESETVAL     (0x00000000u)
03388 
03389 #define EDMA3_CCRL_CERH_E52_MASK         (0x00100000u)
03390 #define EDMA3_CCRL_CERH_E52_SHIFT        (0x00000014u)
03391 #define EDMA3_CCRL_CERH_E52_RESETVAL     (0x00000000u)
03392 
03393 #define EDMA3_CCRL_CERH_E51_MASK         (0x00080000u)
03394 #define EDMA3_CCRL_CERH_E51_SHIFT        (0x00000013u)
03395 #define EDMA3_CCRL_CERH_E51_RESETVAL     (0x00000000u)
03396 
03397 #define EDMA3_CCRL_CERH_E50_MASK         (0x00040000u)
03398 #define EDMA3_CCRL_CERH_E50_SHIFT        (0x00000012u)
03399 #define EDMA3_CCRL_CERH_E50_RESETVAL     (0x00000000u)
03400 
03401 #define EDMA3_CCRL_CERH_E49_MASK         (0x00020000u)
03402 #define EDMA3_CCRL_CERH_E49_SHIFT        (0x00000011u)
03403 #define EDMA3_CCRL_CERH_E49_RESETVAL     (0x00000000u)
03404 
03405 #define EDMA3_CCRL_CERH_E48_MASK         (0x00010000u)
03406 #define EDMA3_CCRL_CERH_E48_SHIFT        (0x00000010u)
03407 #define EDMA3_CCRL_CERH_E48_RESETVAL     (0x00000000u)
03408 
03409 #define EDMA3_CCRL_CERH_E47_MASK         (0x00008000u)
03410 #define EDMA3_CCRL_CERH_E47_SHIFT        (0x0000000Fu)
03411 #define EDMA3_CCRL_CERH_E47_RESETVAL     (0x00000000u)
03412 
03413 #define EDMA3_CCRL_CERH_E46_MASK         (0x00004000u)
03414 #define EDMA3_CCRL_CERH_E46_SHIFT        (0x0000000Eu)
03415 #define EDMA3_CCRL_CERH_E46_RESETVAL     (0x00000000u)
03416 
03417 #define EDMA3_CCRL_CERH_E45_MASK         (0x00002000u)
03418 #define EDMA3_CCRL_CERH_E45_SHIFT        (0x0000000Du)
03419 #define EDMA3_CCRL_CERH_E45_RESETVAL     (0x00000000u)
03420 
03421 #define EDMA3_CCRL_CERH_E44_MASK         (0x00001000u)
03422 #define EDMA3_CCRL_CERH_E44_SHIFT        (0x0000000Cu)
03423 #define EDMA3_CCRL_CERH_E44_RESETVAL     (0x00000000u)
03424 
03425 #define EDMA3_CCRL_CERH_E43_MASK         (0x00000800u)
03426 #define EDMA3_CCRL_CERH_E43_SHIFT        (0x0000000Bu)
03427 #define EDMA3_CCRL_CERH_E43_RESETVAL     (0x00000000u)
03428 
03429 #define EDMA3_CCRL_CERH_E42_MASK         (0x00000400u)
03430 #define EDMA3_CCRL_CERH_E42_SHIFT        (0x0000000Au)
03431 #define EDMA3_CCRL_CERH_E42_RESETVAL     (0x00000000u)
03432 
03433 #define EDMA3_CCRL_CERH_E41_MASK         (0x00000200u)
03434 #define EDMA3_CCRL_CERH_E41_SHIFT        (0x00000009u)
03435 #define EDMA3_CCRL_CERH_E41_RESETVAL     (0x00000000u)
03436 
03437 #define EDMA3_CCRL_CERH_E40_MASK         (0x00000100u)
03438 #define EDMA3_CCRL_CERH_E40_SHIFT        (0x00000008u)
03439 #define EDMA3_CCRL_CERH_E40_RESETVAL     (0x00000000u)
03440 
03441 #define EDMA3_CCRL_CERH_E39_MASK         (0x00000080u)
03442 #define EDMA3_CCRL_CERH_E39_SHIFT        (0x00000007u)
03443 #define EDMA3_CCRL_CERH_E39_RESETVAL     (0x00000000u)
03444 
03445 #define EDMA3_CCRL_CERH_E38_MASK         (0x00000040u)
03446 #define EDMA3_CCRL_CERH_E38_SHIFT        (0x00000006u)
03447 #define EDMA3_CCRL_CERH_E38_RESETVAL     (0x00000000u)
03448 
03449 #define EDMA3_CCRL_CERH_E37_MASK         (0x00000020u)
03450 #define EDMA3_CCRL_CERH_E37_SHIFT        (0x00000005u)
03451 #define EDMA3_CCRL_CERH_E37_RESETVAL     (0x00000000u)
03452 
03453 #define EDMA3_CCRL_CERH_E36_MASK         (0x00000010u)
03454 #define EDMA3_CCRL_CERH_E36_SHIFT        (0x00000004u)
03455 #define EDMA3_CCRL_CERH_E36_RESETVAL     (0x00000000u)
03456 
03457 #define EDMA3_CCRL_CERH_E35_MASK         (0x00000008u)
03458 #define EDMA3_CCRL_CERH_E35_SHIFT        (0x00000003u)
03459 #define EDMA3_CCRL_CERH_E35_RESETVAL     (0x00000000u)
03460 
03461 #define EDMA3_CCRL_CERH_E34_MASK         (0x00000004u)
03462 #define EDMA3_CCRL_CERH_E34_SHIFT        (0x00000002u)
03463 #define EDMA3_CCRL_CERH_E34_RESETVAL     (0x00000000u)
03464 
03465 #define EDMA3_CCRL_CERH_E33_MASK         (0x00000002u)
03466 #define EDMA3_CCRL_CERH_E33_SHIFT        (0x00000001u)
03467 #define EDMA3_CCRL_CERH_E33_RESETVAL     (0x00000000u)
03468 
03469 #define EDMA3_CCRL_CERH_E32_MASK         (0x00000001u)
03470 #define EDMA3_CCRL_CERH_E32_SHIFT        (0x00000000u)
03471 #define EDMA3_CCRL_CERH_E32_RESETVAL     (0x00000000u)
03472 
03473 #define EDMA3_CCRL_CERH_RESETVAL         (0x00000000u)
03474 
03475 /* EER */
03476 
03477 #define EDMA3_CCRL_EER_E31_MASK          (0x80000000u)
03478 #define EDMA3_CCRL_EER_E31_SHIFT         (0x0000001Fu)
03479 #define EDMA3_CCRL_EER_E31_RESETVAL      (0x00000000u)
03480 
03481 /*----E31 Tokens----*/
03482 #define EDMA3_CCRL_EER_E31_              (0x00000001u)
03483 
03484 #define EDMA3_CCRL_EER_E30_MASK          (0x40000000u)
03485 #define EDMA3_CCRL_EER_E30_SHIFT         (0x0000001Eu)
03486 #define EDMA3_CCRL_EER_E30_RESETVAL      (0x00000000u)
03487 
03488 #define EDMA3_CCRL_EER_E29_MASK          (0x20000000u)
03489 #define EDMA3_CCRL_EER_E29_SHIFT         (0x0000001Du)
03490 #define EDMA3_CCRL_EER_E29_RESETVAL      (0x00000000u)
03491 
03492 #define EDMA3_CCRL_EER_E28_MASK          (0x10000000u)
03493 #define EDMA3_CCRL_EER_E28_SHIFT         (0x0000001Cu)
03494 #define EDMA3_CCRL_EER_E28_RESETVAL      (0x00000000u)
03495 
03496 #define EDMA3_CCRL_EER_E27_MASK          (0x08000000u)
03497 #define EDMA3_CCRL_EER_E27_SHIFT         (0x0000001Bu)
03498 #define EDMA3_CCRL_EER_E27_RESETVAL      (0x00000000u)
03499 
03500 #define EDMA3_CCRL_EER_E26_MASK          (0x04000000u)
03501 #define EDMA3_CCRL_EER_E26_SHIFT         (0x0000001Au)
03502 #define EDMA3_CCRL_EER_E26_RESETVAL      (0x00000000u)
03503 
03504 #define EDMA3_CCRL_EER_E25_MASK          (0x02000000u)
03505 #define EDMA3_CCRL_EER_E25_SHIFT         (0x00000019u)
03506 #define EDMA3_CCRL_EER_E25_RESETVAL      (0x00000000u)
03507 
03508 #define EDMA3_CCRL_EER_E24_MASK          (0x01000000u)
03509 #define EDMA3_CCRL_EER_E24_SHIFT         (0x00000018u)
03510 #define EDMA3_CCRL_EER_E24_RESETVAL      (0x00000000u)
03511 
03512 #define EDMA3_CCRL_EER_E23_MASK          (0x00800000u)
03513 #define EDMA3_CCRL_EER_E23_SHIFT         (0x00000017u)
03514 #define EDMA3_CCRL_EER_E23_RESETVAL      (0x00000000u)
03515 
03516 #define EDMA3_CCRL_EER_E22_MASK          (0x00400000u)
03517 #define EDMA3_CCRL_EER_E22_SHIFT         (0x00000016u)
03518 #define EDMA3_CCRL_EER_E22_RESETVAL      (0x00000000u)
03519 
03520 #define EDMA3_CCRL_EER_E21_MASK          (0x00200000u)
03521 #define EDMA3_CCRL_EER_E21_SHIFT         (0x00000015u)
03522 #define EDMA3_CCRL_EER_E21_RESETVAL      (0x00000000u)
03523 
03524 #define EDMA3_CCRL_EER_E20_MASK          (0x00100000u)
03525 #define EDMA3_CCRL_EER_E20_SHIFT         (0x00000014u)
03526 #define EDMA3_CCRL_EER_E20_RESETVAL      (0x00000000u)
03527 
03528 #define EDMA3_CCRL_EER_E19_MASK          (0x00080000u)
03529 #define EDMA3_CCRL_EER_E19_SHIFT         (0x00000013u)
03530 #define EDMA3_CCRL_EER_E19_RESETVAL      (0x00000000u)
03531 
03532 #define EDMA3_CCRL_EER_E18_MASK          (0x00040000u)
03533 #define EDMA3_CCRL_EER_E18_SHIFT         (0x00000012u)
03534 #define EDMA3_CCRL_EER_E18_RESETVAL      (0x00000000u)
03535 
03536 #define EDMA3_CCRL_EER_E17_MASK          (0x00020000u)
03537 #define EDMA3_CCRL_EER_E17_SHIFT         (0x00000011u)
03538 #define EDMA3_CCRL_EER_E17_RESETVAL      (0x00000000u)
03539 
03540 #define EDMA3_CCRL_EER_E16_MASK          (0x00010000u)
03541 #define EDMA3_CCRL_EER_E16_SHIFT         (0x00000010u)
03542 #define EDMA3_CCRL_EER_E16_RESETVAL      (0x00000000u)
03543 
03544 #define EDMA3_CCRL_EER_E15_MASK          (0x00008000u)
03545 #define EDMA3_CCRL_EER_E15_SHIFT         (0x0000000Fu)
03546 #define EDMA3_CCRL_EER_E15_RESETVAL      (0x00000000u)
03547 
03548 #define EDMA3_CCRL_EER_E14_MASK          (0x00004000u)
03549 #define EDMA3_CCRL_EER_E14_SHIFT         (0x0000000Eu)
03550 #define EDMA3_CCRL_EER_E14_RESETVAL      (0x00000000u)
03551 
03552 #define EDMA3_CCRL_EER_E13_MASK          (0x00002000u)
03553 #define EDMA3_CCRL_EER_E13_SHIFT         (0x0000000Du)
03554 #define EDMA3_CCRL_EER_E13_RESETVAL      (0x00000000u)
03555 
03556 #define EDMA3_CCRL_EER_E12_MASK          (0x00001000u)
03557 #define EDMA3_CCRL_EER_E12_SHIFT         (0x0000000Cu)
03558 #define EDMA3_CCRL_EER_E12_RESETVAL      (0x00000000u)
03559 
03560 #define EDMA3_CCRL_EER_E11_MASK          (0x00000800u)
03561 #define EDMA3_CCRL_EER_E11_SHIFT         (0x0000000Bu)
03562 #define EDMA3_CCRL_EER_E11_RESETVAL      (0x00000000u)
03563 
03564 #define EDMA3_CCRL_EER_E10_MASK          (0x00000400u)
03565 #define EDMA3_CCRL_EER_E10_SHIFT         (0x0000000Au)
03566 #define EDMA3_CCRL_EER_E10_RESETVAL      (0x00000000u)
03567 
03568 #define EDMA3_CCRL_EER_E9_MASK           (0x00000200u)
03569 #define EDMA3_CCRL_EER_E9_SHIFT          (0x00000009u)
03570 #define EDMA3_CCRL_EER_E9_RESETVAL       (0x00000000u)
03571 
03572 #define EDMA3_CCRL_EER_E8_MASK           (0x00000100u)
03573 #define EDMA3_CCRL_EER_E8_SHIFT          (0x00000008u)
03574 #define EDMA3_CCRL_EER_E8_RESETVAL       (0x00000000u)
03575 
03576 #define EDMA3_CCRL_EER_E7_MASK           (0x00000080u)
03577 #define EDMA3_CCRL_EER_E7_SHIFT          (0x00000007u)
03578 #define EDMA3_CCRL_EER_E7_RESETVAL       (0x00000000u)
03579 
03580 #define EDMA3_CCRL_EER_E6_MASK           (0x00000040u)
03581 #define EDMA3_CCRL_EER_E6_SHIFT          (0x00000006u)
03582 #define EDMA3_CCRL_EER_E6_RESETVAL       (0x00000000u)
03583 
03584 #define EDMA3_CCRL_EER_E5_MASK           (0x00000020u)
03585 #define EDMA3_CCRL_EER_E5_SHIFT          (0x00000005u)
03586 #define EDMA3_CCRL_EER_E5_RESETVAL       (0x00000000u)
03587 
03588 #define EDMA3_CCRL_EER_E4_MASK           (0x00000010u)
03589 #define EDMA3_CCRL_EER_E4_SHIFT          (0x00000004u)
03590 #define EDMA3_CCRL_EER_E4_RESETVAL       (0x00000000u)
03591 
03592 #define EDMA3_CCRL_EER_E3_MASK           (0x00000008u)
03593 #define EDMA3_CCRL_EER_E3_SHIFT          (0x00000003u)
03594 #define EDMA3_CCRL_EER_E3_RESETVAL       (0x00000000u)
03595 
03596 #define EDMA3_CCRL_EER_E2_MASK           (0x00000004u)
03597 #define EDMA3_CCRL_EER_E2_SHIFT          (0x00000002u)
03598 #define EDMA3_CCRL_EER_E2_RESETVAL       (0x00000000u)
03599 
03600 #define EDMA3_CCRL_EER_E1_MASK           (0x00000002u)
03601 #define EDMA3_CCRL_EER_E1_SHIFT          (0x00000001u)
03602 #define EDMA3_CCRL_EER_E1_RESETVAL       (0x00000000u)
03603 
03604 #define EDMA3_CCRL_EER_E0_MASK           (0x00000001u)
03605 #define EDMA3_CCRL_EER_E0_SHIFT          (0x00000000u)
03606 #define EDMA3_CCRL_EER_E0_RESETVAL       (0x00000000u)
03607 
03608 #define EDMA3_CCRL_EER_RESETVAL          (0x00000000u)
03609 
03610 /* EERH */
03611 
03612 #define EDMA3_CCRL_EERH_E63_MASK         (0x80000000u)
03613 #define EDMA3_CCRL_EERH_E63_SHIFT        (0x0000001Fu)
03614 #define EDMA3_CCRL_EERH_E63_RESETVAL     (0x00000000u)
03615 
03616 #define EDMA3_CCRL_EERH_E62_MASK         (0x40000000u)
03617 #define EDMA3_CCRL_EERH_E62_SHIFT        (0x0000001Eu)
03618 #define EDMA3_CCRL_EERH_E62_RESETVAL     (0x00000000u)
03619 
03620 #define EDMA3_CCRL_EERH_E61_MASK         (0x20000000u)
03621 #define EDMA3_CCRL_EERH_E61_SHIFT        (0x0000001Du)
03622 #define EDMA3_CCRL_EERH_E61_RESETVAL     (0x00000000u)
03623 
03624 #define EDMA3_CCRL_EERH_E60_MASK         (0x10000000u)
03625 #define EDMA3_CCRL_EERH_E60_SHIFT        (0x0000001Cu)
03626 #define EDMA3_CCRL_EERH_E60_RESETVAL     (0x00000000u)
03627 
03628 #define EDMA3_CCRL_EERH_E59_MASK         (0x08000000u)
03629 #define EDMA3_CCRL_EERH_E59_SHIFT        (0x0000001Bu)
03630 #define EDMA3_CCRL_EERH_E59_RESETVAL     (0x00000000u)
03631 
03632 #define EDMA3_CCRL_EERH_E58_MASK         (0x04000000u)
03633 #define EDMA3_CCRL_EERH_E58_SHIFT        (0x0000001Au)
03634 #define EDMA3_CCRL_EERH_E58_RESETVAL     (0x00000000u)
03635 
03636 #define EDMA3_CCRL_EERH_E57_MASK         (0x02000000u)
03637 #define EDMA3_CCRL_EERH_E57_SHIFT        (0x00000019u)
03638 #define EDMA3_CCRL_EERH_E57_RESETVAL     (0x00000000u)
03639 
03640 #define EDMA3_CCRL_EERH_E56_MASK         (0x01000000u)
03641 #define EDMA3_CCRL_EERH_E56_SHIFT        (0x00000018u)
03642 #define EDMA3_CCRL_EERH_E56_RESETVAL     (0x00000000u)
03643 
03644 #define EDMA3_CCRL_EERH_E55_MASK         (0x00800000u)
03645 #define EDMA3_CCRL_EERH_E55_SHIFT        (0x00000017u)
03646 #define EDMA3_CCRL_EERH_E55_RESETVAL     (0x00000000u)
03647 
03648 #define EDMA3_CCRL_EERH_E54_MASK         (0x00400000u)
03649 #define EDMA3_CCRL_EERH_E54_SHIFT        (0x00000016u)
03650 #define EDMA3_CCRL_EERH_E54_RESETVAL     (0x00000000u)
03651 
03652 #define EDMA3_CCRL_EERH_E53_MASK         (0x00200000u)
03653 #define EDMA3_CCRL_EERH_E53_SHIFT        (0x00000015u)
03654 #define EDMA3_CCRL_EERH_E53_RESETVAL     (0x00000000u)
03655 
03656 #define EDMA3_CCRL_EERH_E52_MASK         (0x00100000u)
03657 #define EDMA3_CCRL_EERH_E52_SHIFT        (0x00000014u)
03658 #define EDMA3_CCRL_EERH_E52_RESETVAL     (0x00000000u)
03659 
03660 #define EDMA3_CCRL_EERH_E51_MASK         (0x00080000u)
03661 #define EDMA3_CCRL_EERH_E51_SHIFT        (0x00000013u)
03662 #define EDMA3_CCRL_EERH_E51_RESETVAL     (0x00000000u)
03663 
03664 #define EDMA3_CCRL_EERH_E50_MASK         (0x00040000u)
03665 #define EDMA3_CCRL_EERH_E50_SHIFT        (0x00000012u)
03666 #define EDMA3_CCRL_EERH_E50_RESETVAL     (0x00000000u)
03667 
03668 #define EDMA3_CCRL_EERH_E49_MASK         (0x00020000u)
03669 #define EDMA3_CCRL_EERH_E49_SHIFT        (0x00000011u)
03670 #define EDMA3_CCRL_EERH_E49_RESETVAL     (0x00000000u)
03671 
03672 #define EDMA3_CCRL_EERH_E48_MASK         (0x00010000u)
03673 #define EDMA3_CCRL_EERH_E48_SHIFT        (0x00000010u)
03674 #define EDMA3_CCRL_EERH_E48_RESETVAL     (0x00000000u)
03675 
03676 #define EDMA3_CCRL_EERH_E47_MASK         (0x00008000u)
03677 #define EDMA3_CCRL_EERH_E47_SHIFT        (0x0000000Fu)
03678 #define EDMA3_CCRL_EERH_E47_RESETVAL     (0x00000000u)
03679 
03680 #define EDMA3_CCRL_EERH_E46_MASK         (0x00004000u)
03681 #define EDMA3_CCRL_EERH_E46_SHIFT        (0x0000000Eu)
03682 #define EDMA3_CCRL_EERH_E46_RESETVAL     (0x00000000u)
03683 
03684 #define EDMA3_CCRL_EERH_E45_MASK         (0x00002000u)
03685 #define EDMA3_CCRL_EERH_E45_SHIFT        (0x0000000Du)
03686 #define EDMA3_CCRL_EERH_E45_RESETVAL     (0x00000000u)
03687 
03688 #define EDMA3_CCRL_EERH_E44_MASK         (0x00001000u)
03689 #define EDMA3_CCRL_EERH_E44_SHIFT        (0x0000000Cu)
03690 #define EDMA3_CCRL_EERH_E44_RESETVAL     (0x00000000u)
03691 
03692 #define EDMA3_CCRL_EERH_E43_MASK         (0x00000800u)
03693 #define EDMA3_CCRL_EERH_E43_SHIFT        (0x0000000Bu)
03694 #define EDMA3_CCRL_EERH_E43_RESETVAL     (0x00000000u)
03695 
03696 #define EDMA3_CCRL_EERH_E42_MASK         (0x00000400u)
03697 #define EDMA3_CCRL_EERH_E42_SHIFT        (0x0000000Au)
03698 #define EDMA3_CCRL_EERH_E42_RESETVAL     (0x00000000u)
03699 
03700 #define EDMA3_CCRL_EERH_E41_MASK         (0x00000200u)
03701 #define EDMA3_CCRL_EERH_E41_SHIFT        (0x00000009u)
03702 #define EDMA3_CCRL_EERH_E41_RESETVAL     (0x00000000u)
03703 
03704 #define EDMA3_CCRL_EERH_E40_MASK         (0x00000100u)
03705 #define EDMA3_CCRL_EERH_E40_SHIFT        (0x00000008u)
03706 #define EDMA3_CCRL_EERH_E40_RESETVAL     (0x00000000u)
03707 
03708 #define EDMA3_CCRL_EERH_E39_MASK         (0x00000080u)
03709 #define EDMA3_CCRL_EERH_E39_SHIFT        (0x00000007u)
03710 #define EDMA3_CCRL_EERH_E39_RESETVAL     (0x00000000u)
03711 
03712 #define EDMA3_CCRL_EERH_E38_MASK         (0x00000040u)
03713 #define EDMA3_CCRL_EERH_E38_SHIFT        (0x00000006u)
03714 #define EDMA3_CCRL_EERH_E38_RESETVAL     (0x00000000u)
03715 
03716 #define EDMA3_CCRL_EERH_E37_MASK         (0x00000020u)
03717 #define EDMA3_CCRL_EERH_E37_SHIFT        (0x00000005u)
03718 #define EDMA3_CCRL_EERH_E37_RESETVAL     (0x00000000u)
03719 
03720 #define EDMA3_CCRL_EERH_E36_MASK         (0x00000010u)
03721 #define EDMA3_CCRL_EERH_E36_SHIFT        (0x00000004u)
03722 #define EDMA3_CCRL_EERH_E36_RESETVAL     (0x00000000u)
03723 
03724 #define EDMA3_CCRL_EERH_E35_MASK         (0x00000008u)
03725 #define EDMA3_CCRL_EERH_E35_SHIFT        (0x00000003u)
03726 #define EDMA3_CCRL_EERH_E35_RESETVAL     (0x00000000u)
03727 
03728 #define EDMA3_CCRL_EERH_E34_MASK         (0x00000004u)
03729 #define EDMA3_CCRL_EERH_E34_SHIFT        (0x00000002u)
03730 #define EDMA3_CCRL_EERH_E34_RESETVAL     (0x00000000u)
03731 
03732 #define EDMA3_CCRL_EERH_E33_MASK         (0x00000002u)
03733 #define EDMA3_CCRL_EERH_E33_SHIFT        (0x00000001u)
03734 #define EDMA3_CCRL_EERH_E33_RESETVAL     (0x00000000u)
03735 
03736 #define EDMA3_CCRL_EERH_E32_MASK         (0x00000001u)
03737 #define EDMA3_CCRL_EERH_E32_SHIFT        (0x00000000u)
03738 #define EDMA3_CCRL_EERH_E32_RESETVAL     (0x00000000u)
03739 
03740 #define EDMA3_CCRL_EERH_RESETVAL         (0x00000000u)
03741 
03742 /* EECR */
03743 
03744 #define EDMA3_CCRL_EECR_E31_MASK         (0x80000000u)
03745 #define EDMA3_CCRL_EECR_E31_SHIFT        (0x0000001Fu)
03746 #define EDMA3_CCRL_EECR_E31_RESETVAL     (0x00000000u)
03747 
03748 /*----E31 Tokens----*/
03749 #define EDMA3_CCRL_EECR_E31_CLEAR        (0x00000001u)
03750 
03751 #define EDMA3_CCRL_EECR_E30_MASK         (0x40000000u)
03752 #define EDMA3_CCRL_EECR_E30_SHIFT        (0x0000001Eu)
03753 #define EDMA3_CCRL_EECR_E30_RESETVAL     (0x00000000u)
03754 
03755 /*----E30 Tokens----*/
03756 #define EDMA3_CCRL_EECR_E30_CLEAR        (0x00000001u)
03757 
03758 #define EDMA3_CCRL_EECR_E29_MASK         (0x20000000u)
03759 #define EDMA3_CCRL_EECR_E29_SHIFT        (0x0000001Du)
03760 #define EDMA3_CCRL_EECR_E29_RESETVAL     (0x00000000u)
03761 
03762 /*----E29 Tokens----*/
03763 #define EDMA3_CCRL_EECR_E29_CLEAR        (0x00000001u)
03764 
03765 #define EDMA3_CCRL_EECR_E28_MASK         (0x10000000u)
03766 #define EDMA3_CCRL_EECR_E28_SHIFT        (0x0000001Cu)
03767 #define EDMA3_CCRL_EECR_E28_RESETVAL     (0x00000000u)
03768 
03769 /*----E28 Tokens----*/
03770 #define EDMA3_CCRL_EECR_E28_CLEAR        (0x00000001u)
03771 
03772 #define EDMA3_CCRL_EECR_E27_MASK         (0x08000000u)
03773 #define EDMA3_CCRL_EECR_E27_SHIFT        (0x0000001Bu)
03774 #define EDMA3_CCRL_EECR_E27_RESETVAL     (0x00000000u)
03775 
03776 /*----E27 Tokens----*/
03777 #define EDMA3_CCRL_EECR_E27_CLEAR        (0x00000001u)
03778 
03779 #define EDMA3_CCRL_EECR_E26_MASK         (0x04000000u)
03780 #define EDMA3_CCRL_EECR_E26_SHIFT        (0x0000001Au)
03781 #define EDMA3_CCRL_EECR_E26_RESETVAL     (0x00000000u)
03782 
03783 /*----E26 Tokens----*/
03784 #define EDMA3_CCRL_EECR_E26_CLEAR        (0x00000001u)
03785 
03786 #define EDMA3_CCRL_EECR_E25_MASK         (0x02000000u)
03787 #define EDMA3_CCRL_EECR_E25_SHIFT        (0x00000019u)
03788 #define EDMA3_CCRL_EECR_E25_RESETVAL     (0x00000000u)
03789 
03790 /*----E25 Tokens----*/
03791 #define EDMA3_CCRL_EECR_E25_CLEAR        (0x00000001u)
03792 
03793 #define EDMA3_CCRL_EECR_E24_MASK         (0x01000000u)
03794 #define EDMA3_CCRL_EECR_E24_SHIFT        (0x00000018u)
03795 #define EDMA3_CCRL_EECR_E24_RESETVAL     (0x00000000u)
03796 
03797 /*----E24 Tokens----*/
03798 #define EDMA3_CCRL_EECR_E24_CLEAR        (0x00000001u)
03799 
03800 #define EDMA3_CCRL_EECR_E23_MASK         (0x00800000u)
03801 #define EDMA3_CCRL_EECR_E23_SHIFT        (0x00000017u)
03802 #define EDMA3_CCRL_EECR_E23_RESETVAL     (0x00000000u)
03803 
03804 /*----E23 Tokens----*/
03805 #define EDMA3_CCRL_EECR_E23_CLEAR        (0x00000001u)
03806 
03807 #define EDMA3_CCRL_EECR_E22_MASK         (0x00400000u)
03808 #define EDMA3_CCRL_EECR_E22_SHIFT        (0x00000016u)
03809 #define EDMA3_CCRL_EECR_E22_RESETVAL     (0x00000000u)
03810 
03811 /*----E22 Tokens----*/
03812 #define EDMA3_CCRL_EECR_E22_CLEAR        (0x00000001u)
03813 
03814 #define EDMA3_CCRL_EECR_E21_MASK         (0x00200000u)
03815 #define EDMA3_CCRL_EECR_E21_SHIFT        (0x00000015u)
03816 #define EDMA3_CCRL_EECR_E21_RESETVAL     (0x00000000u)
03817 
03818 /*----E21 Tokens----*/
03819 #define EDMA3_CCRL_EECR_E21_CLEAR        (0x00000001u)
03820 
03821 #define EDMA3_CCRL_EECR_E20_MASK         (0x00100000u)
03822 #define EDMA3_CCRL_EECR_E20_SHIFT        (0x00000014u)
03823 #define EDMA3_CCRL_EECR_E20_RESETVAL     (0x00000000u)
03824 
03825 /*----E20 Tokens----*/
03826 #define EDMA3_CCRL_EECR_E20_CLEAR        (0x00000001u)
03827 
03828 #define EDMA3_CCRL_EECR_E19_MASK         (0x00080000u)
03829 #define EDMA3_CCRL_EECR_E19_SHIFT        (0x00000013u)
03830 #define EDMA3_CCRL_EECR_E19_RESETVAL     (0x00000000u)
03831 
03832 /*----E19 Tokens----*/
03833 #define EDMA3_CCRL_EECR_E19_CLEAR        (0x00000001u)
03834 
03835 #define EDMA3_CCRL_EECR_E18_MASK         (0x00040000u)
03836 #define EDMA3_CCRL_EECR_E18_SHIFT        (0x00000012u)
03837 #define EDMA3_CCRL_EECR_E18_RESETVAL     (0x00000000u)
03838 
03839 /*----E18 Tokens----*/
03840 #define EDMA3_CCRL_EECR_E18_CLEAR        (0x00000001u)
03841 
03842 #define EDMA3_CCRL_EECR_E17_MASK         (0x00020000u)
03843 #define EDMA3_CCRL_EECR_E17_SHIFT        (0x00000011u)
03844 #define EDMA3_CCRL_EECR_E17_RESETVAL     (0x00000000u)
03845 
03846 /*----E17 Tokens----*/
03847 #define EDMA3_CCRL_EECR_E17_CLEAR        (0x00000001u)
03848 
03849 #define EDMA3_CCRL_EECR_E16_MASK         (0x00010000u)
03850 #define EDMA3_CCRL_EECR_E16_SHIFT        (0x00000010u)
03851 #define EDMA3_CCRL_EECR_E16_RESETVAL     (0x00000000u)
03852 
03853 /*----E16 Tokens----*/
03854 #define EDMA3_CCRL_EECR_E16_CLEAR        (0x00000001u)
03855 
03856 #define EDMA3_CCRL_EECR_E15_MASK         (0x00008000u)
03857 #define EDMA3_CCRL_EECR_E15_SHIFT        (0x0000000Fu)
03858 #define EDMA3_CCRL_EECR_E15_RESETVAL     (0x00000000u)
03859 
03860 /*----E15 Tokens----*/
03861 #define EDMA3_CCRL_EECR_E15_CLEAR        (0x00000001u)
03862 
03863 #define EDMA3_CCRL_EECR_E14_MASK         (0x00004000u)
03864 #define EDMA3_CCRL_EECR_E14_SHIFT        (0x0000000Eu)
03865 #define EDMA3_CCRL_EECR_E14_RESETVAL     (0x00000000u)
03866 
03867 /*----E14 Tokens----*/
03868 #define EDMA3_CCRL_EECR_E14_CLEAR        (0x00000001u)
03869 
03870 #define EDMA3_CCRL_EECR_E13_MASK         (0x00002000u)
03871 #define EDMA3_CCRL_EECR_E13_SHIFT        (0x0000000Du)
03872 #define EDMA3_CCRL_EECR_E13_RESETVAL     (0x00000000u)
03873 
03874 /*----E13 Tokens----*/
03875 #define EDMA3_CCRL_EECR_E13_CLEAR        (0x00000001u)
03876 
03877 #define EDMA3_CCRL_EECR_E12_MASK         (0x00001000u)
03878 #define EDMA3_CCRL_EECR_E12_SHIFT        (0x0000000Cu)
03879 #define EDMA3_CCRL_EECR_E12_RESETVAL     (0x00000000u)
03880 
03881 /*----E12 Tokens----*/
03882 #define EDMA3_CCRL_EECR_E12_CLEAR        (0x00000001u)
03883 
03884 #define EDMA3_CCRL_EECR_E11_MASK         (0x00000800u)
03885 #define EDMA3_CCRL_EECR_E11_SHIFT        (0x0000000Bu)
03886 #define EDMA3_CCRL_EECR_E11_RESETVAL     (0x00000000u)
03887 
03888 /*----E11 Tokens----*/
03889 #define EDMA3_CCRL_EECR_E11_CLEAR        (0x00000001u)
03890 
03891 #define EDMA3_CCRL_EECR_E10_MASK         (0x00000400u)
03892 #define EDMA3_CCRL_EECR_E10_SHIFT        (0x0000000Au)
03893 #define EDMA3_CCRL_EECR_E10_RESETVAL     (0x00000000u)
03894 
03895 /*----E10 Tokens----*/
03896 #define EDMA3_CCRL_EECR_E10_CLEAR        (0x00000001u)
03897 
03898 #define EDMA3_CCRL_EECR_E9_MASK          (0x00000200u)
03899 #define EDMA3_CCRL_EECR_E9_SHIFT         (0x00000009u)
03900 #define EDMA3_CCRL_EECR_E9_RESETVAL      (0x00000000u)
03901 
03902 /*----E9 Tokens----*/
03903 #define EDMA3_CCRL_EECR_E9_CLEAR         (0x00000001u)
03904 
03905 #define EDMA3_CCRL_EECR_E8_MASK          (0x00000100u)
03906 #define EDMA3_CCRL_EECR_E8_SHIFT         (0x00000008u)
03907 #define EDMA3_CCRL_EECR_E8_RESETVAL      (0x00000000u)
03908 
03909 /*----E8 Tokens----*/
03910 #define EDMA3_CCRL_EECR_E8_CLEAR         (0x00000001u)
03911 
03912 #define EDMA3_CCRL_EECR_E7_MASK          (0x00000080u)
03913 #define EDMA3_CCRL_EECR_E7_SHIFT         (0x00000007u)
03914 #define EDMA3_CCRL_EECR_E7_RESETVAL      (0x00000000u)
03915 
03916 /*----E7 Tokens----*/
03917 #define EDMA3_CCRL_EECR_E7_CLEAR         (0x00000001u)
03918 
03919 #define EDMA3_CCRL_EECR_E6_MASK          (0x00000040u)
03920 #define EDMA3_CCRL_EECR_E6_SHIFT         (0x00000006u)
03921 #define EDMA3_CCRL_EECR_E6_RESETVAL      (0x00000000u)
03922 
03923 /*----E6 Tokens----*/
03924 #define EDMA3_CCRL_EECR_E6_CLEAR         (0x00000001u)
03925 
03926 #define EDMA3_CCRL_EECR_E5_MASK          (0x00000020u)
03927 #define EDMA3_CCRL_EECR_E5_SHIFT         (0x00000005u)
03928 #define EDMA3_CCRL_EECR_E5_RESETVAL      (0x00000000u)
03929 
03930 /*----E5 Tokens----*/
03931 #define EDMA3_CCRL_EECR_E5_CLEAR         (0x00000001u)
03932 
03933 #define EDMA3_CCRL_EECR_E4_MASK          (0x00000010u)
03934 #define EDMA3_CCRL_EECR_E4_SHIFT         (0x00000004u)
03935 #define EDMA3_CCRL_EECR_E4_RESETVAL      (0x00000000u)
03936 
03937 /*----E4 Tokens----*/
03938 #define EDMA3_CCRL_EECR_E4_CLEAR         (0x00000001u)
03939 
03940 #define EDMA3_CCRL_EECR_E3_MASK          (0x00000008u)
03941 #define EDMA3_CCRL_EECR_E3_SHIFT         (0x00000003u)
03942 #define EDMA3_CCRL_EECR_E3_RESETVAL      (0x00000000u)
03943 
03944 /*----E3 Tokens----*/
03945 #define EDMA3_CCRL_EECR_E3_CLEAR         (0x00000001u)
03946 
03947 #define EDMA3_CCRL_EECR_E2_MASK          (0x00000004u)
03948 #define EDMA3_CCRL_EECR_E2_SHIFT         (0x00000002u)
03949 #define EDMA3_CCRL_EECR_E2_RESETVAL      (0x00000000u)
03950 
03951 /*----E2 Tokens----*/
03952 #define EDMA3_CCRL_EECR_E2_CLEAR         (0x00000001u)
03953 
03954 #define EDMA3_CCRL_EECR_E1_MASK          (0x00000002u)
03955 #define EDMA3_CCRL_EECR_E1_SHIFT         (0x00000001u)
03956 #define EDMA3_CCRL_EECR_E1_RESETVAL      (0x00000000u)
03957 
03958 /*----E1 Tokens----*/
03959 #define EDMA3_CCRL_EECR_E1_CLEAR         (0x00000001u)
03960 
03961 #define EDMA3_CCRL_EECR_E0_MASK          (0x00000001u)
03962 #define EDMA3_CCRL_EECR_E0_SHIFT         (0x00000000u)
03963 #define EDMA3_CCRL_EECR_E0_RESETVAL      (0x00000000u)
03964 
03965 /*----E0 Tokens----*/
03966 #define EDMA3_CCRL_EECR_E0_CLEAR         (0x00000001u)
03967 
03968 #define EDMA3_CCRL_EECR_RESETVAL         (0x00000000u)
03969 
03970 /* EECRH */
03971 
03972 #define EDMA3_CCRL_EECRH_E63_MASK        (0x80000000u)
03973 #define EDMA3_CCRL_EECRH_E63_SHIFT       (0x0000001Fu)
03974 #define EDMA3_CCRL_EECRH_E63_RESETVAL    (0x00000000u)
03975 
03976 /*----E63 Tokens----*/
03977 #define EDMA3_CCRL_EECRH_E63_CLEAR       (0x00000001u)
03978 
03979 #define EDMA3_CCRL_EECRH_E62_MASK        (0x40000000u)
03980 #define EDMA3_CCRL_EECRH_E62_SHIFT       (0x0000001Eu)
03981 #define EDMA3_CCRL_EECRH_E62_RESETVAL    (0x00000000u)
03982 
03983 /*----E62 Tokens----*/
03984 #define EDMA3_CCRL_EECRH_E62_CLEAR       (0x00000001u)
03985 
03986 #define EDMA3_CCRL_EECRH_E61_MASK        (0x20000000u)
03987 #define EDMA3_CCRL_EECRH_E61_SHIFT       (0x0000001Du)
03988 #define EDMA3_CCRL_EECRH_E61_RESETVAL    (0x00000000u)
03989 
03990 /*----E61 Tokens----*/
03991 #define EDMA3_CCRL_EECRH_E61_CLEAR       (0x00000001u)
03992 
03993 #define EDMA3_CCRL_EECRH_E60_MASK        (0x10000000u)
03994 #define EDMA3_CCRL_EECRH_E60_SHIFT       (0x0000001Cu)
03995 #define EDMA3_CCRL_EECRH_E60_RESETVAL    (0x00000000u)
03996 
03997 /*----E60 Tokens----*/
03998 #define EDMA3_CCRL_EECRH_E60_CLEAR       (0x00000001u)
03999 
04000 #define EDMA3_CCRL_EECRH_E59_MASK        (0x08000000u)
04001 #define EDMA3_CCRL_EECRH_E59_SHIFT       (0x0000001Bu)
04002 #define EDMA3_CCRL_EECRH_E59_RESETVAL    (0x00000000u)
04003 
04004 /*----E59 Tokens----*/
04005 #define EDMA3_CCRL_EECRH_E59_CLEAR       (0x00000001u)
04006 
04007 #define EDMA3_CCRL_EECRH_E58_MASK        (0x04000000u)
04008 #define EDMA3_CCRL_EECRH_E58_SHIFT       (0x0000001Au)
04009 #define EDMA3_CCRL_EECRH_E58_RESETVAL    (0x00000000u)
04010 
04011 /*----E58 Tokens----*/
04012 #define EDMA3_CCRL_EECRH_E58_CLEAR       (0x00000001u)
04013 
04014 #define EDMA3_CCRL_EECRH_E57_MASK        (0x02000000u)
04015 #define EDMA3_CCRL_EECRH_E57_SHIFT       (0x00000019u)
04016 #define EDMA3_CCRL_EECRH_E57_RESETVAL    (0x00000000u)
04017 
04018 /*----E57 Tokens----*/
04019 #define EDMA3_CCRL_EECRH_E57_CLEAR       (0x00000001u)
04020 
04021 #define EDMA3_CCRL_EECRH_E56_MASK        (0x01000000u)
04022 #define EDMA3_CCRL_EECRH_E56_SHIFT       (0x00000018u)
04023 #define EDMA3_CCRL_EECRH_E56_RESETVAL    (0x00000000u)
04024 
04025 /*----E56 Tokens----*/
04026 #define EDMA3_CCRL_EECRH_E56_CLEAR       (0x00000001u)
04027 
04028 #define EDMA3_CCRL_EECRH_E55_MASK        (0x00800000u)
04029 #define EDMA3_CCRL_EECRH_E55_SHIFT       (0x00000017u)
04030 #define EDMA3_CCRL_EECRH_E55_RESETVAL    (0x00000000u)
04031 
04032 /*----E55 Tokens----*/
04033 #define EDMA3_CCRL_EECRH_E55_CLEAR       (0x00000001u)
04034 
04035 #define EDMA3_CCRL_EECRH_E54_MASK        (0x00400000u)
04036 #define EDMA3_CCRL_EECRH_E54_SHIFT       (0x00000016u)
04037 #define EDMA3_CCRL_EECRH_E54_RESETVAL    (0x00000000u)
04038 
04039 /*----E54 Tokens----*/
04040 #define EDMA3_CCRL_EECRH_E54_CLEAR       (0x00000001u)
04041 
04042 #define EDMA3_CCRL_EECRH_E53_MASK        (0x00200000u)
04043 #define EDMA3_CCRL_EECRH_E53_SHIFT       (0x00000015u)
04044 #define EDMA3_CCRL_EECRH_E53_RESETVAL    (0x00000000u)
04045 
04046 /*----E53 Tokens----*/
04047 #define EDMA3_CCRL_EECRH_E53_CLEAR       (0x00000001u)
04048 
04049 #define EDMA3_CCRL_EECRH_E52_MASK        (0x00100000u)
04050 #define EDMA3_CCRL_EECRH_E52_SHIFT       (0x00000014u)
04051 #define EDMA3_CCRL_EECRH_E52_RESETVAL    (0x00000000u)
04052 
04053 /*----E52 Tokens----*/
04054 #define EDMA3_CCRL_EECRH_E52_CLEAR       (0x00000001u)
04055 
04056 #define EDMA3_CCRL_EECRH_E51_MASK        (0x00080000u)
04057 #define EDMA3_CCRL_EECRH_E51_SHIFT       (0x00000013u)
04058 #define EDMA3_CCRL_EECRH_E51_RESETVAL    (0x00000000u)
04059 
04060 /*----E51 Tokens----*/
04061 #define EDMA3_CCRL_EECRH_E51_CLEAR       (0x00000001u)
04062 
04063 #define EDMA3_CCRL_EECRH_E50_MASK        (0x00040000u)
04064 #define EDMA3_CCRL_EECRH_E50_SHIFT       (0x00000012u)
04065 #define EDMA3_CCRL_EECRH_E50_RESETVAL    (0x00000000u)
04066 
04067 /*----E50 Tokens----*/
04068 #define EDMA3_CCRL_EECRH_E50_CLEAR       (0x00000001u)
04069 
04070 #define EDMA3_CCRL_EECRH_E49_MASK        (0x00020000u)
04071 #define EDMA3_CCRL_EECRH_E49_SHIFT       (0x00000011u)
04072 #define EDMA3_CCRL_EECRH_E49_RESETVAL    (0x00000000u)
04073 
04074 /*----E49 Tokens----*/
04075 #define EDMA3_CCRL_EECRH_E49_CLEAR       (0x00000001u)
04076 
04077 #define EDMA3_CCRL_EECRH_E48_MASK        (0x00010000u)
04078 #define EDMA3_CCRL_EECRH_E48_SHIFT       (0x00000010u)
04079 #define EDMA3_CCRL_EECRH_E48_RESETVAL    (0x00000000u)
04080 
04081 /*----E48 Tokens----*/
04082 #define EDMA3_CCRL_EECRH_E48_CLEAR       (0x00000001u)
04083 
04084 #define EDMA3_CCRL_EECRH_E47_MASK        (0x00008000u)
04085 #define EDMA3_CCRL_EECRH_E47_SHIFT       (0x0000000Fu)
04086 #define EDMA3_CCRL_EECRH_E47_RESETVAL    (0x00000000u)
04087 
04088 /*----E47 Tokens----*/
04089 #define EDMA3_CCRL_EECRH_E47_CLEAR       (0x00000001u)
04090 
04091 #define EDMA3_CCRL_EECRH_E46_MASK        (0x00004000u)
04092 #define EDMA3_CCRL_EECRH_E46_SHIFT       (0x0000000Eu)
04093 #define EDMA3_CCRL_EECRH_E46_RESETVAL    (0x00000000u)
04094 
04095 /*----E46 Tokens----*/
04096 #define EDMA3_CCRL_EECRH_E46_CLEAR       (0x00000001u)
04097 
04098 #define EDMA3_CCRL_EECRH_E45_MASK        (0x00002000u)
04099 #define EDMA3_CCRL_EECRH_E45_SHIFT       (0x0000000Du)
04100 #define EDMA3_CCRL_EECRH_E45_RESETVAL    (0x00000000u)
04101 
04102 /*----E45 Tokens----*/
04103 #define EDMA3_CCRL_EECRH_E45_CLEAR       (0x00000001u)
04104 
04105 #define EDMA3_CCRL_EECRH_E44_MASK        (0x00001000u)
04106 #define EDMA3_CCRL_EECRH_E44_SHIFT       (0x0000000Cu)
04107 #define EDMA3_CCRL_EECRH_E44_RESETVAL    (0x00000000u)
04108 
04109 /*----E44 Tokens----*/
04110 #define EDMA3_CCRL_EECRH_E44_CLEAR       (0x00000001u)
04111 
04112 #define EDMA3_CCRL_EECRH_E43_MASK        (0x00000800u)
04113 #define EDMA3_CCRL_EECRH_E43_SHIFT       (0x0000000Bu)
04114 #define EDMA3_CCRL_EECRH_E43_RESETVAL    (0x00000000u)
04115 
04116 /*----E43 Tokens----*/
04117 #define EDMA3_CCRL_EECRH_E43_CLEAR       (0x00000001u)
04118 
04119 #define EDMA3_CCRL_EECRH_E42_MASK        (0x00000400u)
04120 #define EDMA3_CCRL_EECRH_E42_SHIFT       (0x0000000Au)
04121 #define EDMA3_CCRL_EECRH_E42_RESETVAL    (0x00000000u)
04122 
04123 /*----E42 Tokens----*/
04124 #define EDMA3_CCRL_EECRH_E42_CLEAR       (0x00000001u)
04125 
04126 #define EDMA3_CCRL_EECRH_E41_MASK        (0x00000200u)
04127 #define EDMA3_CCRL_EECRH_E41_SHIFT       (0x00000009u)
04128 #define EDMA3_CCRL_EECRH_E41_RESETVAL    (0x00000000u)
04129 
04130 /*----E41 Tokens----*/
04131 #define EDMA3_CCRL_EECRH_E41_CLEAR       (0x00000001u)
04132 
04133 #define EDMA3_CCRL_EECRH_E40_MASK        (0x00000100u)
04134 #define EDMA3_CCRL_EECRH_E40_SHIFT       (0x00000008u)
04135 #define EDMA3_CCRL_EECRH_E40_RESETVAL    (0x00000000u)
04136 
04137 /*----E40 Tokens----*/
04138 #define EDMA3_CCRL_EECRH_E40_CLEAR       (0x00000001u)
04139 
04140 #define EDMA3_CCRL_EECRH_E39_MASK        (0x00000080u)
04141 #define EDMA3_CCRL_EECRH_E39_SHIFT       (0x00000007u)
04142 #define EDMA3_CCRL_EECRH_E39_RESETVAL    (0x00000000u)
04143 
04144 /*----E39 Tokens----*/
04145 #define EDMA3_CCRL_EECRH_E39_CLEAR       (0x00000001u)
04146 
04147 #define EDMA3_CCRL_EECRH_E38_MASK        (0x00000040u)
04148 #define EDMA3_CCRL_EECRH_E38_SHIFT       (0x00000006u)
04149 #define EDMA3_CCRL_EECRH_E38_RESETVAL    (0x00000000u)
04150 
04151 /*----E38 Tokens----*/
04152 #define EDMA3_CCRL_EECRH_E38_CLEAR       (0x00000001u)
04153 
04154 #define EDMA3_CCRL_EECRH_E37_MASK        (0x00000020u)
04155 #define EDMA3_CCRL_EECRH_E37_SHIFT       (0x00000005u)
04156 #define EDMA3_CCRL_EECRH_E37_RESETVAL    (0x00000000u)
04157 
04158 /*----E37 Tokens----*/
04159 #define EDMA3_CCRL_EECRH_E37_CLEAR       (0x00000001u)
04160 
04161 #define EDMA3_CCRL_EECRH_E36_MASK        (0x00000010u)
04162 #define EDMA3_CCRL_EECRH_E36_SHIFT       (0x00000004u)
04163 #define EDMA3_CCRL_EECRH_E36_RESETVAL    (0x00000000u)
04164 
04165 /*----E36 Tokens----*/
04166 #define EDMA3_CCRL_EECRH_E36_CLEAR       (0x00000001u)
04167 
04168 #define EDMA3_CCRL_EECRH_E35_MASK        (0x00000008u)
04169 #define EDMA3_CCRL_EECRH_E35_SHIFT       (0x00000003u)
04170 #define EDMA3_CCRL_EECRH_E35_RESETVAL    (0x00000000u)
04171 
04172 /*----E35 Tokens----*/
04173 #define EDMA3_CCRL_EECRH_E35_CLEAR       (0x00000001u)
04174 
04175 #define EDMA3_CCRL_EECRH_E34_MASK        (0x00000004u)
04176 #define EDMA3_CCRL_EECRH_E34_SHIFT       (0x00000002u)
04177 #define EDMA3_CCRL_EECRH_E34_RESETVAL    (0x00000000u)
04178 
04179 /*----E34 Tokens----*/
04180 #define EDMA3_CCRL_EECRH_E34_CLEAR       (0x00000001u)
04181 
04182 #define EDMA3_CCRL_EECRH_E33_MASK        (0x00000002u)
04183 #define EDMA3_CCRL_EECRH_E33_SHIFT       (0x00000001u)
04184 #define EDMA3_CCRL_EECRH_E33_RESETVAL    (0x00000000u)
04185 
04186 /*----E33 Tokens----*/
04187 #define EDMA3_CCRL_EECRH_E33_CLEAR       (0x00000001u)
04188 
04189 #define EDMA3_CCRL_EECRH_E32_MASK        (0x00000001u)
04190 #define EDMA3_CCRL_EECRH_E32_SHIFT       (0x00000000u)
04191 #define EDMA3_CCRL_EECRH_E32_RESETVAL    (0x00000000u)
04192 
04193 /*----E32 Tokens----*/
04194 #define EDMA3_CCRL_EECRH_E32_CLEAR       (0x00000001u)
04195 
04196 #define EDMA3_CCRL_EECRH_RESETVAL        (0x00000000u)
04197 
04198 /* EESR */
04199 
04200 #define EDMA3_CCRL_EESR_E31_MASK         (0x80000000u)
04201 #define EDMA3_CCRL_EESR_E31_SHIFT        (0x0000001Fu)
04202 #define EDMA3_CCRL_EESR_E31_RESETVAL     (0x00000000u)
04203 
04204 /*----E31 Tokens----*/
04205 #define EDMA3_CCRL_EESR_E31_SET          (0x00000001u)
04206 
04207 #define EDMA3_CCRL_EESR_E30_MASK         (0x40000000u)
04208 #define EDMA3_CCRL_EESR_E30_SHIFT        (0x0000001Eu)
04209 #define EDMA3_CCRL_EESR_E30_RESETVAL     (0x00000000u)
04210 
04211 /*----E30 Tokens----*/
04212 #define EDMA3_CCRL_EESR_E30_SET          (0x00000001u)
04213 
04214 #define EDMA3_CCRL_EESR_E29_MASK         (0x20000000u)
04215 #define EDMA3_CCRL_EESR_E29_SHIFT        (0x0000001Du)
04216 #define EDMA3_CCRL_EESR_E29_RESETVAL     (0x00000000u)
04217 
04218 /*----E29 Tokens----*/
04219 #define EDMA3_CCRL_EESR_E29_SET          (0x00000001u)
04220 
04221 #define EDMA3_CCRL_EESR_E28_MASK         (0x10000000u)
04222 #define EDMA3_CCRL_EESR_E28_SHIFT        (0x0000001Cu)
04223 #define EDMA3_CCRL_EESR_E28_RESETVAL     (0x00000000u)
04224 
04225 /*----E28 Tokens----*/
04226 #define EDMA3_CCRL_EESR_E28_SET          (0x00000001u)
04227 
04228 #define EDMA3_CCRL_EESR_E27_MASK         (0x08000000u)
04229 #define EDMA3_CCRL_EESR_E27_SHIFT        (0x0000001Bu)
04230 #define EDMA3_CCRL_EESR_E27_RESETVAL     (0x00000000u)
04231 
04232 /*----E27 Tokens----*/
04233 #define EDMA3_CCRL_EESR_E27_SET          (0x00000001u)
04234 
04235 #define EDMA3_CCRL_EESR_E26_MASK         (0x04000000u)
04236 #define EDMA3_CCRL_EESR_E26_SHIFT        (0x0000001Au)
04237 #define EDMA3_CCRL_EESR_E26_RESETVAL     (0x00000000u)
04238 
04239 /*----E26 Tokens----*/
04240 #define EDMA3_CCRL_EESR_E26_SET          (0x00000001u)
04241 
04242 #define EDMA3_CCRL_EESR_E25_MASK         (0x02000000u)
04243 #define EDMA3_CCRL_EESR_E25_SHIFT        (0x00000019u)
04244 #define EDMA3_CCRL_EESR_E25_RESETVAL     (0x00000000u)
04245 
04246 /*----E25 Tokens----*/
04247 #define EDMA3_CCRL_EESR_E25_SET          (0x00000001u)
04248 
04249 #define EDMA3_CCRL_EESR_E24_MASK         (0x01000000u)
04250 #define EDMA3_CCRL_EESR_E24_SHIFT        (0x00000018u)
04251 #define EDMA3_CCRL_EESR_E24_RESETVAL     (0x00000000u)
04252 
04253 /*----E24 Tokens----*/
04254 #define EDMA3_CCRL_EESR_E24_SET          (0x00000001u)
04255 
04256 #define EDMA3_CCRL_EESR_E23_MASK         (0x00800000u)
04257 #define EDMA3_CCRL_EESR_E23_SHIFT        (0x00000017u)
04258 #define EDMA3_CCRL_EESR_E23_RESETVAL     (0x00000000u)
04259 
04260 /*----E23 Tokens----*/
04261 #define EDMA3_CCRL_EESR_E23_SET          (0x00000001u)
04262 
04263 #define EDMA3_CCRL_EESR_E22_MASK         (0x00400000u)
04264 #define EDMA3_CCRL_EESR_E22_SHIFT        (0x00000016u)
04265 #define EDMA3_CCRL_EESR_E22_RESETVAL     (0x00000000u)
04266 
04267 /*----E22 Tokens----*/
04268 #define EDMA3_CCRL_EESR_E22_SET          (0x00000001u)
04269 
04270 #define EDMA3_CCRL_EESR_E21_MASK         (0x00200000u)
04271 #define EDMA3_CCRL_EESR_E21_SHIFT        (0x00000015u)
04272 #define EDMA3_CCRL_EESR_E21_RESETVAL     (0x00000000u)
04273 
04274 /*----E21 Tokens----*/
04275 #define EDMA3_CCRL_EESR_E21_SET          (0x00000001u)
04276 
04277 #define EDMA3_CCRL_EESR_E20_MASK         (0x00100000u)
04278 #define EDMA3_CCRL_EESR_E20_SHIFT        (0x00000014u)
04279 #define EDMA3_CCRL_EESR_E20_RESETVAL     (0x00000000u)
04280 
04281 /*----E20 Tokens----*/
04282 #define EDMA3_CCRL_EESR_E20_SET          (0x00000001u)
04283 
04284 #define EDMA3_CCRL_EESR_E19_MASK         (0x00080000u)
04285 #define EDMA3_CCRL_EESR_E19_SHIFT        (0x00000013u)
04286 #define EDMA3_CCRL_EESR_E19_RESETVAL     (0x00000000u)
04287 
04288 /*----E19 Tokens----*/
04289 #define EDMA3_CCRL_EESR_E19_SET          (0x00000001u)
04290 
04291 #define EDMA3_CCRL_EESR_E18_MASK         (0x00040000u)
04292 #define EDMA3_CCRL_EESR_E18_SHIFT        (0x00000012u)
04293 #define EDMA3_CCRL_EESR_E18_RESETVAL     (0x00000000u)
04294 
04295 /*----E18 Tokens----*/
04296 #define EDMA3_CCRL_EESR_E18_SET          (0x00000001u)
04297 
04298 #define EDMA3_CCRL_EESR_E17_MASK         (0x00020000u)
04299 #define EDMA3_CCRL_EESR_E17_SHIFT        (0x00000011u)
04300 #define EDMA3_CCRL_EESR_E17_RESETVAL     (0x00000000u)
04301 
04302 /*----E17 Tokens----*/
04303 #define EDMA3_CCRL_EESR_E17_SET          (0x00000001u)
04304 
04305 #define EDMA3_CCRL_EESR_E16_MASK         (0x00010000u)
04306 #define EDMA3_CCRL_EESR_E16_SHIFT        (0x00000010u)
04307 #define EDMA3_CCRL_EESR_E16_RESETVAL     (0x00000000u)
04308 
04309 /*----E16 Tokens----*/
04310 #define EDMA3_CCRL_EESR_E16_SET          (0x00000001u)
04311 
04312 #define EDMA3_CCRL_EESR_E15_MASK         (0x00008000u)
04313 #define EDMA3_CCRL_EESR_E15_SHIFT        (0x0000000Fu)
04314 #define EDMA3_CCRL_EESR_E15_RESETVAL     (0x00000000u)
04315 
04316 /*----E15 Tokens----*/
04317 #define EDMA3_CCRL_EESR_E15_SET          (0x00000001u)
04318 
04319 #define EDMA3_CCRL_EESR_E14_MASK         (0x00004000u)
04320 #define EDMA3_CCRL_EESR_E14_SHIFT        (0x0000000Eu)
04321 #define EDMA3_CCRL_EESR_E14_RESETVAL     (0x00000000u)
04322 
04323 /*----E14 Tokens----*/
04324 #define EDMA3_CCRL_EESR_E14_SET          (0x00000001u)
04325 
04326 #define EDMA3_CCRL_EESR_E13_MASK         (0x00002000u)
04327 #define EDMA3_CCRL_EESR_E13_SHIFT        (0x0000000Du)
04328 #define EDMA3_CCRL_EESR_E13_RESETVAL     (0x00000000u)
04329 
04330 /*----E13 Tokens----*/
04331 #define EDMA3_CCRL_EESR_E13_SET          (0x00000001u)
04332 
04333 #define EDMA3_CCRL_EESR_E12_MASK         (0x00001000u)
04334 #define EDMA3_CCRL_EESR_E12_SHIFT        (0x0000000Cu)
04335 #define EDMA3_CCRL_EESR_E12_RESETVAL     (0x00000000u)
04336 
04337 /*----E12 Tokens----*/
04338 #define EDMA3_CCRL_EESR_E12_SET          (0x00000001u)
04339 
04340 #define EDMA3_CCRL_EESR_E11_MASK         (0x00000800u)
04341 #define EDMA3_CCRL_EESR_E11_SHIFT        (0x0000000Bu)
04342 #define EDMA3_CCRL_EESR_E11_RESETVAL     (0x00000000u)
04343 
04344 /*----E11 Tokens----*/
04345 #define EDMA3_CCRL_EESR_E11_SET          (0x00000001u)
04346 
04347 #define EDMA3_CCRL_EESR_E10_MASK         (0x00000400u)
04348 #define EDMA3_CCRL_EESR_E10_SHIFT        (0x0000000Au)
04349 #define EDMA3_CCRL_EESR_E10_RESETVAL     (0x00000000u)
04350 
04351 /*----E10 Tokens----*/
04352 #define EDMA3_CCRL_EESR_E10_SET          (0x00000001u)
04353 
04354 #define EDMA3_CCRL_EESR_E9_MASK          (0x00000200u)
04355 #define EDMA3_CCRL_EESR_E9_SHIFT         (0x00000009u)
04356 #define EDMA3_CCRL_EESR_E9_RESETVAL      (0x00000000u)
04357 
04358 /*----E9 Tokens----*/
04359 #define EDMA3_CCRL_EESR_E9_SET           (0x00000001u)
04360 
04361 #define EDMA3_CCRL_EESR_E8_MASK          (0x00000100u)
04362 #define EDMA3_CCRL_EESR_E8_SHIFT         (0x00000008u)
04363 #define EDMA3_CCRL_EESR_E8_RESETVAL      (0x00000000u)
04364 
04365 /*----E8 Tokens----*/
04366 #define EDMA3_CCRL_EESR_E8_SET           (0x00000001u)
04367 
04368 #define EDMA3_CCRL_EESR_E7_MASK          (0x00000080u)
04369 #define EDMA3_CCRL_EESR_E7_SHIFT         (0x00000007u)
04370 #define EDMA3_CCRL_EESR_E7_RESETVAL      (0x00000000u)
04371 
04372 /*----E7 Tokens----*/
04373 #define EDMA3_CCRL_EESR_E7_SET           (0x00000001u)
04374 
04375 #define EDMA3_CCRL_EESR_E6_MASK          (0x00000040u)
04376 #define EDMA3_CCRL_EESR_E6_SHIFT         (0x00000006u)
04377 #define EDMA3_CCRL_EESR_E6_RESETVAL      (0x00000000u)
04378 
04379 /*----E6 Tokens----*/
04380 #define EDMA3_CCRL_EESR_E6_SET           (0x00000001u)
04381 
04382 #define EDMA3_CCRL_EESR_E5_MASK          (0x00000020u)
04383 #define EDMA3_CCRL_EESR_E5_SHIFT         (0x00000005u)
04384 #define EDMA3_CCRL_EESR_E5_RESETVAL      (0x00000000u)
04385 
04386 /*----E5 Tokens----*/
04387 #define EDMA3_CCRL_EESR_E5_SET           (0x00000001u)
04388 
04389 #define EDMA3_CCRL_EESR_E4_MASK          (0x00000010u)
04390 #define EDMA3_CCRL_EESR_E4_SHIFT         (0x00000004u)
04391 #define EDMA3_CCRL_EESR_E4_RESETVAL      (0x00000000u)
04392 
04393 /*----E4 Tokens----*/
04394 #define EDMA3_CCRL_EESR_E4_SET           (0x00000001u)
04395 
04396 #define EDMA3_CCRL_EESR_E3_MASK          (0x00000008u)
04397 #define EDMA3_CCRL_EESR_E3_SHIFT         (0x00000003u)
04398 #define EDMA3_CCRL_EESR_E3_RESETVAL      (0x00000000u)
04399 
04400 /*----E3 Tokens----*/
04401 #define EDMA3_CCRL_EESR_E3_SET           (0x00000001u)
04402 
04403 #define EDMA3_CCRL_EESR_E2_MASK          (0x00000004u)
04404 #define EDMA3_CCRL_EESR_E2_SHIFT         (0x00000002u)
04405 #define EDMA3_CCRL_EESR_E2_RESETVAL      (0x00000000u)
04406 
04407 /*----E2 Tokens----*/
04408 #define EDMA3_CCRL_EESR_E2_SET           (0x00000001u)
04409 
04410 #define EDMA3_CCRL_EESR_E1_MASK          (0x00000002u)
04411 #define EDMA3_CCRL_EESR_E1_SHIFT         (0x00000001u)
04412 #define EDMA3_CCRL_EESR_E1_RESETVAL      (0x00000000u)
04413 
04414 /*----E1 Tokens----*/
04415 #define EDMA3_CCRL_EESR_E1_SET           (0x00000001u)
04416 
04417 #define EDMA3_CCRL_EESR_E0_MASK          (0x00000001u)
04418 #define EDMA3_CCRL_EESR_E0_SHIFT         (0x00000000u)
04419 #define EDMA3_CCRL_EESR_E0_RESETVAL      (0x00000000u)
04420 
04421 /*----E0 Tokens----*/
04422 #define EDMA3_CCRL_EESR_E0_SET           (0x00000001u)
04423 
04424 #define EDMA3_CCRL_EESR_RESETVAL         (0x00000000u)
04425 
04426 /* EESRH */
04427 
04428 #define EDMA3_CCRL_EESRH_E63_MASK        (0x80000000u)
04429 #define EDMA3_CCRL_EESRH_E63_SHIFT       (0x0000001Fu)
04430 #define EDMA3_CCRL_EESRH_E63_RESETVAL    (0x00000000u)
04431 
04432 /*----E63 Tokens----*/
04433 #define EDMA3_CCRL_EESRH_E63_SET         (0x00000001u)
04434 
04435 #define EDMA3_CCRL_EESRH_E62_MASK        (0x40000000u)
04436 #define EDMA3_CCRL_EESRH_E62_SHIFT       (0x0000001Eu)
04437 #define EDMA3_CCRL_EESRH_E62_RESETVAL    (0x00000000u)
04438 
04439 /*----E62 Tokens----*/
04440 #define EDMA3_CCRL_EESRH_E62_SET         (0x00000001u)
04441 
04442 #define EDMA3_CCRL_EESRH_E61_MASK        (0x20000000u)
04443 #define EDMA3_CCRL_EESRH_E61_SHIFT       (0x0000001Du)
04444 #define EDMA3_CCRL_EESRH_E61_RESETVAL    (0x00000000u)
04445 
04446 /*----E61 Tokens----*/
04447 #define EDMA3_CCRL_EESRH_E61_SET         (0x00000001u)
04448 
04449 #define EDMA3_CCRL_EESRH_E60_MASK        (0x10000000u)
04450 #define EDMA3_CCRL_EESRH_E60_SHIFT       (0x0000001Cu)
04451 #define EDMA3_CCRL_EESRH_E60_RESETVAL    (0x00000000u)
04452 
04453 /*----E60 Tokens----*/
04454 #define EDMA3_CCRL_EESRH_E60_SET         (0x00000001u)
04455 
04456 #define EDMA3_CCRL_EESRH_E59_MASK        (0x08000000u)
04457 #define EDMA3_CCRL_EESRH_E59_SHIFT       (0x0000001Bu)
04458 #define EDMA3_CCRL_EESRH_E59_RESETVAL    (0x00000000u)
04459 
04460 /*----E59 Tokens----*/
04461 #define EDMA3_CCRL_EESRH_E59_SET         (0x00000001u)
04462 
04463 #define EDMA3_CCRL_EESRH_E58_MASK        (0x04000000u)
04464 #define EDMA3_CCRL_EESRH_E58_SHIFT       (0x0000001Au)
04465 #define EDMA3_CCRL_EESRH_E58_RESETVAL    (0x00000000u)
04466 
04467 /*----E58 Tokens----*/
04468 #define EDMA3_CCRL_EESRH_E58_SET         (0x00000001u)
04469 
04470 #define EDMA3_CCRL_EESRH_E57_MASK        (0x02000000u)
04471 #define EDMA3_CCRL_EESRH_E57_SHIFT       (0x00000019u)
04472 #define EDMA3_CCRL_EESRH_E57_RESETVAL    (0x00000000u)
04473 
04474 /*----E57 Tokens----*/
04475 #define EDMA3_CCRL_EESRH_E57_SET         (0x00000001u)
04476 
04477 #define EDMA3_CCRL_EESRH_E56_MASK        (0x01000000u)
04478 #define EDMA3_CCRL_EESRH_E56_SHIFT       (0x00000018u)
04479 #define EDMA3_CCRL_EESRH_E56_RESETVAL    (0x00000000u)
04480 
04481 /*----E56 Tokens----*/
04482 #define EDMA3_CCRL_EESRH_E56_SET         (0x00000001u)
04483 
04484 #define EDMA3_CCRL_EESRH_E55_MASK        (0x00800000u)
04485 #define EDMA3_CCRL_EESRH_E55_SHIFT       (0x00000017u)
04486 #define EDMA3_CCRL_EESRH_E55_RESETVAL    (0x00000000u)
04487 
04488 /*----E55 Tokens----*/
04489 #define EDMA3_CCRL_EESRH_E55_SET         (0x00000001u)
04490 
04491 #define EDMA3_CCRL_EESRH_E54_MASK        (0x00400000u)
04492 #define EDMA3_CCRL_EESRH_E54_SHIFT       (0x00000016u)
04493 #define EDMA3_CCRL_EESRH_E54_RESETVAL    (0x00000000u)
04494 
04495 /*----E54 Tokens----*/
04496 #define EDMA3_CCRL_EESRH_E54_SET         (0x00000001u)
04497 
04498 #define EDMA3_CCRL_EESRH_E53_MASK        (0x00200000u)
04499 #define EDMA3_CCRL_EESRH_E53_SHIFT       (0x00000015u)
04500 #define EDMA3_CCRL_EESRH_E53_RESETVAL    (0x00000000u)
04501 
04502 /*----E53 Tokens----*/
04503 #define EDMA3_CCRL_EESRH_E53_SET         (0x00000001u)
04504 
04505 #define EDMA3_CCRL_EESRH_E52_MASK        (0x00100000u)
04506 #define EDMA3_CCRL_EESRH_E52_SHIFT       (0x00000014u)
04507 #define EDMA3_CCRL_EESRH_E52_RESETVAL    (0x00000000u)
04508 
04509 /*----E52 Tokens----*/
04510 #define EDMA3_CCRL_EESRH_E52_SET         (0x00000001u)
04511 
04512 #define EDMA3_CCRL_EESRH_E51_MASK        (0x00080000u)
04513 #define EDMA3_CCRL_EESRH_E51_SHIFT       (0x00000013u)
04514 #define EDMA3_CCRL_EESRH_E51_RESETVAL    (0x00000000u)
04515 
04516 /*----E51 Tokens----*/
04517 #define EDMA3_CCRL_EESRH_E51_SET         (0x00000001u)
04518 
04519 #define EDMA3_CCRL_EESRH_E50_MASK        (0x00040000u)
04520 #define EDMA3_CCRL_EESRH_E50_SHIFT       (0x00000012u)
04521 #define EDMA3_CCRL_EESRH_E50_RESETVAL    (0x00000000u)
04522 
04523 /*----E50 Tokens----*/
04524 #define EDMA3_CCRL_EESRH_E50_SET         (0x00000001u)
04525 
04526 #define EDMA3_CCRL_EESRH_E49_MASK        (0x00020000u)
04527 #define EDMA3_CCRL_EESRH_E49_SHIFT       (0x00000011u)
04528 #define EDMA3_CCRL_EESRH_E49_RESETVAL    (0x00000000u)
04529 
04530 /*----E49 Tokens----*/
04531 #define EDMA3_CCRL_EESRH_E49_SET         (0x00000001u)
04532 
04533 #define EDMA3_CCRL_EESRH_E48_MASK        (0x00010000u)
04534 #define EDMA3_CCRL_EESRH_E48_SHIFT       (0x00000010u)
04535 #define EDMA3_CCRL_EESRH_E48_RESETVAL    (0x00000000u)
04536 
04537 /*----E48 Tokens----*/
04538 #define EDMA3_CCRL_EESRH_E48_SET         (0x00000001u)
04539 
04540 #define EDMA3_CCRL_EESRH_E47_MASK        (0x00008000u)
04541 #define EDMA3_CCRL_EESRH_E47_SHIFT       (0x0000000Fu)
04542 #define EDMA3_CCRL_EESRH_E47_RESETVAL    (0x00000000u)
04543 
04544 /*----E47 Tokens----*/
04545 #define EDMA3_CCRL_EESRH_E47_SET         (0x00000001u)
04546 
04547 #define EDMA3_CCRL_EESRH_E46_MASK        (0x00004000u)
04548 #define EDMA3_CCRL_EESRH_E46_SHIFT       (0x0000000Eu)
04549 #define EDMA3_CCRL_EESRH_E46_RESETVAL    (0x00000000u)
04550 
04551 /*----E46 Tokens----*/
04552 #define EDMA3_CCRL_EESRH_E46_SET         (0x00000001u)
04553 
04554 #define EDMA3_CCRL_EESRH_E45_MASK        (0x00002000u)
04555 #define EDMA3_CCRL_EESRH_E45_SHIFT       (0x0000000Du)
04556 #define EDMA3_CCRL_EESRH_E45_RESETVAL    (0x00000000u)
04557 
04558 /*----E45 Tokens----*/
04559 #define EDMA3_CCRL_EESRH_E45_SET         (0x00000001u)
04560 
04561 #define EDMA3_CCRL_EESRH_E44_MASK        (0x00001000u)
04562 #define EDMA3_CCRL_EESRH_E44_SHIFT       (0x0000000Cu)
04563 #define EDMA3_CCRL_EESRH_E44_RESETVAL    (0x00000000u)
04564 
04565 /*----E44 Tokens----*/
04566 #define EDMA3_CCRL_EESRH_E44_SET         (0x00000001u)
04567 
04568 #define EDMA3_CCRL_EESRH_E43_MASK        (0x00000800u)
04569 #define EDMA3_CCRL_EESRH_E43_SHIFT       (0x0000000Bu)
04570 #define EDMA3_CCRL_EESRH_E43_RESETVAL    (0x00000000u)
04571 
04572 /*----E43 Tokens----*/
04573 #define EDMA3_CCRL_EESRH_E43_SET         (0x00000001u)
04574 
04575 #define EDMA3_CCRL_EESRH_E42_MASK        (0x00000400u)
04576 #define EDMA3_CCRL_EESRH_E42_SHIFT       (0x0000000Au)
04577 #define EDMA3_CCRL_EESRH_E42_RESETVAL    (0x00000000u)
04578 
04579 /*----E42 Tokens----*/
04580 #define EDMA3_CCRL_EESRH_E42_SET         (0x00000001u)
04581 
04582 #define EDMA3_CCRL_EESRH_E41_MASK        (0x00000200u)
04583 #define EDMA3_CCRL_EESRH_E41_SHIFT       (0x00000009u)
04584 #define EDMA3_CCRL_EESRH_E41_RESETVAL    (0x00000000u)
04585 
04586 /*----E41 Tokens----*/
04587 #define EDMA3_CCRL_EESRH_E41_SET         (0x00000001u)
04588 
04589 #define EDMA3_CCRL_EESRH_E40_MASK        (0x00000100u)
04590 #define EDMA3_CCRL_EESRH_E40_SHIFT       (0x00000008u)
04591 #define EDMA3_CCRL_EESRH_E40_RESETVAL    (0x00000000u)
04592 
04593 /*----E40 Tokens----*/
04594 #define EDMA3_CCRL_EESRH_E40_SET         (0x00000001u)
04595 
04596 #define EDMA3_CCRL_EESRH_E39_MASK        (0x00000080u)
04597 #define EDMA3_CCRL_EESRH_E39_SHIFT       (0x00000007u)
04598 #define EDMA3_CCRL_EESRH_E39_RESETVAL    (0x00000000u)
04599 
04600 /*----E39 Tokens----*/
04601 #define EDMA3_CCRL_EESRH_E39_SET         (0x00000001u)
04602 
04603 #define EDMA3_CCRL_EESRH_E38_MASK        (0x00000040u)
04604 #define EDMA3_CCRL_EESRH_E38_SHIFT       (0x00000006u)
04605 #define EDMA3_CCRL_EESRH_E38_RESETVAL    (0x00000000u)
04606 
04607 /*----E38 Tokens----*/
04608 #define EDMA3_CCRL_EESRH_E38_SET         (0x00000001u)
04609 
04610 #define EDMA3_CCRL_EESRH_E37_MASK        (0x00000020u)
04611 #define EDMA3_CCRL_EESRH_E37_SHIFT       (0x00000005u)
04612 #define EDMA3_CCRL_EESRH_E37_RESETVAL    (0x00000000u)
04613 
04614 /*----E37 Tokens----*/
04615 #define EDMA3_CCRL_EESRH_E37_SET         (0x00000001u)
04616 
04617 #define EDMA3_CCRL_EESRH_E36_MASK        (0x00000010u)
04618 #define EDMA3_CCRL_EESRH_E36_SHIFT       (0x00000004u)
04619 #define EDMA3_CCRL_EESRH_E36_RESETVAL    (0x00000000u)
04620 
04621 /*----E36 Tokens----*/
04622 #define EDMA3_CCRL_EESRH_E36_SET         (0x00000001u)
04623 
04624 #define EDMA3_CCRL_EESRH_E35_MASK        (0x00000008u)
04625 #define EDMA3_CCRL_EESRH_E35_SHIFT       (0x00000003u)
04626 #define EDMA3_CCRL_EESRH_E35_RESETVAL    (0x00000000u)
04627 
04628 /*----E35 Tokens----*/
04629 #define EDMA3_CCRL_EESRH_E35_SET         (0x00000001u)
04630 
04631 #define EDMA3_CCRL_EESRH_E34_MASK        (0x00000004u)
04632 #define EDMA3_CCRL_EESRH_E34_SHIFT       (0x00000002u)
04633 #define EDMA3_CCRL_EESRH_E34_RESETVAL    (0x00000000u)
04634 
04635 /*----E34 Tokens----*/
04636 #define EDMA3_CCRL_EESRH_E34_SET         (0x00000001u)
04637 
04638 #define EDMA3_CCRL_EESRH_E33_MASK        (0x00000002u)
04639 #define EDMA3_CCRL_EESRH_E33_SHIFT       (0x00000001u)
04640 #define EDMA3_CCRL_EESRH_E33_RESETVAL    (0x00000000u)
04641 
04642 /*----E33 Tokens----*/
04643 #define EDMA3_CCRL_EESRH_E33_SET         (0x00000001u)
04644 
04645 #define EDMA3_CCRL_EESRH_E32_MASK        (0x00000001u)
04646 #define EDMA3_CCRL_EESRH_E32_SHIFT       (0x00000000u)
04647 #define EDMA3_CCRL_EESRH_E32_RESETVAL    (0x00000000u)
04648 
04649 /*----E32 Tokens----*/
04650 #define EDMA3_CCRL_EESRH_E32_SET         (0x00000001u)
04651 
04652 #define EDMA3_CCRL_EESRH_RESETVAL        (0x00000000u)
04653 
04654 /* SER */
04655 
04656 #define EDMA3_CCRL_SER_E31_MASK          (0x80000000u)
04657 #define EDMA3_CCRL_SER_E31_SHIFT         (0x0000001Fu)
04658 #define EDMA3_CCRL_SER_E31_RESETVAL      (0x00000000u)
04659 
04660 #define EDMA3_CCRL_SER_E30_MASK          (0x40000000u)
04661 #define EDMA3_CCRL_SER_E30_SHIFT         (0x0000001Eu)
04662 #define EDMA3_CCRL_SER_E30_RESETVAL      (0x00000000u)
04663 
04664 #define EDMA3_CCRL_SER_E29_MASK          (0x20000000u)
04665 #define EDMA3_CCRL_SER_E29_SHIFT         (0x0000001Du)
04666 #define EDMA3_CCRL_SER_E29_RESETVAL      (0x00000000u)
04667 
04668 #define EDMA3_CCRL_SER_E28_MASK          (0x10000000u)
04669 #define EDMA3_CCRL_SER_E28_SHIFT         (0x0000001Cu)
04670 #define EDMA3_CCRL_SER_E28_RESETVAL      (0x00000000u)
04671 
04672 #define EDMA3_CCRL_SER_E27_MASK          (0x08000000u)
04673 #define EDMA3_CCRL_SER_E27_SHIFT         (0x0000001Bu)
04674 #define EDMA3_CCRL_SER_E27_RESETVAL      (0x00000000u)
04675 
04676 #define EDMA3_CCRL_SER_E26_MASK          (0x04000000u)
04677 #define EDMA3_CCRL_SER_E26_SHIFT         (0x0000001Au)
04678 #define EDMA3_CCRL_SER_E26_RESETVAL      (0x00000000u)
04679 
04680 #define EDMA3_CCRL_SER_E25_MASK          (0x02000000u)
04681 #define EDMA3_CCRL_SER_E25_SHIFT         (0x00000019u)
04682 #define EDMA3_CCRL_SER_E25_RESETVAL      (0x00000000u)
04683 
04684 #define EDMA3_CCRL_SER_E24_MASK          (0x01000000u)
04685 #define EDMA3_CCRL_SER_E24_SHIFT         (0x00000018u)
04686 #define EDMA3_CCRL_SER_E24_RESETVAL      (0x00000000u)
04687 
04688 #define EDMA3_CCRL_SER_E23_MASK          (0x00800000u)
04689 #define EDMA3_CCRL_SER_E23_SHIFT         (0x00000017u)
04690 #define EDMA3_CCRL_SER_E23_RESETVAL      (0x00000000u)
04691 
04692 #define EDMA3_CCRL_SER_E22_MASK          (0x00400000u)
04693 #define EDMA3_CCRL_SER_E22_SHIFT         (0x00000016u)
04694 #define EDMA3_CCRL_SER_E22_RESETVAL      (0x00000000u)
04695 
04696 #define EDMA3_CCRL_SER_E21_MASK          (0x00200000u)
04697 #define EDMA3_CCRL_SER_E21_SHIFT         (0x00000015u)
04698 #define EDMA3_CCRL_SER_E21_RESETVAL      (0x00000000u)
04699 
04700 #define EDMA3_CCRL_SER_E20_MASK          (0x00100000u)
04701 #define EDMA3_CCRL_SER_E20_SHIFT         (0x00000014u)
04702 #define EDMA3_CCRL_SER_E20_RESETVAL      (0x00000000u)
04703 
04704 #define EDMA3_CCRL_SER_E19_MASK          (0x00080000u)
04705 #define EDMA3_CCRL_SER_E19_SHIFT         (0x00000013u)
04706 #define EDMA3_CCRL_SER_E19_RESETVAL      (0x00000000u)
04707 
04708 #define EDMA3_CCRL_SER_E18_MASK          (0x00040000u)
04709 #define EDMA3_CCRL_SER_E18_SHIFT         (0x00000012u)
04710 #define EDMA3_CCRL_SER_E18_RESETVAL      (0x00000000u)
04711 
04712 #define EDMA3_CCRL_SER_E17_MASK          (0x00020000u)
04713 #define EDMA3_CCRL_SER_E17_SHIFT         (0x00000011u)
04714 #define EDMA3_CCRL_SER_E17_RESETVAL      (0x00000000u)
04715 
04716 #define EDMA3_CCRL_SER_E16_MASK          (0x00010000u)
04717 #define EDMA3_CCRL_SER_E16_SHIFT         (0x00000010u)
04718 #define EDMA3_CCRL_SER_E16_RESETVAL      (0x00000000u)
04719 
04720 #define EDMA3_CCRL_SER_E15_MASK          (0x00008000u)
04721 #define EDMA3_CCRL_SER_E15_SHIFT         (0x0000000Fu)
04722 #define EDMA3_CCRL_SER_E15_RESETVAL      (0x00000000u)
04723 
04724 #define EDMA3_CCRL_SER_E14_MASK          (0x00004000u)
04725 #define EDMA3_CCRL_SER_E14_SHIFT         (0x0000000Eu)
04726 #define EDMA3_CCRL_SER_E14_RESETVAL      (0x00000000u)
04727 
04728 #define EDMA3_CCRL_SER_E13_MASK          (0x00002000u)
04729 #define EDMA3_CCRL_SER_E13_SHIFT         (0x0000000Du)
04730 #define EDMA3_CCRL_SER_E13_RESETVAL      (0x00000000u)
04731 
04732 #define EDMA3_CCRL_SER_E12_MASK          (0x00001000u)
04733 #define EDMA3_CCRL_SER_E12_SHIFT         (0x0000000Cu)
04734 #define EDMA3_CCRL_SER_E12_RESETVAL      (0x00000000u)
04735 
04736 #define EDMA3_CCRL_SER_E11_MASK          (0x00000800u)
04737 #define EDMA3_CCRL_SER_E11_SHIFT         (0x0000000Bu)
04738 #define EDMA3_CCRL_SER_E11_RESETVAL      (0x00000000u)
04739 
04740 #define EDMA3_CCRL_SER_E10_MASK          (0x00000400u)
04741 #define EDMA3_CCRL_SER_E10_SHIFT         (0x0000000Au)
04742 #define EDMA3_CCRL_SER_E10_RESETVAL      (0x00000000u)
04743 
04744 #define EDMA3_CCRL_SER_E9_MASK           (0x00000200u)
04745 #define EDMA3_CCRL_SER_E9_SHIFT          (0x00000009u)
04746 #define EDMA3_CCRL_SER_E9_RESETVAL       (0x00000000u)
04747 
04748 #define EDMA3_CCRL_SER_E8_MASK           (0x00000100u)
04749 #define EDMA3_CCRL_SER_E8_SHIFT          (0x00000008u)
04750 #define EDMA3_CCRL_SER_E8_RESETVAL       (0x00000000u)
04751 
04752 #define EDMA3_CCRL_SER_E7_MASK           (0x00000080u)
04753 #define EDMA3_CCRL_SER_E7_SHIFT          (0x00000007u)
04754 #define EDMA3_CCRL_SER_E7_RESETVAL       (0x00000000u)
04755 
04756 #define EDMA3_CCRL_SER_E6_MASK           (0x00000040u)
04757 #define EDMA3_CCRL_SER_E6_SHIFT          (0x00000006u)
04758 #define EDMA3_CCRL_SER_E6_RESETVAL       (0x00000000u)
04759 
04760 #define EDMA3_CCRL_SER_E5_MASK           (0x00000020u)
04761 #define EDMA3_CCRL_SER_E5_SHIFT          (0x00000005u)
04762 #define EDMA3_CCRL_SER_E5_RESETVAL       (0x00000000u)
04763 
04764 #define EDMA3_CCRL_SER_E4_MASK           (0x00000010u)
04765 #define EDMA3_CCRL_SER_E4_SHIFT          (0x00000004u)
04766 #define EDMA3_CCRL_SER_E4_RESETVAL       (0x00000000u)
04767 
04768 #define EDMA3_CCRL_SER_E3_MASK           (0x00000008u)
04769 #define EDMA3_CCRL_SER_E3_SHIFT          (0x00000003u)
04770 #define EDMA3_CCRL_SER_E3_RESETVAL       (0x00000000u)
04771 
04772 #define EDMA3_CCRL_SER_E2_MASK           (0x00000004u)
04773 #define EDMA3_CCRL_SER_E2_SHIFT          (0x00000002u)
04774 #define EDMA3_CCRL_SER_E2_RESETVAL       (0x00000000u)
04775 
04776 #define EDMA3_CCRL_SER_E1_MASK           (0x00000002u)
04777 #define EDMA3_CCRL_SER_E1_SHIFT          (0x00000001u)
04778 #define EDMA3_CCRL_SER_E1_RESETVAL       (0x00000000u)
04779 
04780 #define EDMA3_CCRL_SER_E0_MASK           (0x00000001u)
04781 #define EDMA3_CCRL_SER_E0_SHIFT          (0x00000000u)
04782 #define EDMA3_CCRL_SER_E0_RESETVAL       (0x00000000u)
04783 
04784 #define EDMA3_CCRL_SER_RESETVAL          (0x00000000u)
04785 
04786 /* SERH */
04787 
04788 #define EDMA3_CCRL_SERH_E63_MASK         (0x80000000u)
04789 #define EDMA3_CCRL_SERH_E63_SHIFT        (0x0000001Fu)
04790 #define EDMA3_CCRL_SERH_E63_RESETVAL     (0x00000000u)
04791 
04792 #define EDMA3_CCRL_SERH_E62_MASK         (0x40000000u)
04793 #define EDMA3_CCRL_SERH_E62_SHIFT        (0x0000001Eu)
04794 #define EDMA3_CCRL_SERH_E62_RESETVAL     (0x00000000u)
04795 
04796 #define EDMA3_CCRL_SERH_E61_MASK         (0x20000000u)
04797 #define EDMA3_CCRL_SERH_E61_SHIFT        (0x0000001Du)
04798 #define EDMA3_CCRL_SERH_E61_RESETVAL     (0x00000000u)
04799 
04800 #define EDMA3_CCRL_SERH_E60_MASK         (0x10000000u)
04801 #define EDMA3_CCRL_SERH_E60_SHIFT        (0x0000001Cu)
04802 #define EDMA3_CCRL_SERH_E60_RESETVAL     (0x00000000u)
04803 
04804 #define EDMA3_CCRL_SERH_E59_MASK         (0x08000000u)
04805 #define EDMA3_CCRL_SERH_E59_SHIFT        (0x0000001Bu)
04806 #define EDMA3_CCRL_SERH_E59_RESETVAL     (0x00000000u)
04807 
04808 #define EDMA3_CCRL_SERH_E58_MASK         (0x04000000u)
04809 #define EDMA3_CCRL_SERH_E58_SHIFT        (0x0000001Au)
04810 #define EDMA3_CCRL_SERH_E58_RESETVAL     (0x00000000u)
04811 
04812 #define EDMA3_CCRL_SERH_E57_MASK         (0x02000000u)
04813 #define EDMA3_CCRL_SERH_E57_SHIFT        (0x00000019u)
04814 #define EDMA3_CCRL_SERH_E57_RESETVAL     (0x00000000u)
04815 
04816 #define EDMA3_CCRL_SERH_E56_MASK         (0x01000000u)
04817 #define EDMA3_CCRL_SERH_E56_SHIFT        (0x00000018u)
04818 #define EDMA3_CCRL_SERH_E56_RESETVAL     (0x00000000u)
04819 
04820 #define EDMA3_CCRL_SERH_E55_MASK         (0x00800000u)
04821 #define EDMA3_CCRL_SERH_E55_SHIFT        (0x00000017u)
04822 #define EDMA3_CCRL_SERH_E55_RESETVAL     (0x00000000u)
04823 
04824 #define EDMA3_CCRL_SERH_E54_MASK         (0x00400000u)
04825 #define EDMA3_CCRL_SERH_E54_SHIFT        (0x00000016u)
04826 #define EDMA3_CCRL_SERH_E54_RESETVAL     (0x00000000u)
04827 
04828 #define EDMA3_CCRL_SERH_E53_MASK         (0x00200000u)
04829 #define EDMA3_CCRL_SERH_E53_SHIFT        (0x00000015u)
04830 #define EDMA3_CCRL_SERH_E53_RESETVAL     (0x00000000u)
04831 
04832 #define EDMA3_CCRL_SERH_E52_MASK         (0x00100000u)
04833 #define EDMA3_CCRL_SERH_E52_SHIFT        (0x00000014u)
04834 #define EDMA3_CCRL_SERH_E52_RESETVAL     (0x00000000u)
04835 
04836 #define EDMA3_CCRL_SERH_E51_MASK         (0x00080000u)
04837 #define EDMA3_CCRL_SERH_E51_SHIFT        (0x00000013u)
04838 #define EDMA3_CCRL_SERH_E51_RESETVAL     (0x00000000u)
04839 
04840 #define EDMA3_CCRL_SERH_E50_MASK         (0x00040000u)
04841 #define EDMA3_CCRL_SERH_E50_SHIFT        (0x00000012u)
04842 #define EDMA3_CCRL_SERH_E50_RESETVAL     (0x00000000u)
04843 
04844 #define EDMA3_CCRL_SERH_E49_MASK         (0x00020000u)
04845 #define EDMA3_CCRL_SERH_E49_SHIFT        (0x00000011u)
04846 #define EDMA3_CCRL_SERH_E49_RESETVAL     (0x00000000u)
04847 
04848 #define EDMA3_CCRL_SERH_E48_MASK         (0x00010000u)
04849 #define EDMA3_CCRL_SERH_E48_SHIFT        (0x00000010u)
04850 #define EDMA3_CCRL_SERH_E48_RESETVAL     (0x00000000u)
04851 
04852 #define EDMA3_CCRL_SERH_E47_MASK         (0x00008000u)
04853 #define EDMA3_CCRL_SERH_E47_SHIFT        (0x0000000Fu)
04854 #define EDMA3_CCRL_SERH_E47_RESETVAL     (0x00000000u)
04855 
04856 #define EDMA3_CCRL_SERH_E46_MASK         (0x00004000u)
04857 #define EDMA3_CCRL_SERH_E46_SHIFT        (0x0000000Eu)
04858 #define EDMA3_CCRL_SERH_E46_RESETVAL     (0x00000000u)
04859 
04860 #define EDMA3_CCRL_SERH_E45_MASK         (0x00002000u)
04861 #define EDMA3_CCRL_SERH_E45_SHIFT        (0x0000000Du)
04862 #define EDMA3_CCRL_SERH_E45_RESETVAL     (0x00000000u)
04863 
04864 #define EDMA3_CCRL_SERH_E44_MASK         (0x00001000u)
04865 #define EDMA3_CCRL_SERH_E44_SHIFT        (0x0000000Cu)
04866 #define EDMA3_CCRL_SERH_E44_RESETVAL     (0x00000000u)
04867 
04868 #define EDMA3_CCRL_SERH_E43_MASK         (0x00000800u)
04869 #define EDMA3_CCRL_SERH_E43_SHIFT        (0x0000000Bu)
04870 #define EDMA3_CCRL_SERH_E43_RESETVAL     (0x00000000u)
04871 
04872 #define EDMA3_CCRL_SERH_E42_MASK         (0x00000400u)
04873 #define EDMA3_CCRL_SERH_E42_SHIFT        (0x0000000Au)
04874 #define EDMA3_CCRL_SERH_E42_RESETVAL     (0x00000000u)
04875 
04876 #define EDMA3_CCRL_SERH_E41_MASK         (0x00000200u)
04877 #define EDMA3_CCRL_SERH_E41_SHIFT        (0x00000009u)
04878 #define EDMA3_CCRL_SERH_E41_RESETVAL     (0x00000000u)
04879 
04880 #define EDMA3_CCRL_SERH_E40_MASK         (0x00000100u)
04881 #define EDMA3_CCRL_SERH_E40_SHIFT        (0x00000008u)
04882 #define EDMA3_CCRL_SERH_E40_RESETVAL     (0x00000000u)
04883 
04884 #define EDMA3_CCRL_SERH_E39_MASK         (0x00000080u)
04885 #define EDMA3_CCRL_SERH_E39_SHIFT        (0x00000007u)
04886 #define EDMA3_CCRL_SERH_E39_RESETVAL     (0x00000000u)
04887 
04888 #define EDMA3_CCRL_SERH_E38_MASK         (0x00000040u)
04889 #define EDMA3_CCRL_SERH_E38_SHIFT        (0x00000006u)
04890 #define EDMA3_CCRL_SERH_E38_RESETVAL     (0x00000000u)
04891 
04892 #define EDMA3_CCRL_SERH_E37_MASK         (0x00000020u)
04893 #define EDMA3_CCRL_SERH_E37_SHIFT        (0x00000005u)
04894 #define EDMA3_CCRL_SERH_E37_RESETVAL     (0x00000000u)
04895 
04896 #define EDMA3_CCRL_SERH_E36_MASK         (0x00000010u)
04897 #define EDMA3_CCRL_SERH_E36_SHIFT        (0x00000004u)
04898 #define EDMA3_CCRL_SERH_E36_RESETVAL     (0x00000000u)
04899 
04900 #define EDMA3_CCRL_SERH_E35_MASK         (0x00000008u)
04901 #define EDMA3_CCRL_SERH_E35_SHIFT        (0x00000003u)
04902 #define EDMA3_CCRL_SERH_E35_RESETVAL     (0x00000000u)
04903 
04904 #define EDMA3_CCRL_SERH_E34_MASK         (0x00000004u)
04905 #define EDMA3_CCRL_SERH_E34_SHIFT        (0x00000002u)
04906 #define EDMA3_CCRL_SERH_E34_RESETVAL     (0x00000000u)
04907 
04908 #define EDMA3_CCRL_SERH_E33_MASK         (0x00000002u)
04909 #define EDMA3_CCRL_SERH_E33_SHIFT        (0x00000001u)
04910 #define EDMA3_CCRL_SERH_E33_RESETVAL     (0x00000000u)
04911 
04912 #define EDMA3_CCRL_SERH_E32_MASK         (0x00000001u)
04913 #define EDMA3_CCRL_SERH_E32_SHIFT        (0x00000000u)
04914 #define EDMA3_CCRL_SERH_E32_RESETVAL     (0x00000000u)
04915 
04916 #define EDMA3_CCRL_SERH_RESETVAL         (0x00000000u)
04917 
04918 /* SECR */
04919 
04920 #define EDMA3_CCRL_SECR_E31_MASK         (0x80000000u)
04921 #define EDMA3_CCRL_SECR_E31_SHIFT        (0x0000001Fu)
04922 #define EDMA3_CCRL_SECR_E31_RESETVAL     (0x00000000u)
04923 
04924 /*----E31 Tokens----*/
04925 #define EDMA3_CCRL_SECR_E31_CLEAR        (0x00000001u)
04926 
04927 #define EDMA3_CCRL_SECR_E30_MASK         (0x40000000u)
04928 #define EDMA3_CCRL_SECR_E30_SHIFT        (0x0000001Eu)
04929 #define EDMA3_CCRL_SECR_E30_RESETVAL     (0x00000000u)
04930 
04931 /*----E30 Tokens----*/
04932 #define EDMA3_CCRL_SECR_E30_CLEAR        (0x00000001u)
04933 
04934 #define EDMA3_CCRL_SECR_E29_MASK         (0x20000000u)
04935 #define EDMA3_CCRL_SECR_E29_SHIFT        (0x0000001Du)
04936 #define EDMA3_CCRL_SECR_E29_RESETVAL     (0x00000000u)
04937 
04938 /*----E29 Tokens----*/
04939 #define EDMA3_CCRL_SECR_E29_CLEAR        (0x00000001u)
04940 
04941 #define EDMA3_CCRL_SECR_E28_MASK         (0x10000000u)
04942 #define EDMA3_CCRL_SECR_E28_SHIFT        (0x0000001Cu)
04943 #define EDMA3_CCRL_SECR_E28_RESETVAL     (0x00000000u)
04944 
04945 /*----E28 Tokens----*/
04946 #define EDMA3_CCRL_SECR_E28_CLEAR        (0x00000001u)
04947 
04948 #define EDMA3_CCRL_SECR_E27_MASK         (0x08000000u)
04949 #define EDMA3_CCRL_SECR_E27_SHIFT        (0x0000001Bu)
04950 #define EDMA3_CCRL_SECR_E27_RESETVAL     (0x00000000u)
04951 
04952 /*----E27 Tokens----*/
04953 #define EDMA3_CCRL_SECR_E27_CLEAR        (0x00000001u)
04954 
04955 #define EDMA3_CCRL_SECR_E26_MASK         (0x04000000u)
04956 #define EDMA3_CCRL_SECR_E26_SHIFT        (0x0000001Au)
04957 #define EDMA3_CCRL_SECR_E26_RESETVAL     (0x00000000u)
04958 
04959 /*----E26 Tokens----*/
04960 #define EDMA3_CCRL_SECR_E26_CLEAR        (0x00000001u)
04961 
04962 #define EDMA3_CCRL_SECR_E25_MASK         (0x02000000u)
04963 #define EDMA3_CCRL_SECR_E25_SHIFT        (0x00000019u)
04964 #define EDMA3_CCRL_SECR_E25_RESETVAL     (0x00000000u)
04965 
04966 /*----E25 Tokens----*/
04967 #define EDMA3_CCRL_SECR_E25_CLEAR        (0x00000001u)
04968 
04969 #define EDMA3_CCRL_SECR_E24_MASK         (0x01000000u)
04970 #define EDMA3_CCRL_SECR_E24_SHIFT        (0x00000018u)
04971 #define EDMA3_CCRL_SECR_E24_RESETVAL     (0x00000000u)
04972 
04973 /*----E24 Tokens----*/
04974 #define EDMA3_CCRL_SECR_E24_CLEAR        (0x00000001u)
04975 
04976 #define EDMA3_CCRL_SECR_E23_MASK         (0x00800000u)
04977 #define EDMA3_CCRL_SECR_E23_SHIFT        (0x00000017u)
04978 #define EDMA3_CCRL_SECR_E23_RESETVAL     (0x00000000u)
04979 
04980 /*----E23 Tokens----*/
04981 #define EDMA3_CCRL_SECR_E23_CLEAR        (0x00000001u)
04982 
04983 #define EDMA3_CCRL_SECR_E22_MASK         (0x00400000u)
04984 #define EDMA3_CCRL_SECR_E22_SHIFT        (0x00000016u)
04985 #define EDMA3_CCRL_SECR_E22_RESETVAL     (0x00000000u)
04986 
04987 /*----E22 Tokens----*/
04988 #define EDMA3_CCRL_SECR_E22_CLEAR        (0x00000001u)
04989 
04990 #define EDMA3_CCRL_SECR_E21_MASK         (0x00200000u)
04991 #define EDMA3_CCRL_SECR_E21_SHIFT        (0x00000015u)
04992 #define EDMA3_CCRL_SECR_E21_RESETVAL     (0x00000000u)
04993 
04994 /*----E21 Tokens----*/
04995 #define EDMA3_CCRL_SECR_E21_CLEAR        (0x00000001u)
04996 
04997 #define EDMA3_CCRL_SECR_E20_MASK         (0x00100000u)
04998 #define EDMA3_CCRL_SECR_E20_SHIFT        (0x00000014u)
04999 #define EDMA3_CCRL_SECR_E20_RESETVAL     (0x00000000u)
05000 
05001 /*----E20 Tokens----*/
05002 #define EDMA3_CCRL_SECR_E20_CLEAR        (0x00000001u)
05003 
05004 #define EDMA3_CCRL_SECR_E19_MASK         (0x00080000u)
05005 #define EDMA3_CCRL_SECR_E19_SHIFT        (0x00000013u)
05006 #define EDMA3_CCRL_SECR_E19_RESETVAL     (0x00000000u)
05007 
05008 /*----E19 Tokens----*/
05009 #define EDMA3_CCRL_SECR_E19_CLEAR        (0x00000001u)
05010 
05011 #define EDMA3_CCRL_SECR_E18_MASK         (0x00040000u)
05012 #define EDMA3_CCRL_SECR_E18_SHIFT        (0x00000012u)
05013 #define EDMA3_CCRL_SECR_E18_RESETVAL     (0x00000000u)
05014 
05015 /*----E18 Tokens----*/
05016 #define EDMA3_CCRL_SECR_E18_CLEAR        (0x00000001u)
05017 
05018 #define EDMA3_CCRL_SECR_E17_MASK         (0x00020000u)
05019 #define EDMA3_CCRL_SECR_E17_SHIFT        (0x00000011u)
05020 #define EDMA3_CCRL_SECR_E17_RESETVAL     (0x00000000u)
05021 
05022 /*----E17 Tokens----*/
05023 #define EDMA3_CCRL_SECR_E17_CLEAR        (0x00000001u)
05024 
05025 #define EDMA3_CCRL_SECR_E16_MASK         (0x00010000u)
05026 #define EDMA3_CCRL_SECR_E16_SHIFT        (0x00000010u)
05027 #define EDMA3_CCRL_SECR_E16_RESETVAL     (0x00000000u)
05028 
05029 /*----E16 Tokens----*/
05030 #define EDMA3_CCRL_SECR_E16_CLEAR        (0x00000001u)
05031 
05032 #define EDMA3_CCRL_SECR_E15_MASK         (0x00008000u)
05033 #define EDMA3_CCRL_SECR_E15_SHIFT        (0x0000000Fu)
05034 #define EDMA3_CCRL_SECR_E15_RESETVAL     (0x00000000u)
05035 
05036 /*----E15 Tokens----*/
05037 #define EDMA3_CCRL_SECR_E15_CLEAR        (0x00000001u)
05038 
05039 #define EDMA3_CCRL_SECR_E14_MASK         (0x00004000u)
05040 #define EDMA3_CCRL_SECR_E14_SHIFT        (0x0000000Eu)
05041 #define EDMA3_CCRL_SECR_E14_RESETVAL     (0x00000000u)
05042 
05043 /*----E14 Tokens----*/
05044 #define EDMA3_CCRL_SECR_E14_CLEAR        (0x00000001u)
05045 
05046 #define EDMA3_CCRL_SECR_E13_MASK         (0x00002000u)
05047 #define EDMA3_CCRL_SECR_E13_SHIFT        (0x0000000Du)
05048 #define EDMA3_CCRL_SECR_E13_RESETVAL     (0x00000000u)
05049 
05050 /*----E13 Tokens----*/
05051 #define EDMA3_CCRL_SECR_E13_CLEAR        (0x00000001u)
05052 
05053 #define EDMA3_CCRL_SECR_E12_MASK         (0x00001000u)
05054 #define EDMA3_CCRL_SECR_E12_SHIFT        (0x0000000Cu)
05055 #define EDMA3_CCRL_SECR_E12_RESETVAL     (0x00000000u)
05056 
05057 /*----E12 Tokens----*/
05058 #define EDMA3_CCRL_SECR_E12_CLEAR        (0x00000001u)
05059 
05060 #define EDMA3_CCRL_SECR_E11_MASK         (0x00000800u)
05061 #define EDMA3_CCRL_SECR_E11_SHIFT        (0x0000000Bu)
05062 #define EDMA3_CCRL_SECR_E11_RESETVAL     (0x00000000u)
05063 
05064 /*----E11 Tokens----*/
05065 #define EDMA3_CCRL_SECR_E11_CLEAR        (0x00000001u)
05066 
05067 #define EDMA3_CCRL_SECR_E10_MASK         (0x00000400u)
05068 #define EDMA3_CCRL_SECR_E10_SHIFT        (0x0000000Au)
05069 #define EDMA3_CCRL_SECR_E10_RESETVAL     (0x00000000u)
05070 
05071 /*----E10 Tokens----*/
05072 #define EDMA3_CCRL_SECR_E10_CLEAR        (0x00000001u)
05073 
05074 #define EDMA3_CCRL_SECR_E9_MASK          (0x00000200u)
05075 #define EDMA3_CCRL_SECR_E9_SHIFT         (0x00000009u)
05076 #define EDMA3_CCRL_SECR_E9_RESETVAL      (0x00000000u)
05077 
05078 /*----E9 Tokens----*/
05079 #define EDMA3_CCRL_SECR_E9_CLEAR         (0x00000001u)
05080 
05081 #define EDMA3_CCRL_SECR_E8_MASK          (0x00000100u)
05082 #define EDMA3_CCRL_SECR_E8_SHIFT         (0x00000008u)
05083 #define EDMA3_CCRL_SECR_E8_RESETVAL      (0x00000000u)
05084 
05085 /*----E8 Tokens----*/
05086 #define EDMA3_CCRL_SECR_E8_CLEAR         (0x00000001u)
05087 
05088 #define EDMA3_CCRL_SECR_E7_MASK          (0x00000080u)
05089 #define EDMA3_CCRL_SECR_E7_SHIFT         (0x00000007u)
05090 #define EDMA3_CCRL_SECR_E7_RESETVAL      (0x00000000u)
05091 
05092 /*----E7 Tokens----*/
05093 #define EDMA3_CCRL_SECR_E7_CLEAR         (0x00000001u)
05094 
05095 #define EDMA3_CCRL_SECR_E6_MASK          (0x00000040u)
05096 #define EDMA3_CCRL_SECR_E6_SHIFT         (0x00000006u)
05097 #define EDMA3_CCRL_SECR_E6_RESETVAL      (0x00000000u)
05098 
05099 /*----E6 Tokens----*/
05100 #define EDMA3_CCRL_SECR_E6_CLEAR         (0x00000001u)
05101 
05102 #define EDMA3_CCRL_SECR_E5_MASK          (0x00000020u)
05103 #define EDMA3_CCRL_SECR_E5_SHIFT         (0x00000005u)
05104 #define EDMA3_CCRL_SECR_E5_RESETVAL      (0x00000000u)
05105 
05106 /*----E5 Tokens----*/
05107 #define EDMA3_CCRL_SECR_E5_CLEAR         (0x00000001u)
05108 
05109 #define EDMA3_CCRL_SECR_E4_MASK          (0x00000010u)
05110 #define EDMA3_CCRL_SECR_E4_SHIFT         (0x00000004u)
05111 #define EDMA3_CCRL_SECR_E4_RESETVAL      (0x00000000u)
05112 
05113 /*----E4 Tokens----*/
05114 #define EDMA3_CCRL_SECR_E4_CLEAR         (0x00000001u)
05115 
05116 #define EDMA3_CCRL_SECR_E3_MASK          (0x00000008u)
05117 #define EDMA3_CCRL_SECR_E3_SHIFT         (0x00000003u)
05118 #define EDMA3_CCRL_SECR_E3_RESETVAL      (0x00000000u)
05119 
05120 /*----E3 Tokens----*/
05121 #define EDMA3_CCRL_SECR_E3_CLEAR         (0x00000001u)
05122 
05123 #define EDMA3_CCRL_SECR_E2_MASK          (0x00000004u)
05124 #define EDMA3_CCRL_SECR_E2_SHIFT         (0x00000002u)
05125 #define EDMA3_CCRL_SECR_E2_RESETVAL      (0x00000000u)
05126 
05127 /*----E2 Tokens----*/
05128 #define EDMA3_CCRL_SECR_E2_CLEAR         (0x00000001u)
05129 
05130 #define EDMA3_CCRL_SECR_E1_MASK          (0x00000002u)
05131 #define EDMA3_CCRL_SECR_E1_SHIFT         (0x00000001u)
05132 #define EDMA3_CCRL_SECR_E1_RESETVAL      (0x00000000u)
05133 
05134 /*----E1 Tokens----*/
05135 #define EDMA3_CCRL_SECR_E1_CLEAR         (0x00000001u)
05136 
05137 #define EDMA3_CCRL_SECR_E0_MASK          (0x00000001u)
05138 #define EDMA3_CCRL_SECR_E0_SHIFT         (0x00000000u)
05139 #define EDMA3_CCRL_SECR_E0_RESETVAL      (0x00000000u)
05140 
05141 /*----E0 Tokens----*/
05142 #define EDMA3_CCRL_SECR_E0_CLEAR         (0x00000001u)
05143 
05144 #define EDMA3_CCRL_SECR_RESETVAL         (0x00000000u)
05145 
05146 /* SECRH */
05147 
05148 #define EDMA3_CCRL_SECRH_E63_MASK        (0x80000000u)
05149 #define EDMA3_CCRL_SECRH_E63_SHIFT       (0x0000001Fu)
05150 #define EDMA3_CCRL_SECRH_E63_RESETVAL    (0x00000000u)
05151 
05152 /*----E63 Tokens----*/
05153 #define EDMA3_CCRL_SECRH_E63_CLEAR       (0x00000001u)
05154 
05155 #define EDMA3_CCRL_SECRH_E62_MASK        (0x40000000u)
05156 #define EDMA3_CCRL_SECRH_E62_SHIFT       (0x0000001Eu)
05157 #define EDMA3_CCRL_SECRH_E62_RESETVAL    (0x00000000u)
05158 
05159 /*----E62 Tokens----*/
05160 #define EDMA3_CCRL_SECRH_E62_CLEAR       (0x00000001u)
05161 
05162 #define EDMA3_CCRL_SECRH_E61_MASK        (0x20000000u)
05163 #define EDMA3_CCRL_SECRH_E61_SHIFT       (0x0000001Du)
05164 #define EDMA3_CCRL_SECRH_E61_RESETVAL    (0x00000000u)
05165 
05166 /*----E61 Tokens----*/
05167 #define EDMA3_CCRL_SECRH_E61_CLEAR       (0x00000001u)
05168 
05169 #define EDMA3_CCRL_SECRH_E60_MASK        (0x10000000u)
05170 #define EDMA3_CCRL_SECRH_E60_SHIFT       (0x0000001Cu)
05171 #define EDMA3_CCRL_SECRH_E60_RESETVAL    (0x00000000u)
05172 
05173 /*----E60 Tokens----*/
05174 #define EDMA3_CCRL_SECRH_E60_CLEAR       (0x00000001u)
05175 
05176 #define EDMA3_CCRL_SECRH_E59_MASK        (0x08000000u)
05177 #define EDMA3_CCRL_SECRH_E59_SHIFT       (0x0000001Bu)
05178 #define EDMA3_CCRL_SECRH_E59_RESETVAL    (0x00000000u)
05179 
05180 /*----E59 Tokens----*/
05181 #define EDMA3_CCRL_SECRH_E59_CLEAR       (0x00000001u)
05182 
05183 #define EDMA3_CCRL_SECRH_E58_MASK        (0x04000000u)
05184 #define EDMA3_CCRL_SECRH_E58_SHIFT       (0x0000001Au)
05185 #define EDMA3_CCRL_SECRH_E58_RESETVAL    (0x00000000u)
05186 
05187 /*----E58 Tokens----*/
05188 #define EDMA3_CCRL_SECRH_E58_CLEAR       (0x00000001u)
05189 
05190 #define EDMA3_CCRL_SECRH_E57_MASK        (0x02000000u)
05191 #define EDMA3_CCRL_SECRH_E57_SHIFT       (0x00000019u)
05192 #define EDMA3_CCRL_SECRH_E57_RESETVAL    (0x00000000u)
05193 
05194 /*----E57 Tokens----*/
05195 #define EDMA3_CCRL_SECRH_E57_CLEAR       (0x00000001u)
05196 
05197 #define EDMA3_CCRL_SECRH_E56_MASK        (0x01000000u)
05198 #define EDMA3_CCRL_SECRH_E56_SHIFT       (0x00000018u)
05199 #define EDMA3_CCRL_SECRH_E56_RESETVAL    (0x00000000u)
05200 
05201 /*----E56 Tokens----*/
05202 #define EDMA3_CCRL_SECRH_E56_CLEAR       (0x00000001u)
05203 
05204 #define EDMA3_CCRL_SECRH_E55_MASK        (0x00800000u)
05205 #define EDMA3_CCRL_SECRH_E55_SHIFT       (0x00000017u)
05206 #define EDMA3_CCRL_SECRH_E55_RESETVAL    (0x00000000u)
05207 
05208 /*----E55 Tokens----*/
05209 #define EDMA3_CCRL_SECRH_E55_CLEAR       (0x00000001u)
05210 
05211 #define EDMA3_CCRL_SECRH_E54_MASK        (0x00400000u)
05212 #define EDMA3_CCRL_SECRH_E54_SHIFT       (0x00000016u)
05213 #define EDMA3_CCRL_SECRH_E54_RESETVAL    (0x00000000u)
05214 
05215 /*----E54 Tokens----*/
05216 #define EDMA3_CCRL_SECRH_E54_CLEAR       (0x00000001u)
05217 
05218 #define EDMA3_CCRL_SECRH_E53_MASK        (0x00200000u)
05219 #define EDMA3_CCRL_SECRH_E53_SHIFT       (0x00000015u)
05220 #define EDMA3_CCRL_SECRH_E53_RESETVAL    (0x00000000u)
05221 
05222 /*----E53 Tokens----*/
05223 #define EDMA3_CCRL_SECRH_E53_CLEAR       (0x00000001u)
05224 
05225 #define EDMA3_CCRL_SECRH_E52_MASK        (0x00100000u)
05226 #define EDMA3_CCRL_SECRH_E52_SHIFT       (0x00000014u)
05227 #define EDMA3_CCRL_SECRH_E52_RESETVAL    (0x00000000u)
05228 
05229 /*----E52 Tokens----*/
05230 #define EDMA3_CCRL_SECRH_E52_CLEAR       (0x00000001u)
05231 
05232 #define EDMA3_CCRL_SECRH_E51_MASK        (0x00080000u)
05233 #define EDMA3_CCRL_SECRH_E51_SHIFT       (0x00000013u)
05234 #define EDMA3_CCRL_SECRH_E51_RESETVAL    (0x00000000u)
05235 
05236 /*----E51 Tokens----*/
05237 #define EDMA3_CCRL_SECRH_E51_CLEAR       (0x00000001u)
05238 
05239 #define EDMA3_CCRL_SECRH_E50_MASK        (0x00040000u)
05240 #define EDMA3_CCRL_SECRH_E50_SHIFT       (0x00000012u)
05241 #define EDMA3_CCRL_SECRH_E50_RESETVAL    (0x00000000u)
05242 
05243 /*----E50 Tokens----*/
05244 #define EDMA3_CCRL_SECRH_E50_CLEAR       (0x00000001u)
05245 
05246 #define EDMA3_CCRL_SECRH_E49_MASK        (0x00020000u)
05247 #define EDMA3_CCRL_SECRH_E49_SHIFT       (0x00000011u)
05248 #define EDMA3_CCRL_SECRH_E49_RESETVAL    (0x00000000u)
05249 
05250 /*----E49 Tokens----*/
05251 #define EDMA3_CCRL_SECRH_E49_CLEAR       (0x00000001u)
05252 
05253 #define EDMA3_CCRL_SECRH_E48_MASK        (0x00010000u)
05254 #define EDMA3_CCRL_SECRH_E48_SHIFT       (0x00000010u)
05255 #define EDMA3_CCRL_SECRH_E48_RESETVAL    (0x00000000u)
05256 
05257 /*----E48 Tokens----*/
05258 #define EDMA3_CCRL_SECRH_E48_CLEAR       (0x00000001u)
05259 
05260 #define EDMA3_CCRL_SECRH_E47_MASK        (0x00008000u)
05261 #define EDMA3_CCRL_SECRH_E47_SHIFT       (0x0000000Fu)
05262 #define EDMA3_CCRL_SECRH_E47_RESETVAL    (0x00000000u)
05263 
05264 /*----E47 Tokens----*/
05265 #define EDMA3_CCRL_SECRH_E47_CLEAR       (0x00000001u)
05266 
05267 #define EDMA3_CCRL_SECRH_E46_MASK        (0x00004000u)
05268 #define EDMA3_CCRL_SECRH_E46_SHIFT       (0x0000000Eu)
05269 #define EDMA3_CCRL_SECRH_E46_RESETVAL    (0x00000000u)
05270 
05271 /*----E46 Tokens----*/
05272 #define EDMA3_CCRL_SECRH_E46_CLEAR       (0x00000001u)
05273 
05274 #define EDMA3_CCRL_SECRH_E45_MASK        (0x00002000u)
05275 #define EDMA3_CCRL_SECRH_E45_SHIFT       (0x0000000Du)
05276 #define EDMA3_CCRL_SECRH_E45_RESETVAL    (0x00000000u)
05277 
05278 /*----E45 Tokens----*/
05279 #define EDMA3_CCRL_SECRH_E45_CLEAR       (0x00000001u)
05280 
05281 #define EDMA3_CCRL_SECRH_E44_MASK        (0x00001000u)
05282 #define EDMA3_CCRL_SECRH_E44_SHIFT       (0x0000000Cu)
05283 #define EDMA3_CCRL_SECRH_E44_RESETVAL    (0x00000000u)
05284 
05285 /*----E44 Tokens----*/
05286 #define EDMA3_CCRL_SECRH_E44_CLEAR       (0x00000001u)
05287 
05288 #define EDMA3_CCRL_SECRH_E43_MASK        (0x00000800u)
05289 #define EDMA3_CCRL_SECRH_E43_SHIFT       (0x0000000Bu)
05290 #define EDMA3_CCRL_SECRH_E43_RESETVAL    (0x00000000u)
05291 
05292 /*----E43 Tokens----*/
05293 #define EDMA3_CCRL_SECRH_E43_CLEAR       (0x00000001u)
05294 
05295 #define EDMA3_CCRL_SECRH_E42_MASK        (0x00000400u)
05296 #define EDMA3_CCRL_SECRH_E42_SHIFT       (0x0000000Au)
05297 #define EDMA3_CCRL_SECRH_E42_RESETVAL    (0x00000000u)
05298 
05299 /*----E42 Tokens----*/
05300 #define EDMA3_CCRL_SECRH_E42_CLEAR       (0x00000001u)
05301 
05302 #define EDMA3_CCRL_SECRH_E41_MASK        (0x00000200u)
05303 #define EDMA3_CCRL_SECRH_E41_SHIFT       (0x00000009u)
05304 #define EDMA3_CCRL_SECRH_E41_RESETVAL    (0x00000000u)
05305 
05306 /*----E41 Tokens----*/
05307 #define EDMA3_CCRL_SECRH_E41_CLEAR       (0x00000001u)
05308 
05309 #define EDMA3_CCRL_SECRH_E40_MASK        (0x00000100u)
05310 #define EDMA3_CCRL_SECRH_E40_SHIFT       (0x00000008u)
05311 #define EDMA3_CCRL_SECRH_E40_RESETVAL    (0x00000000u)
05312 
05313 /*----E40 Tokens----*/
05314 #define EDMA3_CCRL_SECRH_E40_CLEAR       (0x00000001u)
05315 
05316 #define EDMA3_CCRL_SECRH_E39_MASK        (0x00000080u)
05317 #define EDMA3_CCRL_SECRH_E39_SHIFT       (0x00000007u)
05318 #define EDMA3_CCRL_SECRH_E39_RESETVAL    (0x00000000u)
05319 
05320 /*----E39 Tokens----*/
05321 #define EDMA3_CCRL_SECRH_E39_CLEAR       (0x00000001u)
05322 
05323 #define EDMA3_CCRL_SECRH_E38_MASK        (0x00000040u)
05324 #define EDMA3_CCRL_SECRH_E38_SHIFT       (0x00000006u)
05325 #define EDMA3_CCRL_SECRH_E38_RESETVAL    (0x00000000u)
05326 
05327 /*----E38 Tokens----*/
05328 #define EDMA3_CCRL_SECRH_E38_CLEAR       (0x00000001u)
05329 
05330 #define EDMA3_CCRL_SECRH_E37_MASK        (0x00000020u)
05331 #define EDMA3_CCRL_SECRH_E37_SHIFT       (0x00000005u)
05332 #define EDMA3_CCRL_SECRH_E37_RESETVAL    (0x00000000u)
05333 
05334 /*----E37 Tokens----*/
05335 #define EDMA3_CCRL_SECRH_E37_CLEAR       (0x00000001u)
05336 
05337 #define EDMA3_CCRL_SECRH_E36_MASK        (0x00000010u)
05338 #define EDMA3_CCRL_SECRH_E36_SHIFT       (0x00000004u)
05339 #define EDMA3_CCRL_SECRH_E36_RESETVAL    (0x00000000u)
05340 
05341 /*----E36 Tokens----*/
05342 #define EDMA3_CCRL_SECRH_E36_CLEAR       (0x00000001u)
05343 
05344 #define EDMA3_CCRL_SECRH_E35_MASK        (0x00000008u)
05345 #define EDMA3_CCRL_SECRH_E35_SHIFT       (0x00000003u)
05346 #define EDMA3_CCRL_SECRH_E35_RESETVAL    (0x00000000u)
05347 
05348 /*----E35 Tokens----*/
05349 #define EDMA3_CCRL_SECRH_E35_CLEAR       (0x00000001u)
05350 
05351 #define EDMA3_CCRL_SECRH_E34_MASK        (0x00000004u)
05352 #define EDMA3_CCRL_SECRH_E34_SHIFT       (0x00000002u)
05353 #define EDMA3_CCRL_SECRH_E34_RESETVAL    (0x00000000u)
05354 
05355 /*----E34 Tokens----*/
05356 #define EDMA3_CCRL_SECRH_E34_CLEAR       (0x00000001u)
05357 
05358 #define EDMA3_CCRL_SECRH_E33_MASK        (0x00000002u)
05359 #define EDMA3_CCRL_SECRH_E33_SHIFT       (0x00000001u)
05360 #define EDMA3_CCRL_SECRH_E33_RESETVAL    (0x00000000u)
05361 
05362 /*----E33 Tokens----*/
05363 #define EDMA3_CCRL_SECRH_E33_CLEAR       (0x00000001u)
05364 
05365 #define EDMA3_CCRL_SECRH_E32_MASK        (0x00000001u)
05366 #define EDMA3_CCRL_SECRH_E32_SHIFT       (0x00000000u)
05367 #define EDMA3_CCRL_SECRH_E32_RESETVAL    (0x00000000u)
05368 
05369 /*----E32 Tokens----*/
05370 #define EDMA3_CCRL_SECRH_E32_CLEAR       (0x00000001u)
05371 
05372 #define EDMA3_CCRL_SECRH_RESETVAL        (0x00000000u)
05373 
05374 /* IER */
05375 
05376 #define EDMA3_CCRL_IER_I31_MASK          (0x80000000u)
05377 #define EDMA3_CCRL_IER_I31_SHIFT         (0x0000001Fu)
05378 #define EDMA3_CCRL_IER_I31_RESETVAL      (0x00000000u)
05379 
05380 #define EDMA3_CCRL_IER_I30_MASK          (0x40000000u)
05381 #define EDMA3_CCRL_IER_I30_SHIFT         (0x0000001Eu)
05382 #define EDMA3_CCRL_IER_I30_RESETVAL      (0x00000000u)
05383 
05384 #define EDMA3_CCRL_IER_I29_MASK          (0x20000000u)
05385 #define EDMA3_CCRL_IER_I29_SHIFT         (0x0000001Du)
05386 #define EDMA3_CCRL_IER_I29_RESETVAL      (0x00000000u)
05387 
05388 #define EDMA3_CCRL_IER_I28_MASK          (0x10000000u)
05389 #define EDMA3_CCRL_IER_I28_SHIFT         (0x0000001Cu)
05390 #define EDMA3_CCRL_IER_I28_RESETVAL      (0x00000000u)
05391 
05392 #define EDMA3_CCRL_IER_I27_MASK          (0x08000000u)
05393 #define EDMA3_CCRL_IER_I27_SHIFT         (0x0000001Bu)
05394 #define EDMA3_CCRL_IER_I27_RESETVAL      (0x00000000u)
05395 
05396 #define EDMA3_CCRL_IER_I26_MASK          (0x04000000u)
05397 #define EDMA3_CCRL_IER_I26_SHIFT         (0x0000001Au)
05398 #define EDMA3_CCRL_IER_I26_RESETVAL      (0x00000000u)
05399 
05400 #define EDMA3_CCRL_IER_I25_MASK          (0x02000000u)
05401 #define EDMA3_CCRL_IER_I25_SHIFT         (0x00000019u)
05402 #define EDMA3_CCRL_IER_I25_RESETVAL      (0x00000000u)
05403 
05404 #define EDMA3_CCRL_IER_I24_MASK          (0x01000000u)
05405 #define EDMA3_CCRL_IER_I24_SHIFT         (0x00000018u)
05406 #define EDMA3_CCRL_IER_I24_RESETVAL      (0x00000000u)
05407 
05408 #define EDMA3_CCRL_IER_I23_MASK          (0x00800000u)
05409 #define EDMA3_CCRL_IER_I23_SHIFT         (0x00000017u)
05410 #define EDMA3_CCRL_IER_I23_RESETVAL      (0x00000000u)
05411 
05412 #define EDMA3_CCRL_IER_I22_MASK          (0x00400000u)
05413 #define EDMA3_CCRL_IER_I22_SHIFT         (0x00000016u)
05414 #define EDMA3_CCRL_IER_I22_RESETVAL      (0x00000000u)
05415 
05416 #define EDMA3_CCRL_IER_I21_MASK          (0x00200000u)
05417 #define EDMA3_CCRL_IER_I21_SHIFT         (0x00000015u)
05418 #define EDMA3_CCRL_IER_I21_RESETVAL      (0x00000000u)
05419 
05420 #define EDMA3_CCRL_IER_I20_MASK          (0x00100000u)
05421 #define EDMA3_CCRL_IER_I20_SHIFT         (0x00000014u)
05422 #define EDMA3_CCRL_IER_I20_RESETVAL      (0x00000000u)
05423 
05424 #define EDMA3_CCRL_IER_I19_MASK          (0x00080000u)
05425 #define EDMA3_CCRL_IER_I19_SHIFT         (0x00000013u)
05426 #define EDMA3_CCRL_IER_I19_RESETVAL      (0x00000000u)
05427 
05428 #define EDMA3_CCRL_IER_I18_MASK          (0x00040000u)
05429 #define EDMA3_CCRL_IER_I18_SHIFT         (0x00000012u)
05430 #define EDMA3_CCRL_IER_I18_RESETVAL      (0x00000000u)
05431 
05432 #define EDMA3_CCRL_IER_I17_MASK          (0x00020000u)
05433 #define EDMA3_CCRL_IER_I17_SHIFT         (0x00000011u)
05434 #define EDMA3_CCRL_IER_I17_RESETVAL      (0x00000000u)
05435 
05436 #define EDMA3_CCRL_IER_I16_MASK          (0x00010000u)
05437 #define EDMA3_CCRL_IER_I16_SHIFT         (0x00000010u)
05438 #define EDMA3_CCRL_IER_I16_RESETVAL      (0x00000000u)
05439 
05440 #define EDMA3_CCRL_IER_I15_MASK          (0x00008000u)
05441 #define EDMA3_CCRL_IER_I15_SHIFT         (0x0000000Fu)
05442 #define EDMA3_CCRL_IER_I15_RESETVAL      (0x00000000u)
05443 
05444 #define EDMA3_CCRL_IER_I14_MASK          (0x00004000u)
05445 #define EDMA3_CCRL_IER_I14_SHIFT         (0x0000000Eu)
05446 #define EDMA3_CCRL_IER_I14_RESETVAL      (0x00000000u)
05447 
05448 #define EDMA3_CCRL_IER_I13_MASK          (0x00002000u)
05449 #define EDMA3_CCRL_IER_I13_SHIFT         (0x0000000Du)
05450 #define EDMA3_CCRL_IER_I13_RESETVAL      (0x00000000u)
05451 
05452 #define EDMA3_CCRL_IER_I12_MASK          (0x00001000u)
05453 #define EDMA3_CCRL_IER_I12_SHIFT         (0x0000000Cu)
05454 #define EDMA3_CCRL_IER_I12_RESETVAL      (0x00000000u)
05455 
05456 #define EDMA3_CCRL_IER_I11_MASK          (0x00000800u)
05457 #define EDMA3_CCRL_IER_I11_SHIFT         (0x0000000Bu)
05458 #define EDMA3_CCRL_IER_I11_RESETVAL      (0x00000000u)
05459 
05460 #define EDMA3_CCRL_IER_I10_MASK          (0x00000400u)
05461 #define EDMA3_CCRL_IER_I10_SHIFT         (0x0000000Au)
05462 #define EDMA3_CCRL_IER_I10_RESETVAL      (0x00000000u)
05463 
05464 #define EDMA3_CCRL_IER_I9_MASK           (0x00000200u)
05465 #define EDMA3_CCRL_IER_I9_SHIFT          (0x00000009u)
05466 #define EDMA3_CCRL_IER_I9_RESETVAL       (0x00000000u)
05467 
05468 #define EDMA3_CCRL_IER_I8_MASK           (0x00000100u)
05469 #define EDMA3_CCRL_IER_I8_SHIFT          (0x00000008u)
05470 #define EDMA3_CCRL_IER_I8_RESETVAL       (0x00000000u)
05471 
05472 #define EDMA3_CCRL_IER_I7_MASK           (0x00000080u)
05473 #define EDMA3_CCRL_IER_I7_SHIFT          (0x00000007u)
05474 #define EDMA3_CCRL_IER_I7_RESETVAL       (0x00000000u)
05475 
05476 #define EDMA3_CCRL_IER_I6_MASK           (0x00000040u)
05477 #define EDMA3_CCRL_IER_I6_SHIFT          (0x00000006u)
05478 #define EDMA3_CCRL_IER_I6_RESETVAL       (0x00000000u)
05479 
05480 #define EDMA3_CCRL_IER_I5_MASK           (0x00000020u)
05481 #define EDMA3_CCRL_IER_I5_SHIFT          (0x00000005u)
05482 #define EDMA3_CCRL_IER_I5_RESETVAL       (0x00000000u)
05483 
05484 #define EDMA3_CCRL_IER_I4_MASK           (0x00000010u)
05485 #define EDMA3_CCRL_IER_I4_SHIFT          (0x00000004u)
05486 #define EDMA3_CCRL_IER_I4_RESETVAL       (0x00000000u)
05487 
05488 #define EDMA3_CCRL_IER_I3_MASK           (0x00000008u)
05489 #define EDMA3_CCRL_IER_I3_SHIFT          (0x00000003u)
05490 #define EDMA3_CCRL_IER_I3_RESETVAL       (0x00000000u)
05491 
05492 #define EDMA3_CCRL_IER_I2_MASK           (0x00000004u)
05493 #define EDMA3_CCRL_IER_I2_SHIFT          (0x00000002u)
05494 #define EDMA3_CCRL_IER_I2_RESETVAL       (0x00000000u)
05495 
05496 #define EDMA3_CCRL_IER_I1_MASK           (0x00000002u)
05497 #define EDMA3_CCRL_IER_I1_SHIFT          (0x00000001u)
05498 #define EDMA3_CCRL_IER_I1_RESETVAL       (0x00000000u)
05499 
05500 #define EDMA3_CCRL_IER_I0_MASK           (0x00000001u)
05501 #define EDMA3_CCRL_IER_I0_SHIFT          (0x00000000u)
05502 #define EDMA3_CCRL_IER_I0_RESETVAL       (0x00000000u)
05503 
05504 #define EDMA3_CCRL_IER_RESETVAL          (0x00000000u)
05505 
05506 /* IERH */
05507 
05508 #define EDMA3_CCRL_IERH_I63_MASK         (0x80000000u)
05509 #define EDMA3_CCRL_IERH_I63_SHIFT        (0x0000001Fu)
05510 #define EDMA3_CCRL_IERH_I63_RESETVAL     (0x00000000u)
05511 
05512 #define EDMA3_CCRL_IERH_I62_MASK         (0x40000000u)
05513 #define EDMA3_CCRL_IERH_I62_SHIFT        (0x0000001Eu)
05514 #define EDMA3_CCRL_IERH_I62_RESETVAL     (0x00000000u)
05515 
05516 #define EDMA3_CCRL_IERH_I61_MASK         (0x20000000u)
05517 #define EDMA3_CCRL_IERH_I61_SHIFT        (0x0000001Du)
05518 #define EDMA3_CCRL_IERH_I61_RESETVAL     (0x00000000u)
05519 
05520 #define EDMA3_CCRL_IERH_I60_MASK         (0x10000000u)
05521 #define EDMA3_CCRL_IERH_I60_SHIFT        (0x0000001Cu)
05522 #define EDMA3_CCRL_IERH_I60_RESETVAL     (0x00000000u)
05523 
05524 #define EDMA3_CCRL_IERH_I59_MASK         (0x08000000u)
05525 #define EDMA3_CCRL_IERH_I59_SHIFT        (0x0000001Bu)
05526 #define EDMA3_CCRL_IERH_I59_RESETVAL     (0x00000000u)
05527 
05528 #define EDMA3_CCRL_IERH_I58_MASK         (0x04000000u)
05529 #define EDMA3_CCRL_IERH_I58_SHIFT        (0x0000001Au)
05530 #define EDMA3_CCRL_IERH_I58_RESETVAL     (0x00000000u)
05531 
05532 #define EDMA3_CCRL_IERH_I57_MASK         (0x02000000u)
05533 #define EDMA3_CCRL_IERH_I57_SHIFT        (0x00000019u)
05534 #define EDMA3_CCRL_IERH_I57_RESETVAL     (0x00000000u)
05535 
05536 #define EDMA3_CCRL_IERH_I56_MASK         (0x01000000u)
05537 #define EDMA3_CCRL_IERH_I56_SHIFT        (0x00000018u)
05538 #define EDMA3_CCRL_IERH_I56_RESETVAL     (0x00000000u)
05539 
05540 #define EDMA3_CCRL_IERH_I55_MASK         (0x00800000u)
05541 #define EDMA3_CCRL_IERH_I55_SHIFT        (0x00000017u)
05542 #define EDMA3_CCRL_IERH_I55_RESETVAL     (0x00000000u)
05543 
05544 #define EDMA3_CCRL_IERH_I54_MASK         (0x00400000u)
05545 #define EDMA3_CCRL_IERH_I54_SHIFT        (0x00000016u)
05546 #define EDMA3_CCRL_IERH_I54_RESETVAL     (0x00000000u)
05547 
05548 #define EDMA3_CCRL_IERH_I53_MASK         (0x00200000u)
05549 #define EDMA3_CCRL_IERH_I53_SHIFT        (0x00000015u)
05550 #define EDMA3_CCRL_IERH_I53_RESETVAL     (0x00000000u)
05551 
05552 #define EDMA3_CCRL_IERH_I52_MASK         (0x00100000u)
05553 #define EDMA3_CCRL_IERH_I52_SHIFT        (0x00000014u)
05554 #define EDMA3_CCRL_IERH_I52_RESETVAL     (0x00000000u)
05555 
05556 #define EDMA3_CCRL_IERH_I51_MASK         (0x00080000u)
05557 #define EDMA3_CCRL_IERH_I51_SHIFT        (0x00000013u)
05558 #define EDMA3_CCRL_IERH_I51_RESETVAL     (0x00000000u)
05559 
05560 #define EDMA3_CCRL_IERH_I50_MASK         (0x00040000u)
05561 #define EDMA3_CCRL_IERH_I50_SHIFT        (0x00000012u)
05562 #define EDMA3_CCRL_IERH_I50_RESETVAL     (0x00000000u)
05563 
05564 #define EDMA3_CCRL_IERH_I49_MASK         (0x00020000u)
05565 #define EDMA3_CCRL_IERH_I49_SHIFT        (0x00000011u)
05566 #define EDMA3_CCRL_IERH_I49_RESETVAL     (0x00000000u)
05567 
05568 #define EDMA3_CCRL_IERH_I48_MASK         (0x00010000u)
05569 #define EDMA3_CCRL_IERH_I48_SHIFT        (0x00000010u)
05570 #define EDMA3_CCRL_IERH_I48_RESETVAL     (0x00000000u)
05571 
05572 #define EDMA3_CCRL_IERH_I47_MASK         (0x00008000u)
05573 #define EDMA3_CCRL_IERH_I47_SHIFT        (0x0000000Fu)
05574 #define EDMA3_CCRL_IERH_I47_RESETVAL     (0x00000000u)
05575 
05576 #define EDMA3_CCRL_IERH_I46_MASK         (0x00004000u)
05577 #define EDMA3_CCRL_IERH_I46_SHIFT        (0x0000000Eu)
05578 #define EDMA3_CCRL_IERH_I46_RESETVAL     (0x00000000u)
05579 
05580 #define EDMA3_CCRL_IERH_I45_MASK         (0x00002000u)
05581 #define EDMA3_CCRL_IERH_I45_SHIFT        (0x0000000Du)
05582 #define EDMA3_CCRL_IERH_I45_RESETVAL     (0x00000000u)
05583 
05584 #define EDMA3_CCRL_IERH_I44_MASK         (0x00001000u)
05585 #define EDMA3_CCRL_IERH_I44_SHIFT        (0x0000000Cu)
05586 #define EDMA3_CCRL_IERH_I44_RESETVAL     (0x00000000u)
05587 
05588 #define EDMA3_CCRL_IERH_I43_MASK         (0x00000800u)
05589 #define EDMA3_CCRL_IERH_I43_SHIFT        (0x0000000Bu)
05590 #define EDMA3_CCRL_IERH_I43_RESETVAL     (0x00000000u)
05591 
05592 #define EDMA3_CCRL_IERH_I42_MASK         (0x00000400u)
05593 #define EDMA3_CCRL_IERH_I42_SHIFT        (0x0000000Au)
05594 #define EDMA3_CCRL_IERH_I42_RESETVAL     (0x00000000u)
05595 
05596 #define EDMA3_CCRL_IERH_I41_MASK         (0x00000200u)
05597 #define EDMA3_CCRL_IERH_I41_SHIFT        (0x00000009u)
05598 #define EDMA3_CCRL_IERH_I41_RESETVAL     (0x00000000u)
05599 
05600 #define EDMA3_CCRL_IERH_I40_MASK         (0x00000100u)
05601 #define EDMA3_CCRL_IERH_I40_SHIFT        (0x00000008u)
05602 #define EDMA3_CCRL_IERH_I40_RESETVAL     (0x00000000u)
05603 
05604 #define EDMA3_CCRL_IERH_I39_MASK         (0x00000080u)
05605 #define EDMA3_CCRL_IERH_I39_SHIFT        (0x00000007u)
05606 #define EDMA3_CCRL_IERH_I39_RESETVAL     (0x00000000u)
05607 
05608 #define EDMA3_CCRL_IERH_I38_MASK         (0x00000040u)
05609 #define EDMA3_CCRL_IERH_I38_SHIFT        (0x00000006u)
05610 #define EDMA3_CCRL_IERH_I38_RESETVAL     (0x00000000u)
05611 
05612 #define EDMA3_CCRL_IERH_I37_MASK         (0x00000020u)
05613 #define EDMA3_CCRL_IERH_I37_SHIFT        (0x00000005u)
05614 #define EDMA3_CCRL_IERH_I37_RESETVAL     (0x00000000u)
05615 
05616 #define EDMA3_CCRL_IERH_I36_MASK         (0x00000010u)
05617 #define EDMA3_CCRL_IERH_I36_SHIFT        (0x00000004u)
05618 #define EDMA3_CCRL_IERH_I36_RESETVAL     (0x00000000u)
05619 
05620 #define EDMA3_CCRL_IERH_I35_MASK         (0x00000008u)
05621 #define EDMA3_CCRL_IERH_I35_SHIFT        (0x00000003u)
05622 #define EDMA3_CCRL_IERH_I35_RESETVAL     (0x00000000u)
05623 
05624 #define EDMA3_CCRL_IERH_I34_MASK         (0x00000004u)
05625 #define EDMA3_CCRL_IERH_I34_SHIFT        (0x00000002u)
05626 #define EDMA3_CCRL_IERH_I34_RESETVAL     (0x00000000u)
05627 
05628 #define EDMA3_CCRL_IERH_I33_MASK         (0x00000002u)
05629 #define EDMA3_CCRL_IERH_I33_SHIFT        (0x00000001u)
05630 #define EDMA3_CCRL_IERH_I33_RESETVAL     (0x00000000u)
05631 
05632 #define EDMA3_CCRL_IERH_I32_MASK         (0x00000001u)
05633 #define EDMA3_CCRL_IERH_I32_SHIFT        (0x00000000u)
05634 #define EDMA3_CCRL_IERH_I32_RESETVAL     (0x00000000u)
05635 
05636 #define EDMA3_CCRL_IERH_RESETVAL         (0x00000000u)
05637 
05638 /* IECR */
05639 
05640 #define EDMA3_CCRL_IECR_I31_MASK         (0x80000000u)
05641 #define EDMA3_CCRL_IECR_I31_SHIFT        (0x0000001Fu)
05642 #define EDMA3_CCRL_IECR_I31_RESETVAL     (0x00000000u)
05643 
05644 /*----I31 Tokens----*/
05645 #define EDMA3_CCRL_IECR_I31_CLEAR        (0x00000001u)
05646 
05647 #define EDMA3_CCRL_IECR_I30_MASK         (0x40000000u)
05648 #define EDMA3_CCRL_IECR_I30_SHIFT        (0x0000001Eu)
05649 #define EDMA3_CCRL_IECR_I30_RESETVAL     (0x00000000u)
05650 
05651 /*----I30 Tokens----*/
05652 #define EDMA3_CCRL_IECR_I30_CLEAR        (0x00000001u)
05653 
05654 #define EDMA3_CCRL_IECR_I29_MASK         (0x20000000u)
05655 #define EDMA3_CCRL_IECR_I29_SHIFT        (0x0000001Du)
05656 #define EDMA3_CCRL_IECR_I29_RESETVAL     (0x00000000u)
05657 
05658 /*----I29 Tokens----*/
05659 #define EDMA3_CCRL_IECR_I29_CLEAR        (0x00000001u)
05660 
05661 #define EDMA3_CCRL_IECR_I28_MASK         (0x10000000u)
05662 #define EDMA3_CCRL_IECR_I28_SHIFT        (0x0000001Cu)
05663 #define EDMA3_CCRL_IECR_I28_RESETVAL     (0x00000000u)
05664 
05665 /*----I28 Tokens----*/
05666 #define EDMA3_CCRL_IECR_I28_CLEAR        (0x00000001u)
05667 
05668 #define EDMA3_CCRL_IECR_I27_MASK         (0x08000000u)
05669 #define EDMA3_CCRL_IECR_I27_SHIFT        (0x0000001Bu)
05670 #define EDMA3_CCRL_IECR_I27_RESETVAL     (0x00000000u)
05671 
05672 /*----I27 Tokens----*/
05673 #define EDMA3_CCRL_IECR_I27_CLEAR        (0x00000001u)
05674 
05675 #define EDMA3_CCRL_IECR_I26_MASK         (0x04000000u)
05676 #define EDMA3_CCRL_IECR_I26_SHIFT        (0x0000001Au)
05677 #define EDMA3_CCRL_IECR_I26_RESETVAL     (0x00000000u)
05678 
05679 /*----I26 Tokens----*/
05680 #define EDMA3_CCRL_IECR_I26_CLEAR        (0x00000001u)
05681 
05682 #define EDMA3_CCRL_IECR_I25_MASK         (0x02000000u)
05683 #define EDMA3_CCRL_IECR_I25_SHIFT        (0x00000019u)
05684 #define EDMA3_CCRL_IECR_I25_RESETVAL     (0x00000000u)
05685 
05686 /*----I25 Tokens----*/
05687 #define EDMA3_CCRL_IECR_I25_CLEAR        (0x00000001u)
05688 
05689 #define EDMA3_CCRL_IECR_I24_MASK         (0x01000000u)
05690 #define EDMA3_CCRL_IECR_I24_SHIFT        (0x00000018u)
05691 #define EDMA3_CCRL_IECR_I24_RESETVAL     (0x00000000u)
05692 
05693 /*----I24 Tokens----*/
05694 #define EDMA3_CCRL_IECR_I24_CLEAR        (0x00000001u)
05695 
05696 #define EDMA3_CCRL_IECR_I23_MASK         (0x00800000u)
05697 #define EDMA3_CCRL_IECR_I23_SHIFT        (0x00000017u)
05698 #define EDMA3_CCRL_IECR_I23_RESETVAL     (0x00000000u)
05699 
05700 /*----I23 Tokens----*/
05701 #define EDMA3_CCRL_IECR_I23_CLEAR        (0x00000001u)
05702 
05703 #define EDMA3_CCRL_IECR_I22_MASK         (0x00400000u)
05704 #define EDMA3_CCRL_IECR_I22_SHIFT        (0x00000016u)
05705 #define EDMA3_CCRL_IECR_I22_RESETVAL     (0x00000000u)
05706 
05707 /*----I22 Tokens----*/
05708 #define EDMA3_CCRL_IECR_I22_CLEAR        (0x00000001u)
05709 
05710 #define EDMA3_CCRL_IECR_I21_MASK         (0x00200000u)
05711 #define EDMA3_CCRL_IECR_I21_SHIFT        (0x00000015u)
05712 #define EDMA3_CCRL_IECR_I21_RESETVAL     (0x00000000u)
05713 
05714 /*----I21 Tokens----*/
05715 #define EDMA3_CCRL_IECR_I21_CLEAR        (0x00000001u)
05716 
05717 #define EDMA3_CCRL_IECR_I20_MASK         (0x00100000u)
05718 #define EDMA3_CCRL_IECR_I20_SHIFT        (0x00000014u)
05719 #define EDMA3_CCRL_IECR_I20_RESETVAL     (0x00000000u)
05720 
05721 /*----I20 Tokens----*/
05722 #define EDMA3_CCRL_IECR_I20_CLEAR        (0x00000001u)
05723 
05724 #define EDMA3_CCRL_IECR_I19_MASK         (0x00080000u)
05725 #define EDMA3_CCRL_IECR_I19_SHIFT        (0x00000013u)
05726 #define EDMA3_CCRL_IECR_I19_RESETVAL     (0x00000000u)
05727 
05728 /*----I19 Tokens----*/
05729 #define EDMA3_CCRL_IECR_I19_CLEAR        (0x00000001u)
05730 
05731 #define EDMA3_CCRL_IECR_I18_MASK         (0x00040000u)
05732 #define EDMA3_CCRL_IECR_I18_SHIFT        (0x00000012u)
05733 #define EDMA3_CCRL_IECR_I18_RESETVAL     (0x00000000u)
05734 
05735 /*----I18 Tokens----*/
05736 #define EDMA3_CCRL_IECR_I18_CLEAR        (0x00000001u)
05737 
05738 #define EDMA3_CCRL_IECR_I17_MASK         (0x00020000u)
05739 #define EDMA3_CCRL_IECR_I17_SHIFT        (0x00000011u)
05740 #define EDMA3_CCRL_IECR_I17_RESETVAL     (0x00000000u)
05741 
05742 /*----I17 Tokens----*/
05743 #define EDMA3_CCRL_IECR_I17_CLEAR        (0x00000001u)
05744 
05745 #define EDMA3_CCRL_IECR_I16_MASK         (0x00010000u)
05746 #define EDMA3_CCRL_IECR_I16_SHIFT        (0x00000010u)
05747 #define EDMA3_CCRL_IECR_I16_RESETVAL     (0x00000000u)
05748 
05749 /*----I16 Tokens----*/
05750 #define EDMA3_CCRL_IECR_I16_CLEAR        (0x00000001u)
05751 
05752 #define EDMA3_CCRL_IECR_I15_MASK         (0x00008000u)
05753 #define EDMA3_CCRL_IECR_I15_SHIFT        (0x0000000Fu)
05754 #define EDMA3_CCRL_IECR_I15_RESETVAL     (0x00000000u)
05755 
05756 /*----I15 Tokens----*/
05757 #define EDMA3_CCRL_IECR_I15_CLEAR        (0x00000001u)
05758 
05759 #define EDMA3_CCRL_IECR_I14_MASK         (0x00004000u)
05760 #define EDMA3_CCRL_IECR_I14_SHIFT        (0x0000000Eu)
05761 #define EDMA3_CCRL_IECR_I14_RESETVAL     (0x00000000u)
05762 
05763 /*----I14 Tokens----*/
05764 #define EDMA3_CCRL_IECR_I14_CLEAR        (0x00000001u)
05765 
05766 #define EDMA3_CCRL_IECR_I13_MASK         (0x00002000u)
05767 #define EDMA3_CCRL_IECR_I13_SHIFT        (0x0000000Du)
05768 #define EDMA3_CCRL_IECR_I13_RESETVAL     (0x00000000u)
05769 
05770 /*----I13 Tokens----*/
05771 #define EDMA3_CCRL_IECR_I13_CLEAR        (0x00000001u)
05772 
05773 #define EDMA3_CCRL_IECR_I12_MASK         (0x00001000u)
05774 #define EDMA3_CCRL_IECR_I12_SHIFT        (0x0000000Cu)
05775 #define EDMA3_CCRL_IECR_I12_RESETVAL     (0x00000000u)
05776 
05777 /*----I12 Tokens----*/
05778 #define EDMA3_CCRL_IECR_I12_CLEAR        (0x00000001u)
05779 
05780 #define EDMA3_CCRL_IECR_I11_MASK         (0x00000800u)
05781 #define EDMA3_CCRL_IECR_I11_SHIFT        (0x0000000Bu)
05782 #define EDMA3_CCRL_IECR_I11_RESETVAL     (0x00000000u)
05783 
05784 /*----I11 Tokens----*/
05785 #define EDMA3_CCRL_IECR_I11_CLEAR        (0x00000001u)
05786 
05787 #define EDMA3_CCRL_IECR_I10_MASK         (0x00000400u)
05788 #define EDMA3_CCRL_IECR_I10_SHIFT        (0x0000000Au)
05789 #define EDMA3_CCRL_IECR_I10_RESETVAL     (0x00000000u)
05790 
05791 /*----I10 Tokens----*/
05792 #define EDMA3_CCRL_IECR_I10_CLEAR        (0x00000001u)
05793 
05794 #define EDMA3_CCRL_IECR_I9_MASK          (0x00000200u)
05795 #define EDMA3_CCRL_IECR_I9_SHIFT         (0x00000009u)
05796 #define EDMA3_CCRL_IECR_I9_RESETVAL      (0x00000000u)
05797 
05798 /*----I9 Tokens----*/
05799 #define EDMA3_CCRL_IECR_I9_CLEAR         (0x00000001u)
05800 
05801 #define EDMA3_CCRL_IECR_I8_MASK          (0x00000100u)
05802 #define EDMA3_CCRL_IECR_I8_SHIFT         (0x00000008u)
05803 #define EDMA3_CCRL_IECR_I8_RESETVAL      (0x00000000u)
05804 
05805 /*----I8 Tokens----*/
05806 #define EDMA3_CCRL_IECR_I8_CLEAR         (0x00000001u)
05807 
05808 #define EDMA3_CCRL_IECR_I7_MASK          (0x00000080u)
05809 #define EDMA3_CCRL_IECR_I7_SHIFT         (0x00000007u)
05810 #define EDMA3_CCRL_IECR_I7_RESETVAL      (0x00000000u)
05811 
05812 /*----I7 Tokens----*/
05813 #define EDMA3_CCRL_IECR_I7_CLEAR         (0x00000001u)
05814 
05815 #define EDMA3_CCRL_IECR_I6_MASK          (0x00000040u)
05816 #define EDMA3_CCRL_IECR_I6_SHIFT         (0x00000006u)
05817 #define EDMA3_CCRL_IECR_I6_RESETVAL      (0x00000000u)
05818 
05819 /*----I6 Tokens----*/
05820 #define EDMA3_CCRL_IECR_I6_CLEAR         (0x00000001u)
05821 
05822 #define EDMA3_CCRL_IECR_I5_MASK          (0x00000020u)
05823 #define EDMA3_CCRL_IECR_I5_SHIFT         (0x00000005u)
05824 #define EDMA3_CCRL_IECR_I5_RESETVAL      (0x00000000u)
05825 
05826 /*----I5 Tokens----*/
05827 #define EDMA3_CCRL_IECR_I5_CLEAR         (0x00000001u)
05828 
05829 #define EDMA3_CCRL_IECR_I4_MASK          (0x00000010u)
05830 #define EDMA3_CCRL_IECR_I4_SHIFT         (0x00000004u)
05831 #define EDMA3_CCRL_IECR_I4_RESETVAL      (0x00000000u)
05832 
05833 /*----I4 Tokens----*/
05834 #define EDMA3_CCRL_IECR_I4_CLEAR         (0x00000001u)
05835 
05836 #define EDMA3_CCRL_IECR_I3_MASK          (0x00000008u)
05837 #define EDMA3_CCRL_IECR_I3_SHIFT         (0x00000003u)
05838 #define EDMA3_CCRL_IECR_I3_RESETVAL      (0x00000000u)
05839 
05840 /*----I3 Tokens----*/
05841 #define EDMA3_CCRL_IECR_I3_CLEAR         (0x00000001u)
05842 
05843 #define EDMA3_CCRL_IECR_I2_MASK          (0x00000004u)
05844 #define EDMA3_CCRL_IECR_I2_SHIFT         (0x00000002u)
05845 #define EDMA3_CCRL_IECR_I2_RESETVAL      (0x00000000u)
05846 
05847 /*----I2 Tokens----*/
05848 #define EDMA3_CCRL_IECR_I2_CLEAR         (0x00000001u)
05849 
05850 #define EDMA3_CCRL_IECR_I1_MASK          (0x00000002u)
05851 #define EDMA3_CCRL_IECR_I1_SHIFT         (0x00000001u)
05852 #define EDMA3_CCRL_IECR_I1_RESETVAL      (0x00000000u)
05853 
05854 /*----I1 Tokens----*/
05855 #define EDMA3_CCRL_IECR_I1_CLEAR         (0x00000001u)
05856 
05857 #define EDMA3_CCRL_IECR_I0_MASK          (0x00000001u)
05858 #define EDMA3_CCRL_IECR_I0_SHIFT         (0x00000000u)
05859 #define EDMA3_CCRL_IECR_I0_RESETVAL      (0x00000000u)
05860 
05861 /*----I0 Tokens----*/
05862 #define EDMA3_CCRL_IECR_I0_CLEAR         (0x00000001u)
05863 
05864 #define EDMA3_CCRL_IECR_RESETVAL         (0x00000000u)
05865 
05866 /* IECRH */
05867 
05868 #define EDMA3_CCRL_IECRH_I63_MASK        (0x80000000u)
05869 #define EDMA3_CCRL_IECRH_I63_SHIFT       (0x0000001Fu)
05870 #define EDMA3_CCRL_IECRH_I63_RESETVAL    (0x00000000u)
05871 
05872 /*----I63 Tokens----*/
05873 #define EDMA3_CCRL_IECRH_I63_CLEAR       (0x00000001u)
05874 
05875 #define EDMA3_CCRL_IECRH_I62_MASK        (0x40000000u)
05876 #define EDMA3_CCRL_IECRH_I62_SHIFT       (0x0000001Eu)
05877 #define EDMA3_CCRL_IECRH_I62_RESETVAL    (0x00000000u)
05878 
05879 /*----I62 Tokens----*/
05880 #define EDMA3_CCRL_IECRH_I62_CLEAR       (0x00000001u)
05881 
05882 #define EDMA3_CCRL_IECRH_I61_MASK        (0x20000000u)
05883 #define EDMA3_CCRL_IECRH_I61_SHIFT       (0x0000001Du)
05884 #define EDMA3_CCRL_IECRH_I61_RESETVAL    (0x00000000u)
05885 
05886 /*----I61 Tokens----*/
05887 #define EDMA3_CCRL_IECRH_I61_CLEAR       (0x00000001u)
05888 
05889 #define EDMA3_CCRL_IECRH_I60_MASK        (0x10000000u)
05890 #define EDMA3_CCRL_IECRH_I60_SHIFT       (0x0000001Cu)
05891 #define EDMA3_CCRL_IECRH_I60_RESETVAL    (0x00000000u)
05892 
05893 /*----I60 Tokens----*/
05894 #define EDMA3_CCRL_IECRH_I60_CLEAR       (0x00000001u)
05895 
05896 #define EDMA3_CCRL_IECRH_I59_MASK        (0x08000000u)
05897 #define EDMA3_CCRL_IECRH_I59_SHIFT       (0x0000001Bu)
05898 #define EDMA3_CCRL_IECRH_I59_RESETVAL    (0x00000000u)
05899 
05900 /*----I59 Tokens----*/
05901 #define EDMA3_CCRL_IECRH_I59_CLEAR       (0x00000001u)
05902 
05903 #define EDMA3_CCRL_IECRH_I58_MASK        (0x04000000u)
05904 #define EDMA3_CCRL_IECRH_I58_SHIFT       (0x0000001Au)
05905 #define EDMA3_CCRL_IECRH_I58_RESETVAL    (0x00000000u)
05906 
05907 /*----I58 Tokens----*/
05908 #define EDMA3_CCRL_IECRH_I58_CLEAR       (0x00000001u)
05909 
05910 #define EDMA3_CCRL_IECRH_I57_MASK        (0x02000000u)
05911 #define EDMA3_CCRL_IECRH_I57_SHIFT       (0x00000019u)
05912 #define EDMA3_CCRL_IECRH_I57_RESETVAL    (0x00000000u)
05913 
05914 /*----I57 Tokens----*/
05915 #define EDMA3_CCRL_IECRH_I57_CLEAR       (0x00000001u)
05916 
05917 #define EDMA3_CCRL_IECRH_I56_MASK        (0x01000000u)
05918 #define EDMA3_CCRL_IECRH_I56_SHIFT       (0x00000018u)
05919 #define EDMA3_CCRL_IECRH_I56_RESETVAL    (0x00000000u)
05920 
05921 /*----I56 Tokens----*/
05922 #define EDMA3_CCRL_IECRH_I56_CLEAR       (0x00000001u)
05923 
05924 #define EDMA3_CCRL_IECRH_I55_MASK        (0x00800000u)
05925 #define EDMA3_CCRL_IECRH_I55_SHIFT       (0x00000017u)
05926 #define EDMA3_CCRL_IECRH_I55_RESETVAL    (0x00000000u)
05927 
05928 /*----I55 Tokens----*/
05929 #define EDMA3_CCRL_IECRH_I55_CLEAR       (0x00000001u)
05930 
05931 #define EDMA3_CCRL_IECRH_I54_MASK        (0x00400000u)
05932 #define EDMA3_CCRL_IECRH_I54_SHIFT       (0x00000016u)
05933 #define EDMA3_CCRL_IECRH_I54_RESETVAL    (0x00000000u)
05934 
05935 /*----I54 Tokens----*/
05936 #define EDMA3_CCRL_IECRH_I54_CLEAR       (0x00000001u)
05937 
05938 #define EDMA3_CCRL_IECRH_I53_MASK        (0x00200000u)
05939 #define EDMA3_CCRL_IECRH_I53_SHIFT       (0x00000015u)
05940 #define EDMA3_CCRL_IECRH_I53_RESETVAL    (0x00000000u)
05941 
05942 /*----I53 Tokens----*/
05943 #define EDMA3_CCRL_IECRH_I53_CLEAR       (0x00000001u)
05944 
05945 #define EDMA3_CCRL_IECRH_I52_MASK        (0x00100000u)
05946 #define EDMA3_CCRL_IECRH_I52_SHIFT       (0x00000014u)
05947 #define EDMA3_CCRL_IECRH_I52_RESETVAL    (0x00000000u)
05948 
05949 /*----I52 Tokens----*/
05950 #define EDMA3_CCRL_IECRH_I52_CLEAR       (0x00000001u)
05951 
05952 #define EDMA3_CCRL_IECRH_I51_MASK        (0x00080000u)
05953 #define EDMA3_CCRL_IECRH_I51_SHIFT       (0x00000013u)
05954 #define EDMA3_CCRL_IECRH_I51_RESETVAL    (0x00000000u)
05955 
05956 /*----I51 Tokens----*/
05957 #define EDMA3_CCRL_IECRH_I51_CLEAR       (0x00000001u)
05958 
05959 #define EDMA3_CCRL_IECRH_I50_MASK        (0x00040000u)
05960 #define EDMA3_CCRL_IECRH_I50_SHIFT       (0x00000012u)
05961 #define EDMA3_CCRL_IECRH_I50_RESETVAL    (0x00000000u)
05962 
05963 /*----I50 Tokens----*/
05964 #define EDMA3_CCRL_IECRH_I50_CLEAR       (0x00000001u)
05965 
05966 #define EDMA3_CCRL_IECRH_I49_MASK        (0x00020000u)
05967 #define EDMA3_CCRL_IECRH_I49_SHIFT       (0x00000011u)
05968 #define EDMA3_CCRL_IECRH_I49_RESETVAL    (0x00000000u)
05969 
05970 /*----I49 Tokens----*/
05971 #define EDMA3_CCRL_IECRH_I49_CLEAR       (0x00000001u)
05972 
05973 #define EDMA3_CCRL_IECRH_I48_MASK        (0x00010000u)
05974 #define EDMA3_CCRL_IECRH_I48_SHIFT       (0x00000010u)
05975 #define EDMA3_CCRL_IECRH_I48_RESETVAL    (0x00000000u)
05976 
05977 /*----I48 Tokens----*/
05978 #define EDMA3_CCRL_IECRH_I48_CLEAR       (0x00000001u)
05979 
05980 #define EDMA3_CCRL_IECRH_I47_MASK        (0x00008000u)
05981 #define EDMA3_CCRL_IECRH_I47_SHIFT       (0x0000000Fu)
05982 #define EDMA3_CCRL_IECRH_I47_RESETVAL    (0x00000000u)
05983 
05984 /*----I47 Tokens----*/
05985 #define EDMA3_CCRL_IECRH_I47_CLEAR       (0x00000001u)
05986 
05987 #define EDMA3_CCRL_IECRH_I46_MASK        (0x00004000u)
05988 #define EDMA3_CCRL_IECRH_I46_SHIFT       (0x0000000Eu)
05989 #define EDMA3_CCRL_IECRH_I46_RESETVAL    (0x00000000u)
05990 
05991 /*----I46 Tokens----*/
05992 #define EDMA3_CCRL_IECRH_I46_CLEAR       (0x00000001u)
05993 
05994 #define EDMA3_CCRL_IECRH_I45_MASK        (0x00002000u)
05995 #define EDMA3_CCRL_IECRH_I45_SHIFT       (0x0000000Du)
05996 #define EDMA3_CCRL_IECRH_I45_RESETVAL    (0x00000000u)
05997 
05998 /*----I45 Tokens----*/
05999 #define EDMA3_CCRL_IECRH_I45_CLEAR       (0x00000001u)
06000 
06001 #define EDMA3_CCRL_IECRH_I44_MASK        (0x00001000u)
06002 #define EDMA3_CCRL_IECRH_I44_SHIFT       (0x0000000Cu)
06003 #define EDMA3_CCRL_IECRH_I44_RESETVAL    (0x00000000u)
06004 
06005 /*----I44 Tokens----*/
06006 #define EDMA3_CCRL_IECRH_I44_CLEAR       (0x00000001u)
06007 
06008 #define EDMA3_CCRL_IECRH_I43_MASK        (0x00000800u)
06009 #define EDMA3_CCRL_IECRH_I43_SHIFT       (0x0000000Bu)
06010 #define EDMA3_CCRL_IECRH_I43_RESETVAL    (0x00000000u)
06011 
06012 /*----I43 Tokens----*/
06013 #define EDMA3_CCRL_IECRH_I43_CLEAR       (0x00000001u)
06014 
06015 #define EDMA3_CCRL_IECRH_I42_MASK        (0x00000400u)
06016 #define EDMA3_CCRL_IECRH_I42_SHIFT       (0x0000000Au)
06017 #define EDMA3_CCRL_IECRH_I42_RESETVAL    (0x00000000u)
06018 
06019 /*----I42 Tokens----*/
06020 #define EDMA3_CCRL_IECRH_I42_CLEAR       (0x00000001u)
06021 
06022 #define EDMA3_CCRL_IECRH_I41_MASK        (0x00000200u)
06023 #define EDMA3_CCRL_IECRH_I41_SHIFT       (0x00000009u)
06024 #define EDMA3_CCRL_IECRH_I41_RESETVAL    (0x00000000u)
06025 
06026 /*----I41 Tokens----*/
06027 #define EDMA3_CCRL_IECRH_I41_CLEAR       (0x00000001u)
06028 
06029 #define EDMA3_CCRL_IECRH_I40_MASK        (0x00000100u)
06030 #define EDMA3_CCRL_IECRH_I40_SHIFT       (0x00000008u)
06031 #define EDMA3_CCRL_IECRH_I40_RESETVAL    (0x00000000u)
06032 
06033 /*----I40 Tokens----*/
06034 #define EDMA3_CCRL_IECRH_I40_CLEAR       (0x00000001u)
06035 
06036 #define EDMA3_CCRL_IECRH_I39_MASK        (0x00000080u)
06037 #define EDMA3_CCRL_IECRH_I39_SHIFT       (0x00000007u)
06038 #define EDMA3_CCRL_IECRH_I39_RESETVAL    (0x00000000u)
06039 
06040 /*----I39 Tokens----*/
06041 #define EDMA3_CCRL_IECRH_I39_CLEAR       (0x00000001u)
06042 
06043 #define EDMA3_CCRL_IECRH_I38_MASK        (0x00000040u)
06044 #define EDMA3_CCRL_IECRH_I38_SHIFT       (0x00000006u)
06045 #define EDMA3_CCRL_IECRH_I38_RESETVAL    (0x00000000u)
06046 
06047 /*----I38 Tokens----*/
06048 #define EDMA3_CCRL_IECRH_I38_CLEAR       (0x00000001u)
06049 
06050 #define EDMA3_CCRL_IECRH_I37_MASK        (0x00000020u)
06051 #define EDMA3_CCRL_IECRH_I37_SHIFT       (0x00000005u)
06052 #define EDMA3_CCRL_IECRH_I37_RESETVAL    (0x00000000u)
06053 
06054 /*----I37 Tokens----*/
06055 #define EDMA3_CCRL_IECRH_I37_CLEAR       (0x00000001u)
06056 
06057 #define EDMA3_CCRL_IECRH_I36_MASK        (0x00000010u)
06058 #define EDMA3_CCRL_IECRH_I36_SHIFT       (0x00000004u)
06059 #define EDMA3_CCRL_IECRH_I36_RESETVAL    (0x00000000u)
06060 
06061 /*----I36 Tokens----*/
06062 #define EDMA3_CCRL_IECRH_I36_CLEAR       (0x00000001u)
06063 
06064 #define EDMA3_CCRL_IECRH_I35_MASK        (0x00000008u)
06065 #define EDMA3_CCRL_IECRH_I35_SHIFT       (0x00000003u)
06066 #define EDMA3_CCRL_IECRH_I35_RESETVAL    (0x00000000u)
06067 
06068 /*----I35 Tokens----*/
06069 #define EDMA3_CCRL_IECRH_I35_CLEAR       (0x00000001u)
06070 
06071 #define EDMA3_CCRL_IECRH_I34_MASK        (0x00000004u)
06072 #define EDMA3_CCRL_IECRH_I34_SHIFT       (0x00000002u)
06073 #define EDMA3_CCRL_IECRH_I34_RESETVAL    (0x00000000u)
06074 
06075 /*----I34 Tokens----*/
06076 #define EDMA3_CCRL_IECRH_I34_CLEAR       (0x00000001u)
06077 
06078 #define EDMA3_CCRL_IECRH_I33_MASK        (0x00000002u)
06079 #define EDMA3_CCRL_IECRH_I33_SHIFT       (0x00000001u)
06080 #define EDMA3_CCRL_IECRH_I33_RESETVAL    (0x00000000u)
06081 
06082 /*----I33 Tokens----*/
06083 #define EDMA3_CCRL_IECRH_I33_CLEAR       (0x00000001u)
06084 
06085 #define EDMA3_CCRL_IECRH_I32_MASK        (0x00000001u)
06086 #define EDMA3_CCRL_IECRH_I32_SHIFT       (0x00000000u)
06087 #define EDMA3_CCRL_IECRH_I32_RESETVAL    (0x00000000u)
06088 
06089 /*----I32 Tokens----*/
06090 #define EDMA3_CCRL_IECRH_I32_CLEAR       (0x00000001u)
06091 
06092 #define EDMA3_CCRL_IECRH_RESETVAL        (0x00000000u)
06093 
06094 /* IESR */
06095 
06096 #define EDMA3_CCRL_IESR_I31_MASK         (0x80000000u)
06097 #define EDMA3_CCRL_IESR_I31_SHIFT        (0x0000001Fu)
06098 #define EDMA3_CCRL_IESR_I31_RESETVAL     (0x00000000u)
06099 
06100 /*----I31 Tokens----*/
06101 #define EDMA3_CCRL_IESR_I31_SET          (0x00000001u)
06102 
06103 #define EDMA3_CCRL_IESR_I30_MASK         (0x40000000u)
06104 #define EDMA3_CCRL_IESR_I30_SHIFT        (0x0000001Eu)
06105 #define EDMA3_CCRL_IESR_I30_RESETVAL     (0x00000000u)
06106 
06107 /*----I30 Tokens----*/
06108 #define EDMA3_CCRL_IESR_I30_SET          (0x00000001u)
06109 
06110 #define EDMA3_CCRL_IESR_I29_MASK         (0x20000000u)
06111 #define EDMA3_CCRL_IESR_I29_SHIFT        (0x0000001Du)
06112 #define EDMA3_CCRL_IESR_I29_RESETVAL     (0x00000000u)
06113 
06114 /*----I29 Tokens----*/
06115 #define EDMA3_CCRL_IESR_I29_SET          (0x00000001u)
06116 
06117 #define EDMA3_CCRL_IESR_I28_MASK         (0x10000000u)
06118 #define EDMA3_CCRL_IESR_I28_SHIFT        (0x0000001Cu)
06119 #define EDMA3_CCRL_IESR_I28_RESETVAL     (0x00000000u)
06120 
06121 /*----I28 Tokens----*/
06122 #define EDMA3_CCRL_IESR_I28_SET          (0x00000001u)
06123 
06124 #define EDMA3_CCRL_IESR_I27_MASK         (0x08000000u)
06125 #define EDMA3_CCRL_IESR_I27_SHIFT        (0x0000001Bu)
06126 #define EDMA3_CCRL_IESR_I27_RESETVAL     (0x00000000u)
06127 
06128 /*----I27 Tokens----*/
06129 #define EDMA3_CCRL_IESR_I27_SET          (0x00000001u)
06130 
06131 #define EDMA3_CCRL_IESR_I26_MASK         (0x04000000u)
06132 #define EDMA3_CCRL_IESR_I26_SHIFT        (0x0000001Au)
06133 #define EDMA3_CCRL_IESR_I26_RESETVAL     (0x00000000u)
06134 
06135 /*----I26 Tokens----*/
06136 #define EDMA3_CCRL_IESR_I26_SET          (0x00000001u)
06137 
06138 #define EDMA3_CCRL_IESR_I25_MASK         (0x02000000u)
06139 #define EDMA3_CCRL_IESR_I25_SHIFT        (0x00000019u)
06140 #define EDMA3_CCRL_IESR_I25_RESETVAL     (0x00000000u)
06141 
06142 /*----I25 Tokens----*/
06143 #define EDMA3_CCRL_IESR_I25_SET          (0x00000001u)
06144 
06145 #define EDMA3_CCRL_IESR_I24_MASK         (0x01000000u)
06146 #define EDMA3_CCRL_IESR_I24_SHIFT        (0x00000018u)
06147 #define EDMA3_CCRL_IESR_I24_RESETVAL     (0x00000000u)
06148 
06149 /*----I24 Tokens----*/
06150 #define EDMA3_CCRL_IESR_I24_SET          (0x00000001u)
06151 
06152 #define EDMA3_CCRL_IESR_I23_MASK         (0x00800000u)
06153 #define EDMA3_CCRL_IESR_I23_SHIFT        (0x00000017u)
06154 #define EDMA3_CCRL_IESR_I23_RESETVAL     (0x00000000u)
06155 
06156 /*----I23 Tokens----*/
06157 #define EDMA3_CCRL_IESR_I23_SET          (0x00000001u)
06158 
06159 #define EDMA3_CCRL_IESR_I22_MASK         (0x00400000u)
06160 #define EDMA3_CCRL_IESR_I22_SHIFT        (0x00000016u)
06161 #define EDMA3_CCRL_IESR_I22_RESETVAL     (0x00000000u)
06162 
06163 /*----I22 Tokens----*/
06164 #define EDMA3_CCRL_IESR_I22_SET          (0x00000001u)
06165 
06166 #define EDMA3_CCRL_IESR_I21_MASK         (0x00200000u)
06167 #define EDMA3_CCRL_IESR_I21_SHIFT        (0x00000015u)
06168 #define EDMA3_CCRL_IESR_I21_RESETVAL     (0x00000000u)
06169 
06170 /*----I21 Tokens----*/
06171 #define EDMA3_CCRL_IESR_I21_SET          (0x00000001u)
06172 
06173 #define EDMA3_CCRL_IESR_I20_MASK         (0x00100000u)
06174 #define EDMA3_CCRL_IESR_I20_SHIFT        (0x00000014u)
06175 #define EDMA3_CCRL_IESR_I20_RESETVAL     (0x00000000u)
06176 
06177 /*----I20 Tokens----*/
06178 #define EDMA3_CCRL_IESR_I20_SET          (0x00000001u)
06179 
06180 #define EDMA3_CCRL_IESR_I19_MASK         (0x00080000u)
06181 #define EDMA3_CCRL_IESR_I19_SHIFT        (0x00000013u)
06182 #define EDMA3_CCRL_IESR_I19_RESETVAL     (0x00000000u)
06183 
06184 /*----I19 Tokens----*/
06185 #define EDMA3_CCRL_IESR_I19_SET          (0x00000001u)
06186 
06187 #define EDMA3_CCRL_IESR_I18_MASK         (0x00040000u)
06188 #define EDMA3_CCRL_IESR_I18_SHIFT        (0x00000012u)
06189 #define EDMA3_CCRL_IESR_I18_RESETVAL     (0x00000000u)
06190 
06191 /*----I18 Tokens----*/
06192 #define EDMA3_CCRL_IESR_I18_SET          (0x00000001u)
06193 
06194 #define EDMA3_CCRL_IESR_I17_MASK         (0x00020000u)
06195 #define EDMA3_CCRL_IESR_I17_SHIFT        (0x00000011u)
06196 #define EDMA3_CCRL_IESR_I17_RESETVAL     (0x00000000u)
06197 
06198 /*----I17 Tokens----*/
06199 #define EDMA3_CCRL_IESR_I17_SET          (0x00000001u)
06200 
06201 #define EDMA3_CCRL_IESR_I16_MASK         (0x00010000u)
06202 #define EDMA3_CCRL_IESR_I16_SHIFT        (0x00000010u)
06203 #define EDMA3_CCRL_IESR_I16_RESETVAL     (0x00000000u)
06204 
06205 /*----I16 Tokens----*/
06206 #define EDMA3_CCRL_IESR_I16_SET          (0x00000001u)
06207 
06208 #define EDMA3_CCRL_IESR_I15_MASK         (0x00008000u)
06209 #define EDMA3_CCRL_IESR_I15_SHIFT        (0x0000000Fu)
06210 #define EDMA3_CCRL_IESR_I15_RESETVAL     (0x00000000u)
06211 
06212 /*----I15 Tokens----*/
06213 #define EDMA3_CCRL_IESR_I15_SET          (0x00000001u)
06214 
06215 #define EDMA3_CCRL_IESR_I14_MASK         (0x00004000u)
06216 #define EDMA3_CCRL_IESR_I14_SHIFT        (0x0000000Eu)
06217 #define EDMA3_CCRL_IESR_I14_RESETVAL     (0x00000000u)
06218 
06219 /*----I14 Tokens----*/
06220 #define EDMA3_CCRL_IESR_I14_SET          (0x00000001u)
06221 
06222 #define EDMA3_CCRL_IESR_I13_MASK         (0x00002000u)
06223 #define EDMA3_CCRL_IESR_I13_SHIFT        (0x0000000Du)
06224 #define EDMA3_CCRL_IESR_I13_RESETVAL     (0x00000000u)
06225 
06226 /*----I13 Tokens----*/
06227 #define EDMA3_CCRL_IESR_I13_SET          (0x00000001u)
06228 
06229 #define EDMA3_CCRL_IESR_I12_MASK         (0x00001000u)
06230 #define EDMA3_CCRL_IESR_I12_SHIFT        (0x0000000Cu)
06231 #define EDMA3_CCRL_IESR_I12_RESETVAL     (0x00000000u)
06232 
06233 /*----I12 Tokens----*/
06234 #define EDMA3_CCRL_IESR_I12_SET          (0x00000001u)
06235 
06236 #define EDMA3_CCRL_IESR_I11_MASK         (0x00000800u)
06237 #define EDMA3_CCRL_IESR_I11_SHIFT        (0x0000000Bu)
06238 #define EDMA3_CCRL_IESR_I11_RESETVAL     (0x00000000u)
06239 
06240 /*----I11 Tokens----*/
06241 #define EDMA3_CCRL_IESR_I11_SET          (0x00000001u)
06242 
06243 #define EDMA3_CCRL_IESR_I10_MASK         (0x00000400u)
06244 #define EDMA3_CCRL_IESR_I10_SHIFT        (0x0000000Au)
06245 #define EDMA3_CCRL_IESR_I10_RESETVAL     (0x00000000u)
06246 
06247 /*----I10 Tokens----*/
06248 #define EDMA3_CCRL_IESR_I10_SET          (0x00000001u)
06249 
06250 #define EDMA3_CCRL_IESR_I9_MASK          (0x00000200u)
06251 #define EDMA3_CCRL_IESR_I9_SHIFT         (0x00000009u)
06252 #define EDMA3_CCRL_IESR_I9_RESETVAL      (0x00000000u)
06253 
06254 /*----I9 Tokens----*/
06255 #define EDMA3_CCRL_IESR_I9_SET           (0x00000001u)
06256 
06257 #define EDMA3_CCRL_IESR_I8_MASK          (0x00000100u)
06258 #define EDMA3_CCRL_IESR_I8_SHIFT         (0x00000008u)
06259 #define EDMA3_CCRL_IESR_I8_RESETVAL      (0x00000000u)
06260 
06261 /*----I8 Tokens----*/
06262 #define EDMA3_CCRL_IESR_I8_SET           (0x00000001u)
06263 
06264 #define EDMA3_CCRL_IESR_I7_MASK          (0x00000080u)
06265 #define EDMA3_CCRL_IESR_I7_SHIFT         (0x00000007u)
06266 #define EDMA3_CCRL_IESR_I7_RESETVAL      (0x00000000u)
06267 
06268 /*----I7 Tokens----*/
06269 #define EDMA3_CCRL_IESR_I7_SET           (0x00000001u)
06270 
06271 #define EDMA3_CCRL_IESR_I6_MASK          (0x00000040u)
06272 #define EDMA3_CCRL_IESR_I6_SHIFT         (0x00000006u)
06273 #define EDMA3_CCRL_IESR_I6_RESETVAL      (0x00000000u)
06274 
06275 /*----I6 Tokens----*/
06276 #define EDMA3_CCRL_IESR_I6_SET           (0x00000001u)
06277 
06278 #define EDMA3_CCRL_IESR_I5_MASK          (0x00000020u)
06279 #define EDMA3_CCRL_IESR_I5_SHIFT         (0x00000005u)
06280 #define EDMA3_CCRL_IESR_I5_RESETVAL      (0x00000000u)
06281 
06282 /*----I5 Tokens----*/
06283 #define EDMA3_CCRL_IESR_I5_SET           (0x00000001u)
06284 
06285 #define EDMA3_CCRL_IESR_I4_MASK          (0x00000010u)
06286 #define EDMA3_CCRL_IESR_I4_SHIFT         (0x00000004u)
06287 #define EDMA3_CCRL_IESR_I4_RESETVAL      (0x00000000u)
06288 
06289 /*----I4 Tokens----*/
06290 #define EDMA3_CCRL_IESR_I4_SET           (0x00000001u)
06291 
06292 #define EDMA3_CCRL_IESR_I3_MASK          (0x00000008u)
06293 #define EDMA3_CCRL_IESR_I3_SHIFT         (0x00000003u)
06294 #define EDMA3_CCRL_IESR_I3_RESETVAL      (0x00000000u)
06295 
06296 /*----I3 Tokens----*/
06297 #define EDMA3_CCRL_IESR_I3_SET           (0x00000001u)
06298 
06299 #define EDMA3_CCRL_IESR_I2_MASK          (0x00000004u)
06300 #define EDMA3_CCRL_IESR_I2_SHIFT         (0x00000002u)
06301 #define EDMA3_CCRL_IESR_I2_RESETVAL      (0x00000000u)
06302 
06303 /*----I2 Tokens----*/
06304 #define EDMA3_CCRL_IESR_I2_SET           (0x00000001u)
06305 
06306 #define EDMA3_CCRL_IESR_I1_MASK          (0x00000002u)
06307 #define EDMA3_CCRL_IESR_I1_SHIFT         (0x00000001u)
06308 #define EDMA3_CCRL_IESR_I1_RESETVAL      (0x00000000u)
06309 
06310 /*----I1 Tokens----*/
06311 #define EDMA3_CCRL_IESR_I1_SET           (0x00000001u)
06312 
06313 #define EDMA3_CCRL_IESR_I0_MASK          (0x00000001u)
06314 #define EDMA3_CCRL_IESR_I0_SHIFT         (0x00000000u)
06315 #define EDMA3_CCRL_IESR_I0_RESETVAL      (0x00000000u)
06316 
06317 /*----I0 Tokens----*/
06318 #define EDMA3_CCRL_IESR_I0_SET           (0x00000001u)
06319 
06320 #define EDMA3_CCRL_IESR_RESETVAL         (0x00000000u)
06321 
06322 /* IESRH */
06323 
06324 #define EDMA3_CCRL_IESRH_I63_MASK        (0x80000000u)
06325 #define EDMA3_CCRL_IESRH_I63_SHIFT       (0x0000001Fu)
06326 #define EDMA3_CCRL_IESRH_I63_RESETVAL    (0x00000000u)
06327 
06328 /*----I63 Tokens----*/
06329 #define EDMA3_CCRL_IESRH_I63_SET         (0x00000001u)
06330 
06331 #define EDMA3_CCRL_IESRH_I62_MASK        (0x40000000u)
06332 #define EDMA3_CCRL_IESRH_I62_SHIFT       (0x0000001Eu)
06333 #define EDMA3_CCRL_IESRH_I62_RESETVAL    (0x00000000u)
06334 
06335 /*----I62 Tokens----*/
06336 #define EDMA3_CCRL_IESRH_I62_SET         (0x00000001u)
06337 
06338 #define EDMA3_CCRL_IESRH_I61_MASK        (0x20000000u)
06339 #define EDMA3_CCRL_IESRH_I61_SHIFT       (0x0000001Du)
06340 #define EDMA3_CCRL_IESRH_I61_RESETVAL    (0x00000000u)
06341 
06342 /*----I61 Tokens----*/
06343 #define EDMA3_CCRL_IESRH_I61_SET         (0x00000001u)
06344 
06345 #define EDMA3_CCRL_IESRH_I60_MASK        (0x10000000u)
06346 #define EDMA3_CCRL_IESRH_I60_SHIFT       (0x0000001Cu)
06347 #define EDMA3_CCRL_IESRH_I60_RESETVAL    (0x00000000u)
06348 
06349 /*----I60 Tokens----*/
06350 #define EDMA3_CCRL_IESRH_I60_SET         (0x00000001u)
06351 
06352 #define EDMA3_CCRL_IESRH_I59_MASK        (0x08000000u)
06353 #define EDMA3_CCRL_IESRH_I59_SHIFT       (0x0000001Bu)
06354 #define EDMA3_CCRL_IESRH_I59_RESETVAL    (0x00000000u)
06355 
06356 /*----I59 Tokens----*/
06357 #define EDMA3_CCRL_IESRH_I59_SET         (0x00000001u)
06358 
06359 #define EDMA3_CCRL_IESRH_I58_MASK        (0x04000000u)
06360 #define EDMA3_CCRL_IESRH_I58_SHIFT       (0x0000001Au)
06361 #define EDMA3_CCRL_IESRH_I58_RESETVAL    (0x00000000u)
06362 
06363 /*----I58 Tokens----*/
06364 #define EDMA3_CCRL_IESRH_I58_SET         (0x00000001u)
06365 
06366 #define EDMA3_CCRL_IESRH_I57_MASK        (0x02000000u)
06367 #define EDMA3_CCRL_IESRH_I57_SHIFT       (0x00000019u)
06368 #define EDMA3_CCRL_IESRH_I57_RESETVAL    (0x00000000u)
06369 
06370 /*----I57 Tokens----*/
06371 #define EDMA3_CCRL_IESRH_I57_SET         (0x00000001u)
06372 
06373 #define EDMA3_CCRL_IESRH_I56_MASK        (0x01000000u)
06374 #define EDMA3_CCRL_IESRH_I56_SHIFT       (0x00000018u)
06375 #define EDMA3_CCRL_IESRH_I56_RESETVAL    (0x00000000u)
06376 
06377 /*----I56 Tokens----*/
06378 #define EDMA3_CCRL_IESRH_I56_SET         (0x00000001u)
06379 
06380 #define EDMA3_CCRL_IESRH_I55_MASK        (0x00800000u)
06381 #define EDMA3_CCRL_IESRH_I55_SHIFT       (0x00000017u)
06382 #define EDMA3_CCRL_IESRH_I55_RESETVAL    (0x00000000u)
06383 
06384 /*----I55 Tokens----*/
06385 #define EDMA3_CCRL_IESRH_I55_SET         (0x00000001u)
06386 
06387 #define EDMA3_CCRL_IESRH_I54_MASK        (0x00400000u)
06388 #define EDMA3_CCRL_IESRH_I54_SHIFT       (0x00000016u)
06389 #define EDMA3_CCRL_IESRH_I54_RESETVAL    (0x00000000u)
06390 
06391 /*----I54 Tokens----*/
06392 #define EDMA3_CCRL_IESRH_I54_SET         (0x00000001u)
06393 
06394 #define EDMA3_CCRL_IESRH_I53_MASK        (0x00200000u)
06395 #define EDMA3_CCRL_IESRH_I53_SHIFT       (0x00000015u)
06396 #define EDMA3_CCRL_IESRH_I53_RESETVAL    (0x00000000u)
06397 
06398 /*----I53 Tokens----*/
06399 #define EDMA3_CCRL_IESRH_I53_SET         (0x00000001u)
06400 
06401 #define EDMA3_CCRL_IESRH_I52_MASK        (0x00100000u)
06402 #define EDMA3_CCRL_IESRH_I52_SHIFT       (0x00000014u)
06403 #define EDMA3_CCRL_IESRH_I52_RESETVAL    (0x00000000u)
06404 
06405 /*----I52 Tokens----*/
06406 #define EDMA3_CCRL_IESRH_I52_SET         (0x00000001u)
06407 
06408 #define EDMA3_CCRL_IESRH_I51_MASK        (0x00080000u)
06409 #define EDMA3_CCRL_IESRH_I51_SHIFT       (0x00000013u)
06410 #define EDMA3_CCRL_IESRH_I51_RESETVAL    (0x00000000u)
06411 
06412 /*----I51 Tokens----*/
06413 #define EDMA3_CCRL_IESRH_I51_SET         (0x00000001u)
06414 
06415 #define EDMA3_CCRL_IESRH_I50_MASK        (0x00040000u)
06416 #define EDMA3_CCRL_IESRH_I50_SHIFT       (0x00000012u)
06417 #define EDMA3_CCRL_IESRH_I50_RESETVAL    (0x00000000u)
06418 
06419 /*----I50 Tokens----*/
06420 #define EDMA3_CCRL_IESRH_I50_SET         (0x00000001u)
06421 
06422 #define EDMA3_CCRL_IESRH_I49_MASK        (0x00020000u)
06423 #define EDMA3_CCRL_IESRH_I49_SHIFT       (0x00000011u)
06424 #define EDMA3_CCRL_IESRH_I49_RESETVAL    (0x00000000u)
06425 
06426 /*----I49 Tokens----*/
06427 #define EDMA3_CCRL_IESRH_I49_SET         (0x00000001u)
06428 
06429 #define EDMA3_CCRL_IESRH_I48_MASK        (0x00010000u)
06430 #define EDMA3_CCRL_IESRH_I48_SHIFT       (0x00000010u)
06431 #define EDMA3_CCRL_IESRH_I48_RESETVAL    (0x00000000u)
06432 
06433 /*----I48 Tokens----*/
06434 #define EDMA3_CCRL_IESRH_I48_SET         (0x00000001u)
06435 
06436 #define EDMA3_CCRL_IESRH_I47_MASK        (0x00008000u)
06437 #define EDMA3_CCRL_IESRH_I47_SHIFT       (0x0000000Fu)
06438 #define EDMA3_CCRL_IESRH_I47_RESETVAL    (0x00000000u)
06439 
06440 /*----I47 Tokens----*/
06441 #define EDMA3_CCRL_IESRH_I47_SET         (0x00000001u)
06442 
06443 #define EDMA3_CCRL_IESRH_I46_MASK        (0x00004000u)
06444 #define EDMA3_CCRL_IESRH_I46_SHIFT       (0x0000000Eu)
06445 #define EDMA3_CCRL_IESRH_I46_RESETVAL    (0x00000000u)
06446 
06447 /*----I46 Tokens----*/
06448 #define EDMA3_CCRL_IESRH_I46_SET         (0x00000001u)
06449 
06450 #define EDMA3_CCRL_IESRH_I45_MASK        (0x00002000u)
06451 #define EDMA3_CCRL_IESRH_I45_SHIFT       (0x0000000Du)
06452 #define EDMA3_CCRL_IESRH_I45_RESETVAL    (0x00000000u)
06453 
06454 /*----I45 Tokens----*/
06455 #define EDMA3_CCRL_IESRH_I45_SET         (0x00000001u)
06456 
06457 #define EDMA3_CCRL_IESRH_I44_MASK        (0x00001000u)
06458 #define EDMA3_CCRL_IESRH_I44_SHIFT       (0x0000000Cu)
06459 #define EDMA3_CCRL_IESRH_I44_RESETVAL    (0x00000000u)
06460 
06461 /*----I44 Tokens----*/
06462 #define EDMA3_CCRL_IESRH_I44_SET         (0x00000001u)
06463 
06464 #define EDMA3_CCRL_IESRH_I43_MASK        (0x00000800u)
06465 #define EDMA3_CCRL_IESRH_I43_SHIFT       (0x0000000Bu)
06466 #define EDMA3_CCRL_IESRH_I43_RESETVAL    (0x00000000u)
06467 
06468 /*----I43 Tokens----*/
06469 #define EDMA3_CCRL_IESRH_I43_SET         (0x00000001u)
06470 
06471 #define EDMA3_CCRL_IESRH_I42_MASK        (0x00000400u)
06472 #define EDMA3_CCRL_IESRH_I42_SHIFT       (0x0000000Au)
06473 #define EDMA3_CCRL_IESRH_I42_RESETVAL    (0x00000000u)
06474 
06475 /*----I42 Tokens----*/
06476 #define EDMA3_CCRL_IESRH_I42_SET         (0x00000001u)
06477 
06478 #define EDMA3_CCRL_IESRH_I41_MASK        (0x00000200u)
06479 #define EDMA3_CCRL_IESRH_I41_SHIFT       (0x00000009u)
06480 #define EDMA3_CCRL_IESRH_I41_RESETVAL    (0x00000000u)
06481 
06482 /*----I41 Tokens----*/
06483 #define EDMA3_CCRL_IESRH_I41_SET         (0x00000001u)
06484 
06485 #define EDMA3_CCRL_IESRH_I40_MASK        (0x00000100u)
06486 #define EDMA3_CCRL_IESRH_I40_SHIFT       (0x00000008u)
06487 #define EDMA3_CCRL_IESRH_I40_RESETVAL    (0x00000000u)
06488 
06489 /*----I40 Tokens----*/
06490 #define EDMA3_CCRL_IESRH_I40_SET         (0x00000001u)
06491 
06492 #define EDMA3_CCRL_IESRH_I39_MASK        (0x00000080u)
06493 #define EDMA3_CCRL_IESRH_I39_SHIFT       (0x00000007u)
06494 #define EDMA3_CCRL_IESRH_I39_RESETVAL    (0x00000000u)
06495 
06496 /*----I39 Tokens----*/
06497 #define EDMA3_CCRL_IESRH_I39_SET         (0x00000001u)
06498 
06499 #define EDMA3_CCRL_IESRH_I38_MASK        (0x00000040u)
06500 #define EDMA3_CCRL_IESRH_I38_SHIFT       (0x00000006u)
06501 #define EDMA3_CCRL_IESRH_I38_RESETVAL    (0x00000000u)
06502 
06503 /*----I38 Tokens----*/
06504 #define EDMA3_CCRL_IESRH_I38_SET         (0x00000001u)
06505 
06506 #define EDMA3_CCRL_IESRH_I37_MASK        (0x00000020u)
06507 #define EDMA3_CCRL_IESRH_I37_SHIFT       (0x00000005u)
06508 #define EDMA3_CCRL_IESRH_I37_RESETVAL    (0x00000000u)
06509 
06510 /*----I37 Tokens----*/
06511 #define EDMA3_CCRL_IESRH_I37_SET         (0x00000001u)
06512 
06513 #define EDMA3_CCRL_IESRH_I36_MASK        (0x00000010u)
06514 #define EDMA3_CCRL_IESRH_I36_SHIFT       (0x00000004u)
06515 #define EDMA3_CCRL_IESRH_I36_RESETVAL    (0x00000000u)
06516 
06517 /*----I36 Tokens----*/
06518 #define EDMA3_CCRL_IESRH_I36_SET         (0x00000001u)
06519 
06520 #define EDMA3_CCRL_IESRH_I35_MASK        (0x00000008u)
06521 #define EDMA3_CCRL_IESRH_I35_SHIFT       (0x00000003u)
06522 #define EDMA3_CCRL_IESRH_I35_RESETVAL    (0x00000000u)
06523 
06524 /*----I35 Tokens----*/
06525 #define EDMA3_CCRL_IESRH_I35_SET         (0x00000001u)
06526 
06527 #define EDMA3_CCRL_IESRH_I34_MASK        (0x00000004u)
06528 #define EDMA3_CCRL_IESRH_I34_SHIFT       (0x00000002u)
06529 #define EDMA3_CCRL_IESRH_I34_RESETVAL    (0x00000000u)
06530 
06531 /*----I34 Tokens----*/
06532 #define EDMA3_CCRL_IESRH_I34_SET         (0x00000001u)
06533 
06534 #define EDMA3_CCRL_IESRH_I33_MASK        (0x00000002u)
06535 #define EDMA3_CCRL_IESRH_I33_SHIFT       (0x00000001u)
06536 #define EDMA3_CCRL_IESRH_I33_RESETVAL    (0x00000000u)
06537 
06538 /*----I33 Tokens----*/
06539 #define EDMA3_CCRL_IESRH_I33_SET         (0x00000001u)
06540 
06541 #define EDMA3_CCRL_IESRH_I32_MASK        (0x00000001u)
06542 #define EDMA3_CCRL_IESRH_I32_SHIFT       (0x00000000u)
06543 #define EDMA3_CCRL_IESRH_I32_RESETVAL    (0x00000000u)
06544 
06545 /*----I32 Tokens----*/
06546 #define EDMA3_CCRL_IESRH_I32_SET         (0x00000001u)
06547 
06548 #define EDMA3_CCRL_IESRH_RESETVAL        (0x00000000u)
06549 
06550 /* IPR */
06551 
06552 #define EDMA3_CCRL_IPR_I31_MASK          (0x80000000u)
06553 #define EDMA3_CCRL_IPR_I31_SHIFT         (0x0000001Fu)
06554 #define EDMA3_CCRL_IPR_I31_RESETVAL      (0x00000000u)
06555 
06556 #define EDMA3_CCRL_IPR_I30_MASK          (0x40000000u)
06557 #define EDMA3_CCRL_IPR_I30_SHIFT         (0x0000001Eu)
06558 #define EDMA3_CCRL_IPR_I30_RESETVAL      (0x00000000u)
06559 
06560 #define EDMA3_CCRL_IPR_I29_MASK          (0x20000000u)
06561 #define EDMA3_CCRL_IPR_I29_SHIFT         (0x0000001Du)
06562 #define EDMA3_CCRL_IPR_I29_RESETVAL      (0x00000000u)
06563 
06564 #define EDMA3_CCRL_IPR_I28_MASK          (0x10000000u)
06565 #define EDMA3_CCRL_IPR_I28_SHIFT         (0x0000001Cu)
06566 #define EDMA3_CCRL_IPR_I28_RESETVAL      (0x00000000u)
06567 
06568 #define EDMA3_CCRL_IPR_I27_MASK          (0x08000000u)
06569 #define EDMA3_CCRL_IPR_I27_SHIFT         (0x0000001Bu)
06570 #define EDMA3_CCRL_IPR_I27_RESETVAL      (0x00000000u)
06571 
06572 #define EDMA3_CCRL_IPR_I26_MASK          (0x04000000u)
06573 #define EDMA3_CCRL_IPR_I26_SHIFT         (0x0000001Au)
06574 #define EDMA3_CCRL_IPR_I26_RESETVAL      (0x00000000u)
06575 
06576 #define EDMA3_CCRL_IPR_I25_MASK          (0x02000000u)
06577 #define EDMA3_CCRL_IPR_I25_SHIFT         (0x00000019u)
06578 #define EDMA3_CCRL_IPR_I25_RESETVAL      (0x00000000u)
06579 
06580 #define EDMA3_CCRL_IPR_I24_MASK          (0x01000000u)
06581 #define EDMA3_CCRL_IPR_I24_SHIFT         (0x00000018u)
06582 #define EDMA3_CCRL_IPR_I24_RESETVAL      (0x00000000u)
06583 
06584 #define EDMA3_CCRL_IPR_I23_MASK          (0x00800000u)
06585 #define EDMA3_CCRL_IPR_I23_SHIFT         (0x00000017u)
06586 #define EDMA3_CCRL_IPR_I23_RESETVAL      (0x00000000u)
06587 
06588 #define EDMA3_CCRL_IPR_I22_MASK          (0x00400000u)
06589 #define EDMA3_CCRL_IPR_I22_SHIFT         (0x00000016u)
06590 #define EDMA3_CCRL_IPR_I22_RESETVAL      (0x00000000u)
06591 
06592 #define EDMA3_CCRL_IPR_I21_MASK          (0x00200000u)
06593 #define EDMA3_CCRL_IPR_I21_SHIFT         (0x00000015u)
06594 #define EDMA3_CCRL_IPR_I21_RESETVAL      (0x00000000u)
06595 
06596 #define EDMA3_CCRL_IPR_I20_MASK          (0x00100000u)
06597 #define EDMA3_CCRL_IPR_I20_SHIFT         (0x00000014u)
06598 #define EDMA3_CCRL_IPR_I20_RESETVAL      (0x00000000u)
06599 
06600 #define EDMA3_CCRL_IPR_I19_MASK          (0x00080000u)
06601 #define EDMA3_CCRL_IPR_I19_SHIFT         (0x00000013u)
06602 #define EDMA3_CCRL_IPR_I19_RESETVAL      (0x00000000u)
06603 
06604 #define EDMA3_CCRL_IPR_I18_MASK          (0x00040000u)
06605 #define EDMA3_CCRL_IPR_I18_SHIFT         (0x00000012u)
06606 #define EDMA3_CCRL_IPR_I18_RESETVAL      (0x00000000u)
06607 
06608 #define EDMA3_CCRL_IPR_I17_MASK          (0x00020000u)
06609 #define EDMA3_CCRL_IPR_I17_SHIFT         (0x00000011u)
06610 #define EDMA3_CCRL_IPR_I17_RESETVAL      (0x00000000u)
06611 
06612 #define EDMA3_CCRL_IPR_I16_MASK          (0x00010000u)
06613 #define EDMA3_CCRL_IPR_I16_SHIFT         (0x00000010u)
06614 #define EDMA3_CCRL_IPR_I16_RESETVAL      (0x00000000u)
06615 
06616 #define EDMA3_CCRL_IPR_I15_MASK          (0x00008000u)
06617 #define EDMA3_CCRL_IPR_I15_SHIFT         (0x0000000Fu)
06618 #define EDMA3_CCRL_IPR_I15_RESETVAL      (0x00000000u)
06619 
06620 #define EDMA3_CCRL_IPR_I14_MASK          (0x00004000u)
06621 #define EDMA3_CCRL_IPR_I14_SHIFT         (0x0000000Eu)
06622 #define EDMA3_CCRL_IPR_I14_RESETVAL      (0x00000000u)
06623 
06624 #define EDMA3_CCRL_IPR_I13_MASK          (0x00002000u)
06625 #define EDMA3_CCRL_IPR_I13_SHIFT         (0x0000000Du)
06626 #define EDMA3_CCRL_IPR_I13_RESETVAL      (0x00000000u)
06627 
06628 #define EDMA3_CCRL_IPR_I12_MASK          (0x00001000u)
06629 #define EDMA3_CCRL_IPR_I12_SHIFT         (0x0000000Cu)
06630 #define EDMA3_CCRL_IPR_I12_RESETVAL      (0x00000000u)
06631 
06632 #define EDMA3_CCRL_IPR_I11_MASK          (0x00000800u)
06633 #define EDMA3_CCRL_IPR_I11_SHIFT         (0x0000000Bu)
06634 #define EDMA3_CCRL_IPR_I11_RESETVAL      (0x00000000u)
06635 
06636 #define EDMA3_CCRL_IPR_I10_MASK          (0x00000400u)
06637 #define EDMA3_CCRL_IPR_I10_SHIFT         (0x0000000Au)
06638 #define EDMA3_CCRL_IPR_I10_RESETVAL      (0x00000000u)
06639 
06640 #define EDMA3_CCRL_IPR_I9_MASK           (0x00000200u)
06641 #define EDMA3_CCRL_IPR_I9_SHIFT          (0x00000009u)
06642 #define EDMA3_CCRL_IPR_I9_RESETVAL       (0x00000000u)
06643 
06644 #define EDMA3_CCRL_IPR_I8_MASK           (0x00000100u)
06645 #define EDMA3_CCRL_IPR_I8_SHIFT          (0x00000008u)
06646 #define EDMA3_CCRL_IPR_I8_RESETVAL       (0x00000000u)
06647 
06648 #define EDMA3_CCRL_IPR_I7_MASK           (0x00000080u)
06649 #define EDMA3_CCRL_IPR_I7_SHIFT          (0x00000007u)
06650 #define EDMA3_CCRL_IPR_I7_RESETVAL       (0x00000000u)
06651 
06652 #define EDMA3_CCRL_IPR_I6_MASK           (0x00000040u)
06653 #define EDMA3_CCRL_IPR_I6_SHIFT          (0x00000006u)
06654 #define EDMA3_CCRL_IPR_I6_RESETVAL       (0x00000000u)
06655 
06656 #define EDMA3_CCRL_IPR_I5_MASK           (0x00000020u)
06657 #define EDMA3_CCRL_IPR_I5_SHIFT          (0x00000005u)
06658 #define EDMA3_CCRL_IPR_I5_RESETVAL       (0x00000000u)
06659 
06660 #define EDMA3_CCRL_IPR_I4_MASK           (0x00000010u)
06661 #define EDMA3_CCRL_IPR_I4_SHIFT          (0x00000004u)
06662 #define EDMA3_CCRL_IPR_I4_RESETVAL       (0x00000000u)
06663 
06664 #define EDMA3_CCRL_IPR_I3_MASK           (0x00000008u)
06665 #define EDMA3_CCRL_IPR_I3_SHIFT          (0x00000003u)
06666 #define EDMA3_CCRL_IPR_I3_RESETVAL       (0x00000000u)
06667 
06668 #define EDMA3_CCRL_IPR_I2_MASK           (0x00000004u)
06669 #define EDMA3_CCRL_IPR_I2_SHIFT          (0x00000002u)
06670 #define EDMA3_CCRL_IPR_I2_RESETVAL       (0x00000000u)
06671 
06672 #define EDMA3_CCRL_IPR_I1_MASK           (0x00000002u)
06673 #define EDMA3_CCRL_IPR_I1_SHIFT          (0x00000001u)
06674 #define EDMA3_CCRL_IPR_I1_RESETVAL       (0x00000000u)
06675 
06676 #define EDMA3_CCRL_IPR_I0_MASK           (0x00000001u)
06677 #define EDMA3_CCRL_IPR_I0_SHIFT          (0x00000000u)
06678 #define EDMA3_CCRL_IPR_I0_RESETVAL       (0x00000000u)
06679 
06680 #define EDMA3_CCRL_IPR_RESETVAL          (0x00000000u)
06681 
06682 /* IPRH */
06683 
06684 #define EDMA3_CCRL_IPRH_I63_MASK         (0x80000000u)
06685 #define EDMA3_CCRL_IPRH_I63_SHIFT        (0x0000001Fu)
06686 #define EDMA3_CCRL_IPRH_I63_RESETVAL     (0x00000000u)
06687 
06688 #define EDMA3_CCRL_IPRH_I62_MASK         (0x40000000u)
06689 #define EDMA3_CCRL_IPRH_I62_SHIFT        (0x0000001Eu)
06690 #define EDMA3_CCRL_IPRH_I62_RESETVAL     (0x00000000u)
06691 
06692 #define EDMA3_CCRL_IPRH_I61_MASK         (0x20000000u)
06693 #define EDMA3_CCRL_IPRH_I61_SHIFT        (0x0000001Du)
06694 #define EDMA3_CCRL_IPRH_I61_RESETVAL     (0x00000000u)
06695 
06696 #define EDMA3_CCRL_IPRH_I60_MASK         (0x10000000u)
06697 #define EDMA3_CCRL_IPRH_I60_SHIFT        (0x0000001Cu)
06698 #define EDMA3_CCRL_IPRH_I60_RESETVAL     (0x00000000u)
06699 
06700 #define EDMA3_CCRL_IPRH_I59_MASK         (0x08000000u)
06701 #define EDMA3_CCRL_IPRH_I59_SHIFT        (0x0000001Bu)
06702 #define EDMA3_CCRL_IPRH_I59_RESETVAL     (0x00000000u)
06703 
06704 #define EDMA3_CCRL_IPRH_I58_MASK         (0x04000000u)
06705 #define EDMA3_CCRL_IPRH_I58_SHIFT        (0x0000001Au)
06706 #define EDMA3_CCRL_IPRH_I58_RESETVAL     (0x00000000u)
06707 
06708 #define EDMA3_CCRL_IPRH_I57_MASK         (0x02000000u)
06709 #define EDMA3_CCRL_IPRH_I57_SHIFT        (0x00000019u)
06710 #define EDMA3_CCRL_IPRH_I57_RESETVAL     (0x00000000u)
06711 
06712 #define EDMA3_CCRL_IPRH_I56_MASK         (0x01000000u)
06713 #define EDMA3_CCRL_IPRH_I56_SHIFT        (0x00000018u)
06714 #define EDMA3_CCRL_IPRH_I56_RESETVAL     (0x00000000u)
06715 
06716 #define EDMA3_CCRL_IPRH_I55_MASK         (0x00800000u)
06717 #define EDMA3_CCRL_IPRH_I55_SHIFT        (0x00000017u)
06718 #define EDMA3_CCRL_IPRH_I55_RESETVAL     (0x00000000u)
06719 
06720 #define EDMA3_CCRL_IPRH_I54_MASK         (0x00400000u)
06721 #define EDMA3_CCRL_IPRH_I54_SHIFT        (0x00000016u)
06722 #define EDMA3_CCRL_IPRH_I54_RESETVAL     (0x00000000u)
06723 
06724 #define EDMA3_CCRL_IPRH_I53_MASK         (0x00200000u)
06725 #define EDMA3_CCRL_IPRH_I53_SHIFT        (0x00000015u)
06726 #define EDMA3_CCRL_IPRH_I53_RESETVAL     (0x00000000u)
06727 
06728 #define EDMA3_CCRL_IPRH_I52_MASK         (0x00100000u)
06729 #define EDMA3_CCRL_IPRH_I52_SHIFT        (0x00000014u)
06730 #define EDMA3_CCRL_IPRH_I52_RESETVAL     (0x00000000u)
06731 
06732 #define EDMA3_CCRL_IPRH_I51_MASK         (0x00080000u)
06733 #define EDMA3_CCRL_IPRH_I51_SHIFT        (0x00000013u)
06734 #define EDMA3_CCRL_IPRH_I51_RESETVAL     (0x00000000u)
06735 
06736 #define EDMA3_CCRL_IPRH_I50_MASK         (0x00040000u)
06737 #define EDMA3_CCRL_IPRH_I50_SHIFT        (0x00000012u)
06738 #define EDMA3_CCRL_IPRH_I50_RESETVAL     (0x00000000u)
06739 
06740 #define EDMA3_CCRL_IPRH_I49_MASK         (0x00020000u)
06741 #define EDMA3_CCRL_IPRH_I49_SHIFT        (0x00000011u)
06742 #define EDMA3_CCRL_IPRH_I49_RESETVAL     (0x00000000u)
06743 
06744 #define EDMA3_CCRL_IPRH_I48_MASK         (0x00010000u)
06745 #define EDMA3_CCRL_IPRH_I48_SHIFT        (0x00000010u)
06746 #define EDMA3_CCRL_IPRH_I48_RESETVAL     (0x00000000u)
06747 
06748 #define EDMA3_CCRL_IPRH_I47_MASK         (0x00008000u)
06749 #define EDMA3_CCRL_IPRH_I47_SHIFT        (0x0000000Fu)
06750 #define EDMA3_CCRL_IPRH_I47_RESETVAL     (0x00000000u)
06751 
06752 #define EDMA3_CCRL_IPRH_I46_MASK         (0x00004000u)
06753 #define EDMA3_CCRL_IPRH_I46_SHIFT        (0x0000000Eu)
06754 #define EDMA3_CCRL_IPRH_I46_RESETVAL     (0x00000000u)
06755 
06756 #define EDMA3_CCRL_IPRH_I45_MASK         (0x00002000u)
06757 #define EDMA3_CCRL_IPRH_I45_SHIFT        (0x0000000Du)
06758 #define EDMA3_CCRL_IPRH_I45_RESETVAL     (0x00000000u)
06759 
06760 #define EDMA3_CCRL_IPRH_I44_MASK         (0x00001000u)
06761 #define EDMA3_CCRL_IPRH_I44_SHIFT        (0x0000000Cu)
06762 #define EDMA3_CCRL_IPRH_I44_RESETVAL     (0x00000000u)
06763 
06764 #define EDMA3_CCRL_IPRH_I43_MASK         (0x00000800u)
06765 #define EDMA3_CCRL_IPRH_I43_SHIFT        (0x0000000Bu)
06766 #define EDMA3_CCRL_IPRH_I43_RESETVAL     (0x00000000u)
06767 
06768 #define EDMA3_CCRL_IPRH_I42_MASK         (0x00000400u)
06769 #define EDMA3_CCRL_IPRH_I42_SHIFT        (0x0000000Au)
06770 #define EDMA3_CCRL_IPRH_I42_RESETVAL     (0x00000000u)
06771 
06772 #define EDMA3_CCRL_IPRH_I41_MASK         (0x00000200u)
06773 #define EDMA3_CCRL_IPRH_I41_SHIFT        (0x00000009u)
06774 #define EDMA3_CCRL_IPRH_I41_RESETVAL     (0x00000000u)
06775 
06776 #define EDMA3_CCRL_IPRH_I40_MASK         (0x00000100u)
06777 #define EDMA3_CCRL_IPRH_I40_SHIFT        (0x00000008u)
06778 #define EDMA3_CCRL_IPRH_I40_RESETVAL     (0x00000000u)
06779 
06780 #define EDMA3_CCRL_IPRH_I39_MASK         (0x00000080u)
06781 #define EDMA3_CCRL_IPRH_I39_SHIFT        (0x00000007u)
06782 #define EDMA3_CCRL_IPRH_I39_RESETVAL     (0x00000000u)
06783 
06784 #define EDMA3_CCRL_IPRH_I38_MASK         (0x00000040u)
06785 #define EDMA3_CCRL_IPRH_I38_SHIFT        (0x00000006u)
06786 #define EDMA3_CCRL_IPRH_I38_RESETVAL     (0x00000000u)
06787 
06788 #define EDMA3_CCRL_IPRH_I37_MASK         (0x00000020u)
06789 #define EDMA3_CCRL_IPRH_I37_SHIFT        (0x00000005u)
06790 #define EDMA3_CCRL_IPRH_I37_RESETVAL     (0x00000000u)
06791 
06792 #define EDMA3_CCRL_IPRH_I36_MASK         (0x00000010u)
06793 #define EDMA3_CCRL_IPRH_I36_SHIFT        (0x00000004u)
06794 #define EDMA3_CCRL_IPRH_I36_RESETVAL     (0x00000000u)
06795 
06796 #define EDMA3_CCRL_IPRH_I35_MASK         (0x00000008u)
06797 #define EDMA3_CCRL_IPRH_I35_SHIFT        (0x00000003u)
06798 #define EDMA3_CCRL_IPRH_I35_RESETVAL     (0x00000000u)
06799 
06800 #define EDMA3_CCRL_IPRH_I34_MASK         (0x00000004u)
06801 #define EDMA3_CCRL_IPRH_I34_SHIFT        (0x00000002u)
06802 #define EDMA3_CCRL_IPRH_I34_RESETVAL     (0x00000000u)
06803 
06804 #define EDMA3_CCRL_IPRH_I33_MASK         (0x00000002u)
06805 #define EDMA3_CCRL_IPRH_I33_SHIFT        (0x00000001u)
06806 #define EDMA3_CCRL_IPRH_I33_RESETVAL     (0x00000000u)
06807 
06808 #define EDMA3_CCRL_IPRH_I32_MASK         (0x00000001u)
06809 #define EDMA3_CCRL_IPRH_I32_SHIFT        (0x00000000u)
06810 #define EDMA3_CCRL_IPRH_I32_RESETVAL     (0x00000000u)
06811 
06812 #define EDMA3_CCRL_IPRH_RESETVAL         (0x00000000u)
06813 
06814 /* ICR */
06815 
06816 #define EDMA3_CCRL_ICR_I31_MASK          (0x80000000u)
06817 #define EDMA3_CCRL_ICR_I31_SHIFT         (0x0000001Fu)
06818 #define EDMA3_CCRL_ICR_I31_RESETVAL      (0x00000000u)
06819 
06820 /*----I31 Tokens----*/
06821 #define EDMA3_CCRL_ICR_I31_CLEAR         (0x00000001u)
06822 
06823 #define EDMA3_CCRL_ICR_I30_MASK          (0x40000000u)
06824 #define EDMA3_CCRL_ICR_I30_SHIFT         (0x0000001Eu)
06825 #define EDMA3_CCRL_ICR_I30_RESETVAL      (0x00000000u)
06826 
06827 /*----I30 Tokens----*/
06828 #define EDMA3_CCRL_ICR_I30_CLEAR         (0x00000001u)
06829 
06830 #define EDMA3_CCRL_ICR_I29_MASK          (0x20000000u)
06831 #define EDMA3_CCRL_ICR_I29_SHIFT         (0x0000001Du)
06832 #define EDMA3_CCRL_ICR_I29_RESETVAL      (0x00000000u)
06833 
06834 /*----I29 Tokens----*/
06835 #define EDMA3_CCRL_ICR_I29_CLEAR         (0x00000001u)
06836 
06837 #define EDMA3_CCRL_ICR_I28_MASK          (0x10000000u)
06838 #define EDMA3_CCRL_ICR_I28_SHIFT         (0x0000001Cu)
06839 #define EDMA3_CCRL_ICR_I28_RESETVAL      (0x00000000u)
06840 
06841 /*----I28 Tokens----*/
06842 #define EDMA3_CCRL_ICR_I28_CLEAR         (0x00000001u)
06843 
06844 #define EDMA3_CCRL_ICR_I27_MASK          (0x08000000u)
06845 #define EDMA3_CCRL_ICR_I27_SHIFT         (0x0000001Bu)
06846 #define EDMA3_CCRL_ICR_I27_RESETVAL      (0x00000000u)
06847 
06848 /*----I27 Tokens----*/
06849 #define EDMA3_CCRL_ICR_I27_CLEAR         (0x00000001u)
06850 
06851 #define EDMA3_CCRL_ICR_I26_MASK          (0x04000000u)
06852 #define EDMA3_CCRL_ICR_I26_SHIFT         (0x0000001Au)
06853 #define EDMA3_CCRL_ICR_I26_RESETVAL      (0x00000000u)
06854 
06855 /*----I26 Tokens----*/
06856 #define EDMA3_CCRL_ICR_I26_CLEAR         (0x00000001u)
06857 
06858 #define EDMA3_CCRL_ICR_I25_MASK          (0x02000000u)
06859 #define EDMA3_CCRL_ICR_I25_SHIFT         (0x00000019u)
06860 #define EDMA3_CCRL_ICR_I25_RESETVAL      (0x00000000u)
06861 
06862 /*----I25 Tokens----*/
06863 #define EDMA3_CCRL_ICR_I25_CLEAR         (0x00000001u)
06864 
06865 #define EDMA3_CCRL_ICR_I24_MASK          (0x01000000u)
06866 #define EDMA3_CCRL_ICR_I24_SHIFT         (0x00000018u)
06867 #define EDMA3_CCRL_ICR_I24_RESETVAL      (0x00000000u)
06868 
06869 /*----I24 Tokens----*/
06870 #define EDMA3_CCRL_ICR_I24_CLEAR         (0x00000001u)
06871 
06872 #define EDMA3_CCRL_ICR_I23_MASK          (0x00800000u)
06873 #define EDMA3_CCRL_ICR_I23_SHIFT         (0x00000017u)
06874 #define EDMA3_CCRL_ICR_I23_RESETVAL      (0x00000000u)
06875 
06876 /*----I23 Tokens----*/
06877 #define EDMA3_CCRL_ICR_I23_CLEAR         (0x00000001u)
06878 
06879 #define EDMA3_CCRL_ICR_I22_MASK          (0x00400000u)
06880 #define EDMA3_CCRL_ICR_I22_SHIFT         (0x00000016u)
06881 #define EDMA3_CCRL_ICR_I22_RESETVAL      (0x00000000u)
06882 
06883 /*----I22 Tokens----*/
06884 #define EDMA3_CCRL_ICR_I22_CLEAR         (0x00000001u)
06885 
06886 #define EDMA3_CCRL_ICR_I21_MASK          (0x00200000u)
06887 #define EDMA3_CCRL_ICR_I21_SHIFT         (0x00000015u)
06888 #define EDMA3_CCRL_ICR_I21_RESETVAL      (0x00000000u)
06889 
06890 /*----I21 Tokens----*/
06891 #define EDMA3_CCRL_ICR_I21_CLEAR         (0x00000001u)
06892 
06893 #define EDMA3_CCRL_ICR_I20_MASK          (0x00100000u)
06894 #define EDMA3_CCRL_ICR_I20_SHIFT         (0x00000014u)
06895 #define EDMA3_CCRL_ICR_I20_RESETVAL      (0x00000000u)
06896 
06897 /*----I20 Tokens----*/
06898 #define EDMA3_CCRL_ICR_I20_CLEAR         (0x00000001u)
06899 
06900 #define EDMA3_CCRL_ICR_I19_MASK          (0x00080000u)
06901 #define EDMA3_CCRL_ICR_I19_SHIFT         (0x00000013u)
06902 #define EDMA3_CCRL_ICR_I19_RESETVAL      (0x00000000u)
06903 
06904 /*----I19 Tokens----*/
06905 #define EDMA3_CCRL_ICR_I19_CLEAR         (0x00000001u)
06906 
06907 #define EDMA3_CCRL_ICR_I18_MASK          (0x00040000u)
06908 #define EDMA3_CCRL_ICR_I18_SHIFT         (0x00000012u)
06909 #define EDMA3_CCRL_ICR_I18_RESETVAL      (0x00000000u)
06910 
06911 /*----I18 Tokens----*/
06912 #define EDMA3_CCRL_ICR_I18_CLEAR         (0x00000001u)
06913 
06914 #define EDMA3_CCRL_ICR_I17_MASK          (0x00020000u)
06915 #define EDMA3_CCRL_ICR_I17_SHIFT         (0x00000011u)
06916 #define EDMA3_CCRL_ICR_I17_RESETVAL      (0x00000000u)
06917 
06918 /*----I17 Tokens----*/
06919 #define EDMA3_CCRL_ICR_I17_CLEAR         (0x00000001u)
06920 
06921 #define EDMA3_CCRL_ICR_I16_MASK          (0x00010000u)
06922 #define EDMA3_CCRL_ICR_I16_SHIFT         (0x00000010u)
06923 #define EDMA3_CCRL_ICR_I16_RESETVAL      (0x00000000u)
06924 
06925 /*----I16 Tokens----*/
06926 #define EDMA3_CCRL_ICR_I16_CLEAR         (0x00000001u)
06927 
06928 #define EDMA3_CCRL_ICR_I15_MASK          (0x00008000u)
06929 #define EDMA3_CCRL_ICR_I15_SHIFT         (0x0000000Fu)
06930 #define EDMA3_CCRL_ICR_I15_RESETVAL      (0x00000000u)
06931 
06932 /*----I15 Tokens----*/
06933 #define EDMA3_CCRL_ICR_I15_CLEAR         (0x00000001u)
06934 
06935 #define EDMA3_CCRL_ICR_I14_MASK          (0x00004000u)
06936 #define EDMA3_CCRL_ICR_I14_SHIFT         (0x0000000Eu)
06937 #define EDMA3_CCRL_ICR_I14_RESETVAL      (0x00000000u)
06938 
06939 /*----I14 Tokens----*/
06940 #define EDMA3_CCRL_ICR_I14_CLEAR         (0x00000001u)
06941 
06942 #define EDMA3_CCRL_ICR_I13_MASK          (0x00002000u)
06943 #define EDMA3_CCRL_ICR_I13_SHIFT         (0x0000000Du)
06944 #define EDMA3_CCRL_ICR_I13_RESETVAL      (0x00000000u)
06945 
06946 /*----I13 Tokens----*/
06947 #define EDMA3_CCRL_ICR_I13_CLEAR         (0x00000001u)
06948 
06949 #define EDMA3_CCRL_ICR_I12_MASK          (0x00001000u)
06950 #define EDMA3_CCRL_ICR_I12_SHIFT         (0x0000000Cu)
06951 #define EDMA3_CCRL_ICR_I12_RESETVAL      (0x00000000u)
06952 
06953 /*----I12 Tokens----*/
06954 #define EDMA3_CCRL_ICR_I12_CLEAR         (0x00000001u)
06955 
06956 #define EDMA3_CCRL_ICR_I11_MASK          (0x00000800u)
06957 #define EDMA3_CCRL_ICR_I11_SHIFT         (0x0000000Bu)
06958 #define EDMA3_CCRL_ICR_I11_RESETVAL      (0x00000000u)
06959 
06960 /*----I11 Tokens----*/
06961 #define EDMA3_CCRL_ICR_I11_CLEAR         (0x00000001u)
06962 
06963 #define EDMA3_CCRL_ICR_I10_MASK          (0x00000400u)
06964 #define EDMA3_CCRL_ICR_I10_SHIFT         (0x0000000Au)
06965 #define EDMA3_CCRL_ICR_I10_RESETVAL      (0x00000000u)
06966 
06967 /*----I10 Tokens----*/
06968 #define EDMA3_CCRL_ICR_I10_CLEAR         (0x00000001u)
06969 
06970 #define EDMA3_CCRL_ICR_I9_MASK           (0x00000200u)
06971 #define EDMA3_CCRL_ICR_I9_SHIFT          (0x00000009u)
06972 #define EDMA3_CCRL_ICR_I9_RESETVAL       (0x00000000u)
06973 
06974 /*----I9 Tokens----*/
06975 #define EDMA3_CCRL_ICR_I9_CLEAR          (0x00000001u)
06976 
06977 #define EDMA3_CCRL_ICR_I8_MASK           (0x00000100u)
06978 #define EDMA3_CCRL_ICR_I8_SHIFT          (0x00000008u)
06979 #define EDMA3_CCRL_ICR_I8_RESETVAL       (0x00000000u)
06980 
06981 /*----I8 Tokens----*/
06982 #define EDMA3_CCRL_ICR_I8_CLEAR          (0x00000001u)
06983 
06984 #define EDMA3_CCRL_ICR_I7_MASK           (0x00000080u)
06985 #define EDMA3_CCRL_ICR_I7_SHIFT          (0x00000007u)
06986 #define EDMA3_CCRL_ICR_I7_RESETVAL       (0x00000000u)
06987 
06988 /*----I7 Tokens----*/
06989 #define EDMA3_CCRL_ICR_I7_CLEAR          (0x00000001u)
06990 
06991 #define EDMA3_CCRL_ICR_I6_MASK           (0x00000040u)
06992 #define EDMA3_CCRL_ICR_I6_SHIFT          (0x00000006u)
06993 #define EDMA3_CCRL_ICR_I6_RESETVAL       (0x00000000u)
06994 
06995 /*----I6 Tokens----*/
06996 #define EDMA3_CCRL_ICR_I6_CLEAR          (0x00000001u)
06997 
06998 #define EDMA3_CCRL_ICR_I5_MASK           (0x00000020u)
06999 #define EDMA3_CCRL_ICR_I5_SHIFT          (0x00000005u)
07000 #define EDMA3_CCRL_ICR_I5_RESETVAL       (0x00000000u)
07001 
07002 /*----I5 Tokens----*/
07003 #define EDMA3_CCRL_ICR_I5_CLEAR          (0x00000001u)
07004 
07005 #define EDMA3_CCRL_ICR_I4_MASK           (0x00000010u)
07006 #define EDMA3_CCRL_ICR_I4_SHIFT          (0x00000004u)
07007 #define EDMA3_CCRL_ICR_I4_RESETVAL       (0x00000000u)
07008 
07009 /*----I4 Tokens----*/
07010 #define EDMA3_CCRL_ICR_I4_CLEAR          (0x00000001u)
07011 
07012 #define EDMA3_CCRL_ICR_I3_MASK           (0x00000008u)
07013 #define EDMA3_CCRL_ICR_I3_SHIFT          (0x00000003u)
07014 #define EDMA3_CCRL_ICR_I3_RESETVAL       (0x00000000u)
07015 
07016 /*----I3 Tokens----*/
07017 #define EDMA3_CCRL_ICR_I3_CLEAR          (0x00000001u)
07018 
07019 #define EDMA3_CCRL_ICR_I2_MASK           (0x00000004u)
07020 #define EDMA3_CCRL_ICR_I2_SHIFT          (0x00000002u)
07021 #define EDMA3_CCRL_ICR_I2_RESETVAL       (0x00000000u)
07022 
07023 /*----I2 Tokens----*/
07024 #define EDMA3_CCRL_ICR_I2_CLEAR          (0x00000001u)
07025 
07026 #define EDMA3_CCRL_ICR_I1_MASK           (0x00000002u)
07027 #define EDMA3_CCRL_ICR_I1_SHIFT          (0x00000001u)
07028 #define EDMA3_CCRL_ICR_I1_RESETVAL       (0x00000000u)
07029 
07030 /*----I1 Tokens----*/
07031 #define EDMA3_CCRL_ICR_I1_CLEAR          (0x00000001u)
07032 
07033 #define EDMA3_CCRL_ICR_I0_MASK           (0x00000001u)
07034 #define EDMA3_CCRL_ICR_I0_SHIFT          (0x00000000u)
07035 #define EDMA3_CCRL_ICR_I0_RESETVAL       (0x00000000u)
07036 
07037 /*----I0 Tokens----*/
07038 #define EDMA3_CCRL_ICR_I0_CLEAR          (0x00000001u)
07039 
07040 #define EDMA3_CCRL_ICR_RESETVAL          (0x00000000u)
07041 
07042 /* ICRH */
07043 
07044 #define EDMA3_CCRL_ICRH_I63_MASK         (0x80000000u)
07045 #define EDMA3_CCRL_ICRH_I63_SHIFT        (0x0000001Fu)
07046 #define EDMA3_CCRL_ICRH_I63_RESETVAL     (0x00000000u)
07047 
07048 /*----I63 Tokens----*/
07049 #define EDMA3_CCRL_ICRH_I63_CLEAR        (0x00000001u)
07050 
07051 #define EDMA3_CCRL_ICRH_I62_MASK         (0x40000000u)
07052 #define EDMA3_CCRL_ICRH_I62_SHIFT        (0x0000001Eu)
07053 #define EDMA3_CCRL_ICRH_I62_RESETVAL     (0x00000000u)
07054 
07055 /*----I62 Tokens----*/
07056 #define EDMA3_CCRL_ICRH_I62_CLEAR        (0x00000001u)
07057 
07058 #define EDMA3_CCRL_ICRH_I61_MASK         (0x20000000u)
07059 #define EDMA3_CCRL_ICRH_I61_SHIFT        (0x0000001Du)
07060 #define EDMA3_CCRL_ICRH_I61_RESETVAL     (0x00000000u)
07061 
07062 /*----I61 Tokens----*/
07063 #define EDMA3_CCRL_ICRH_I61_CLEAR        (0x00000001u)
07064 
07065 #define EDMA3_CCRL_ICRH_I60_MASK         (0x10000000u)
07066 #define EDMA3_CCRL_ICRH_I60_SHIFT        (0x0000001Cu)
07067 #define EDMA3_CCRL_ICRH_I60_RESETVAL     (0x00000000u)
07068 
07069 /*----I60 Tokens----*/
07070 #define EDMA3_CCRL_ICRH_I60_CLEAR        (0x00000001u)
07071 
07072 #define EDMA3_CCRL_ICRH_I59_MASK         (0x08000000u)
07073 #define EDMA3_CCRL_ICRH_I59_SHIFT        (0x0000001Bu)
07074 #define EDMA3_CCRL_ICRH_I59_RESETVAL     (0x00000000u)
07075 
07076 /*----I59 Tokens----*/
07077 #define EDMA3_CCRL_ICRH_I59_CLEAR        (0x00000001u)
07078 
07079 #define EDMA3_CCRL_ICRH_I58_MASK         (0x04000000u)
07080 #define EDMA3_CCRL_ICRH_I58_SHIFT        (0x0000001Au)
07081 #define EDMA3_CCRL_ICRH_I58_RESETVAL     (0x00000000u)
07082 
07083 /*----I58 Tokens----*/
07084 #define EDMA3_CCRL_ICRH_I58_CLEAR        (0x00000001u)
07085 
07086 #define EDMA3_CCRL_ICRH_I57_MASK         (0x02000000u)
07087 #define EDMA3_CCRL_ICRH_I57_SHIFT        (0x00000019u)
07088 #define EDMA3_CCRL_ICRH_I57_RESETVAL     (0x00000000u)
07089 
07090 /*----I57 Tokens----*/
07091 #define EDMA3_CCRL_ICRH_I57_CLEAR        (0x00000001u)
07092 
07093 #define EDMA3_CCRL_ICRH_I56_MASK         (0x01000000u)
07094 #define EDMA3_CCRL_ICRH_I56_SHIFT        (0x00000018u)
07095 #define EDMA3_CCRL_ICRH_I56_RESETVAL     (0x00000000u)
07096 
07097 /*----I56 Tokens----*/
07098 #define EDMA3_CCRL_ICRH_I56_CLEAR        (0x00000001u)
07099 
07100 #define EDMA3_CCRL_ICRH_I55_MASK         (0x00800000u)
07101 #define EDMA3_CCRL_ICRH_I55_SHIFT        (0x00000017u)
07102 #define EDMA3_CCRL_ICRH_I55_RESETVAL     (0x00000000u)
07103 
07104 /*----I55 Tokens----*/
07105 #define EDMA3_CCRL_ICRH_I55_CLEAR        (0x00000001u)
07106 
07107 #define EDMA3_CCRL_ICRH_I54_MASK         (0x00400000u)
07108 #define EDMA3_CCRL_ICRH_I54_SHIFT        (0x00000016u)
07109 #define EDMA3_CCRL_ICRH_I54_RESETVAL     (0x00000000u)
07110 
07111 /*----I54 Tokens----*/
07112 #define EDMA3_CCRL_ICRH_I54_CLEAR        (0x00000001u)
07113 
07114 #define EDMA3_CCRL_ICRH_I53_MASK         (0x00200000u)
07115 #define EDMA3_CCRL_ICRH_I53_SHIFT        (0x00000015u)
07116 #define EDMA3_CCRL_ICRH_I53_RESETVAL     (0x00000000u)
07117 
07118 /*----I53 Tokens----*/
07119 #define EDMA3_CCRL_ICRH_I53_CLEAR        (0x00000001u)
07120 
07121 #define EDMA3_CCRL_ICRH_I52_MASK         (0x00100000u)
07122 #define EDMA3_CCRL_ICRH_I52_SHIFT        (0x00000014u)
07123 #define EDMA3_CCRL_ICRH_I52_RESETVAL     (0x00000000u)
07124 
07125 /*----I52 Tokens----*/
07126 #define EDMA3_CCRL_ICRH_I52_CLEAR        (0x00000001u)
07127 
07128 #define EDMA3_CCRL_ICRH_I51_MASK         (0x00080000u)
07129 #define EDMA3_CCRL_ICRH_I51_SHIFT        (0x00000013u)
07130 #define EDMA3_CCRL_ICRH_I51_RESETVAL     (0x00000000u)
07131 
07132 /*----I51 Tokens----*/
07133 #define EDMA3_CCRL_ICRH_I51_CLEAR        (0x00000001u)
07134 
07135 #define EDMA3_CCRL_ICRH_I50_MASK         (0x00040000u)
07136 #define EDMA3_CCRL_ICRH_I50_SHIFT        (0x00000012u)
07137 #define EDMA3_CCRL_ICRH_I50_RESETVAL     (0x00000000u)
07138 
07139 /*----I50 Tokens----*/
07140 #define EDMA3_CCRL_ICRH_I50_CLEAR        (0x00000001u)
07141 
07142 #define EDMA3_CCRL_ICRH_I49_MASK         (0x00020000u)
07143 #define EDMA3_CCRL_ICRH_I49_SHIFT        (0x00000011u)
07144 #define EDMA3_CCRL_ICRH_I49_RESETVAL     (0x00000000u)
07145 
07146 /*----I49 Tokens----*/
07147 #define EDMA3_CCRL_ICRH_I49_CLEAR        (0x00000001u)
07148 
07149 #define EDMA3_CCRL_ICRH_I48_MASK         (0x00010000u)
07150 #define EDMA3_CCRL_ICRH_I48_SHIFT        (0x00000010u)
07151 #define EDMA3_CCRL_ICRH_I48_RESETVAL     (0x00000000u)
07152 
07153 /*----I48 Tokens----*/
07154 #define EDMA3_CCRL_ICRH_I48_CLEAR        (0x00000001u)
07155 
07156 #define EDMA3_CCRL_ICRH_I47_MASK         (0x00008000u)
07157 #define EDMA3_CCRL_ICRH_I47_SHIFT        (0x0000000Fu)
07158 #define EDMA3_CCRL_ICRH_I47_RESETVAL     (0x00000000u)
07159 
07160 /*----I47 Tokens----*/
07161 #define EDMA3_CCRL_ICRH_I47_CLEAR        (0x00000001u)
07162 
07163 #define EDMA3_CCRL_ICRH_I46_MASK         (0x00004000u)
07164 #define EDMA3_CCRL_ICRH_I46_SHIFT        (0x0000000Eu)
07165 #define EDMA3_CCRL_ICRH_I46_RESETVAL     (0x00000000u)
07166 
07167 /*----I46 Tokens----*/
07168 #define EDMA3_CCRL_ICRH_I46_CLEAR        (0x00000001u)
07169 
07170 #define EDMA3_CCRL_ICRH_I45_MASK         (0x00002000u)
07171 #define EDMA3_CCRL_ICRH_I45_SHIFT        (0x0000000Du)
07172 #define EDMA3_CCRL_ICRH_I45_RESETVAL     (0x00000000u)
07173 
07174 /*----I45 Tokens----*/
07175 #define EDMA3_CCRL_ICRH_I45_CLEAR        (0x00000001u)
07176 
07177 #define EDMA3_CCRL_ICRH_I44_MASK         (0x00001000u)
07178 #define EDMA3_CCRL_ICRH_I44_SHIFT        (0x0000000Cu)
07179 #define EDMA3_CCRL_ICRH_I44_RESETVAL     (0x00000000u)
07180 
07181 /*----I44 Tokens----*/
07182 #define EDMA3_CCRL_ICRH_I44_CLEAR        (0x00000001u)
07183 
07184 #define EDMA3_CCRL_ICRH_I43_MASK         (0x00000800u)
07185 #define EDMA3_CCRL_ICRH_I43_SHIFT        (0x0000000Bu)
07186 #define EDMA3_CCRL_ICRH_I43_RESETVAL     (0x00000000u)
07187 
07188 /*----I43 Tokens----*/
07189 #define EDMA3_CCRL_ICRH_I43_CLEAR        (0x00000001u)
07190 
07191 #define EDMA3_CCRL_ICRH_I42_MASK         (0x00000400u)
07192 #define EDMA3_CCRL_ICRH_I42_SHIFT        (0x0000000Au)
07193 #define EDMA3_CCRL_ICRH_I42_RESETVAL     (0x00000000u)
07194 
07195 /*----I42 Tokens----*/
07196 #define EDMA3_CCRL_ICRH_I42_CLEAR        (0x00000001u)
07197 
07198 #define EDMA3_CCRL_ICRH_I41_MASK         (0x00000200u)
07199 #define EDMA3_CCRL_ICRH_I41_SHIFT        (0x00000009u)
07200 #define EDMA3_CCRL_ICRH_I41_RESETVAL     (0x00000000u)
07201 
07202 /*----I41 Tokens----*/
07203 #define EDMA3_CCRL_ICRH_I41_CLEAR        (0x00000001u)
07204 
07205 #define EDMA3_CCRL_ICRH_I40_MASK         (0x00000100u)
07206 #define EDMA3_CCRL_ICRH_I40_SHIFT        (0x00000008u)
07207 #define EDMA3_CCRL_ICRH_I40_RESETVAL     (0x00000000u)
07208 
07209 /*----I40 Tokens----*/
07210 #define EDMA3_CCRL_ICRH_I40_CLEAR        (0x00000001u)
07211 
07212 #define EDMA3_CCRL_ICRH_I39_MASK         (0x00000080u)
07213 #define EDMA3_CCRL_ICRH_I39_SHIFT        (0x00000007u)
07214 #define EDMA3_CCRL_ICRH_I39_RESETVAL     (0x00000000u)
07215 
07216 /*----I39 Tokens----*/
07217 #define EDMA3_CCRL_ICRH_I39_CLEAR        (0x00000001u)
07218 
07219 #define EDMA3_CCRL_ICRH_I38_MASK         (0x00000040u)
07220 #define EDMA3_CCRL_ICRH_I38_SHIFT        (0x00000006u)
07221 #define EDMA3_CCRL_ICRH_I38_RESETVAL     (0x00000000u)
07222 
07223 /*----I38 Tokens----*/
07224 #define EDMA3_CCRL_ICRH_I38_CLEAR        (0x00000001u)
07225 
07226 #define EDMA3_CCRL_ICRH_I37_MASK         (0x00000020u)
07227 #define EDMA3_CCRL_ICRH_I37_SHIFT        (0x00000005u)
07228 #define EDMA3_CCRL_ICRH_I37_RESETVAL     (0x00000000u)
07229 
07230 /*----I37 Tokens----*/
07231 #define EDMA3_CCRL_ICRH_I37_CLEAR        (0x00000001u)
07232 
07233 #define EDMA3_CCRL_ICRH_I36_MASK         (0x00000010u)
07234 #define EDMA3_CCRL_ICRH_I36_SHIFT        (0x00000004u)
07235 #define EDMA3_CCRL_ICRH_I36_RESETVAL     (0x00000000u)
07236 
07237 /*----I36 Tokens----*/
07238 #define EDMA3_CCRL_ICRH_I36_CLEAR        (0x00000001u)
07239 
07240 #define EDMA3_CCRL_ICRH_I35_MASK         (0x00000008u)
07241 #define EDMA3_CCRL_ICRH_I35_SHIFT        (0x00000003u)
07242 #define EDMA3_CCRL_ICRH_I35_RESETVAL     (0x00000000u)
07243 
07244 /*----I35 Tokens----*/
07245 #define EDMA3_CCRL_ICRH_I35_CLEAR        (0x00000001u)
07246 
07247 #define EDMA3_CCRL_ICRH_I34_MASK         (0x00000004u)
07248 #define EDMA3_CCRL_ICRH_I34_SHIFT        (0x00000002u)
07249 #define EDMA3_CCRL_ICRH_I34_RESETVAL     (0x00000000u)
07250 
07251 /*----I34 Tokens----*/
07252 #define EDMA3_CCRL_ICRH_I34_CLEAR        (0x00000001u)
07253 
07254 #define EDMA3_CCRL_ICRH_I33_MASK         (0x00000002u)
07255 #define EDMA3_CCRL_ICRH_I33_SHIFT        (0x00000001u)
07256 #define EDMA3_CCRL_ICRH_I33_RESETVAL     (0x00000000u)
07257 
07258 /*----I33 Tokens----*/
07259 #define EDMA3_CCRL_ICRH_I33_CLEAR        (0x00000001u)
07260 
07261 #define EDMA3_CCRL_ICRH_I32_MASK         (0x00000001u)
07262 #define EDMA3_CCRL_ICRH_I32_SHIFT        (0x00000000u)
07263 #define EDMA3_CCRL_ICRH_I32_RESETVAL     (0x00000000u)
07264 
07265 /*----I32 Tokens----*/
07266 #define EDMA3_CCRL_ICRH_I32_CLEAR        (0x00000001u)
07267 
07268 #define EDMA3_CCRL_ICRH_RESETVAL         (0x00000000u)
07269 
07270 /* IEVAL */
07271 
07272 #define EDMA3_CCRL_IEVAL_SET_MASK        (0x00000002u)
07273 #define EDMA3_CCRL_IEVAL_SET_SHIFT       (0x00000001u)
07274 #define EDMA3_CCRL_IEVAL_SET_RESETVAL    (0x00000000u)
07275 
07276 /*----SET Tokens----*/
07277 #define EDMA3_CCRL_IEVAL_SET_SET         (0x00000001u)
07278 
07279 #define EDMA3_CCRL_IEVAL_EVAL_MASK       (0x00000001u)
07280 #define EDMA3_CCRL_IEVAL_EVAL_SHIFT      (0x00000000u)
07281 #define EDMA3_CCRL_IEVAL_EVAL_RESETVAL   (0x00000000u)
07282 
07283 /*----EVAL Tokens----*/
07284 #define EDMA3_CCRL_IEVAL_EVAL_EVAL       (0x00000001u)
07285 
07286 #define EDMA3_CCRL_IEVAL_RESETVAL        (0x00000000u)
07287 
07288 /* QER */
07289 
07290 #define EDMA3_CCRL_QER_E7_MASK           (0x00000080u)
07291 #define EDMA3_CCRL_QER_E7_SHIFT          (0x00000007u)
07292 #define EDMA3_CCRL_QER_E7_RESETVAL       (0x00000000u)
07293 
07294 #define EDMA3_CCRL_QER_E6_MASK           (0x00000040u)
07295 #define EDMA3_CCRL_QER_E6_SHIFT          (0x00000006u)
07296 #define EDMA3_CCRL_QER_E6_RESETVAL       (0x00000000u)
07297 
07298 #define EDMA3_CCRL_QER_E5_MASK           (0x00000020u)
07299 #define EDMA3_CCRL_QER_E5_SHIFT          (0x00000005u)
07300 #define EDMA3_CCRL_QER_E5_RESETVAL       (0x00000000u)
07301 
07302 #define EDMA3_CCRL_QER_E4_MASK           (0x00000010u)
07303 #define EDMA3_CCRL_QER_E4_SHIFT          (0x00000004u)
07304 #define EDMA3_CCRL_QER_E4_RESETVAL       (0x00000000u)
07305 
07306 #define EDMA3_CCRL_QER_E3_MASK           (0x00000008u)
07307 #define EDMA3_CCRL_QER_E3_SHIFT          (0x00000003u)
07308 #define EDMA3_CCRL_QER_E3_RESETVAL       (0x00000000u)
07309 
07310 #define EDMA3_CCRL_QER_E2_MASK           (0x00000004u)
07311 #define EDMA3_CCRL_QER_E2_SHIFT          (0x00000002u)
07312 #define EDMA3_CCRL_QER_E2_RESETVAL       (0x00000000u)
07313 
07314 #define EDMA3_CCRL_QER_E1_MASK           (0x00000002u)
07315 #define EDMA3_CCRL_QER_E1_SHIFT          (0x00000001u)
07316 #define EDMA3_CCRL_QER_E1_RESETVAL       (0x00000000u)
07317 
07318 #define EDMA3_CCRL_QER_E0_MASK           (0x00000001u)
07319 #define EDMA3_CCRL_QER_E0_SHIFT          (0x00000000u)
07320 #define EDMA3_CCRL_QER_E0_RESETVAL       (0x00000000u)
07321 
07322 #define EDMA3_CCRL_QER_RESETVAL          (0x00000000u)
07323 
07324 /* QEER */
07325 
07326 #define EDMA3_CCRL_QEER_E7_MASK          (0x00000080u)
07327 #define EDMA3_CCRL_QEER_E7_SHIFT         (0x00000007u)
07328 #define EDMA3_CCRL_QEER_E7_RESETVAL      (0x00000000u)
07329 
07330 #define EDMA3_CCRL_QEER_E6_MASK          (0x00000040u)
07331 #define EDMA3_CCRL_QEER_E6_SHIFT         (0x00000006u)
07332 #define EDMA3_CCRL_QEER_E6_RESETVAL      (0x00000000u)
07333 
07334 #define EDMA3_CCRL_QEER_E5_MASK          (0x00000020u)
07335 #define EDMA3_CCRL_QEER_E5_SHIFT         (0x00000005u)
07336 #define EDMA3_CCRL_QEER_E5_RESETVAL      (0x00000000u)
07337 
07338 #define EDMA3_CCRL_QEER_E4_MASK          (0x00000010u)
07339 #define EDMA3_CCRL_QEER_E4_SHIFT         (0x00000004u)
07340 #define EDMA3_CCRL_QEER_E4_RESETVAL      (0x00000000u)
07341 
07342 #define EDMA3_CCRL_QEER_E3_MASK          (0x00000008u)
07343 #define EDMA3_CCRL_QEER_E3_SHIFT         (0x00000003u)
07344 #define EDMA3_CCRL_QEER_E3_RESETVAL      (0x00000000u)
07345 
07346 #define EDMA3_CCRL_QEER_E2_MASK          (0x00000004u)
07347 #define EDMA3_CCRL_QEER_E2_SHIFT         (0x00000002u)
07348 #define EDMA3_CCRL_QEER_E2_RESETVAL      (0x00000000u)
07349 
07350 #define EDMA3_CCRL_QEER_E1_MASK          (0x00000002u)
07351 #define EDMA3_CCRL_QEER_E1_SHIFT         (0x00000001u)
07352 #define EDMA3_CCRL_QEER_E1_RESETVAL      (0x00000000u)
07353 
07354 #define EDMA3_CCRL_QEER_E0_MASK          (0x00000001u)
07355 #define EDMA3_CCRL_QEER_E0_SHIFT         (0x00000000u)
07356 #define EDMA3_CCRL_QEER_E0_RESETVAL      (0x00000000u)
07357 
07358 #define EDMA3_CCRL_QEER_RESETVAL         (0x00000000u)
07359 
07360 /* QEECR */
07361 
07362 #define EDMA3_CCRL_QEECR_E7_MASK         (0x00000080u)
07363 #define EDMA3_CCRL_QEECR_E7_SHIFT        (0x00000007u)
07364 #define EDMA3_CCRL_QEECR_E7_RESETVAL     (0x00000000u)
07365 
07366 /*----E7 Tokens----*/
07367 #define EDMA3_CCRL_QEECR_E7_CLEAR        (0x00000001u)
07368 
07369 #define EDMA3_CCRL_QEECR_E6_MASK         (0x00000040u)
07370 #define EDMA3_CCRL_QEECR_E6_SHIFT        (0x00000006u)
07371 #define EDMA3_CCRL_QEECR_E6_RESETVAL     (0x00000000u)
07372 
07373 /*----E6 Tokens----*/
07374 #define EDMA3_CCRL_QEECR_E6_CLEAR        (0x00000001u)
07375 
07376 #define EDMA3_CCRL_QEECR_E5_MASK         (0x00000020u)
07377 #define EDMA3_CCRL_QEECR_E5_SHIFT        (0x00000005u)
07378 #define EDMA3_CCRL_QEECR_E5_RESETVAL     (0x00000000u)
07379 
07380 /*----E5 Tokens----*/
07381 #define EDMA3_CCRL_QEECR_E5_CLEAR        (0x00000001u)
07382 
07383 #define EDMA3_CCRL_QEECR_E4_MASK         (0x00000010u)
07384 #define EDMA3_CCRL_QEECR_E4_SHIFT        (0x00000004u)
07385 #define EDMA3_CCRL_QEECR_E4_RESETVAL     (0x00000000u)
07386 
07387 /*----E4 Tokens----*/
07388 #define EDMA3_CCRL_QEECR_E4_CLEAR        (0x00000001u)
07389 
07390 #define EDMA3_CCRL_QEECR_E3_MASK         (0x00000008u)
07391 #define EDMA3_CCRL_QEECR_E3_SHIFT        (0x00000003u)
07392 #define EDMA3_CCRL_QEECR_E3_RESETVAL     (0x00000000u)
07393 
07394 /*----E3 Tokens----*/
07395 #define EDMA3_CCRL_QEECR_E3_CLEAR        (0x00000001u)
07396 
07397 #define EDMA3_CCRL_QEECR_E2_MASK         (0x00000004u)
07398 #define EDMA3_CCRL_QEECR_E2_SHIFT        (0x00000002u)
07399 #define EDMA3_CCRL_QEECR_E2_RESETVAL     (0x00000000u)
07400 
07401 /*----E2 Tokens----*/
07402 #define EDMA3_CCRL_QEECR_E2_CLEAR        (0x00000001u)
07403 
07404 #define EDMA3_CCRL_QEECR_E1_MASK         (0x00000002u)
07405 #define EDMA3_CCRL_QEECR_E1_SHIFT        (0x00000001u)
07406 #define EDMA3_CCRL_QEECR_E1_RESETVAL     (0x00000000u)
07407 
07408 /*----E1 Tokens----*/
07409 #define EDMA3_CCRL_QEECR_E1_CLEAR        (0x00000001u)
07410 
07411 #define EDMA3_CCRL_QEECR_E0_MASK         (0x00000001u)
07412 #define EDMA3_CCRL_QEECR_E0_SHIFT        (0x00000000u)
07413 #define EDMA3_CCRL_QEECR_E0_RESETVAL     (0x00000000u)
07414 
07415 /*----E0 Tokens----*/
07416 #define EDMA3_CCRL_QEECR_E0_CLEAR        (0x00000001u)
07417 
07418 #define EDMA3_CCRL_QEECR_RESETVAL        (0x00000000u)
07419 
07420 /* QEESR */
07421 
07422 #define EDMA3_CCRL_QEESR_E7_MASK         (0x00000080u)
07423 #define EDMA3_CCRL_QEESR_E7_SHIFT        (0x00000007u)
07424 #define EDMA3_CCRL_QEESR_E7_RESETVAL     (0x00000000u)
07425 
07426 /*----E7 Tokens----*/
07427 #define EDMA3_CCRL_QEESR_E7_SET          (0x00000001u)
07428 
07429 #define EDMA3_CCRL_QEESR_E6_MASK         (0x00000040u)
07430 #define EDMA3_CCRL_QEESR_E6_SHIFT        (0x00000006u)
07431 #define EDMA3_CCRL_QEESR_E6_RESETVAL     (0x00000000u)
07432 
07433 /*----E6 Tokens----*/
07434 #define EDMA3_CCRL_QEESR_E6_SET          (0x00000001u)
07435 
07436 #define EDMA3_CCRL_QEESR_E5_MASK         (0x00000020u)
07437 #define EDMA3_CCRL_QEESR_E5_SHIFT        (0x00000005u)
07438 #define EDMA3_CCRL_QEESR_E5_RESETVAL     (0x00000000u)
07439 
07440 /*----E5 Tokens----*/
07441 #define EDMA3_CCRL_QEESR_E5_SET          (0x00000001u)
07442 
07443 #define EDMA3_CCRL_QEESR_E4_MASK         (0x00000010u)
07444 #define EDMA3_CCRL_QEESR_E4_SHIFT        (0x00000004u)
07445 #define EDMA3_CCRL_QEESR_E4_RESETVAL     (0x00000000u)
07446 
07447 /*----E4 Tokens----*/
07448 #define EDMA3_CCRL_QEESR_E4_SET          (0x00000001u)
07449 
07450 #define EDMA3_CCRL_QEESR_E3_MASK         (0x00000008u)
07451 #define EDMA3_CCRL_QEESR_E3_SHIFT        (0x00000003u)
07452 #define EDMA3_CCRL_QEESR_E3_RESETVAL     (0x00000000u)
07453 
07454 /*----E3 Tokens----*/
07455 #define EDMA3_CCRL_QEESR_E3_SET          (0x00000001u)
07456 
07457 #define EDMA3_CCRL_QEESR_E2_MASK         (0x00000004u)
07458 #define EDMA3_CCRL_QEESR_E2_SHIFT        (0x00000002u)
07459 #define EDMA3_CCRL_QEESR_E2_RESETVAL     (0x00000000u)
07460 
07461 /*----E2 Tokens----*/
07462 #define EDMA3_CCRL_QEESR_E2_SET          (0x00000001u)
07463 
07464 #define EDMA3_CCRL_QEESR_E1_MASK         (0x00000002u)
07465 #define EDMA3_CCRL_QEESR_E1_SHIFT        (0x00000001u)
07466 #define EDMA3_CCRL_QEESR_E1_RESETVAL     (0x00000000u)
07467 
07468 /*----E1 Tokens----*/
07469 #define EDMA3_CCRL_QEESR_E1_SET          (0x00000001u)
07470 
07471 #define EDMA3_CCRL_QEESR_E0_MASK         (0x00000001u)
07472 #define EDMA3_CCRL_QEESR_E0_SHIFT        (0x00000000u)
07473 #define EDMA3_CCRL_QEESR_E0_RESETVAL     (0x00000000u)
07474 
07475 /*----E0 Tokens----*/
07476 #define EDMA3_CCRL_QEESR_E0_SET          (0x00000001u)
07477 
07478 #define EDMA3_CCRL_QEESR_RESETVAL        (0x00000000u)
07479 
07480 /* QSER */
07481 
07482 #define EDMA3_CCRL_QSER_E7_MASK          (0x00000080u)
07483 #define EDMA3_CCRL_QSER_E7_SHIFT         (0x00000007u)
07484 #define EDMA3_CCRL_QSER_E7_RESETVAL      (0x00000000u)
07485 
07486 #define EDMA3_CCRL_QSER_E6_MASK          (0x00000040u)
07487 #define EDMA3_CCRL_QSER_E6_SHIFT         (0x00000006u)
07488 #define EDMA3_CCRL_QSER_E6_RESETVAL      (0x00000000u)
07489 
07490 #define EDMA3_CCRL_QSER_E5_MASK          (0x00000020u)
07491 #define EDMA3_CCRL_QSER_E5_SHIFT         (0x00000005u)
07492 #define EDMA3_CCRL_QSER_E5_RESETVAL      (0x00000000u)
07493 
07494 #define EDMA3_CCRL_QSER_E4_MASK          (0x00000010u)
07495 #define EDMA3_CCRL_QSER_E4_SHIFT         (0x00000004u)
07496 #define EDMA3_CCRL_QSER_E4_RESETVAL      (0x00000000u)
07497 
07498 #define EDMA3_CCRL_QSER_E3_MASK          (0x00000008u)
07499 #define EDMA3_CCRL_QSER_E3_SHIFT         (0x00000003u)
07500 #define EDMA3_CCRL_QSER_E3_RESETVAL      (0x00000000u)
07501 
07502 #define EDMA3_CCRL_QSER_E2_MASK          (0x00000004u)
07503 #define EDMA3_CCRL_QSER_E2_SHIFT         (0x00000002u)
07504 #define EDMA3_CCRL_QSER_E2_RESETVAL      (0x00000000u)
07505 
07506 #define EDMA3_CCRL_QSER_E1_MASK          (0x00000002u)
07507 #define EDMA3_CCRL_QSER_E1_SHIFT         (0x00000001u)
07508 #define EDMA3_CCRL_QSER_E1_RESETVAL      (0x00000000u)
07509 
07510 #define EDMA3_CCRL_QSER_E0_MASK          (0x00000001u)
07511 #define EDMA3_CCRL_QSER_E0_SHIFT         (0x00000000u)
07512 #define EDMA3_CCRL_QSER_E0_RESETVAL      (0x00000000u)
07513 
07514 #define EDMA3_CCRL_QSER_RESETVAL         (0x00000000u)
07515 
07516 /* QSECR */
07517 
07518 #define EDMA3_CCRL_QSECR_E7_MASK         (0x00000080u)
07519 #define EDMA3_CCRL_QSECR_E7_SHIFT        (0x00000007u)
07520 #define EDMA3_CCRL_QSECR_E7_RESETVAL     (0x00000000u)
07521 
07522 /*----E7 Tokens----*/
07523 #define EDMA3_CCRL_QSECR_E7_CLEAR        (0x00000001u)
07524 
07525 #define EDMA3_CCRL_QSECR_E6_MASK         (0x00000040u)
07526 #define EDMA3_CCRL_QSECR_E6_SHIFT        (0x00000006u)
07527 #define EDMA3_CCRL_QSECR_E6_RESETVAL     (0x00000000u)
07528 
07529 /*----E6 Tokens----*/
07530 #define EDMA3_CCRL_QSECR_E6_CLEAR        (0x00000001u)
07531 
07532 #define EDMA3_CCRL_QSECR_E5_MASK         (0x00000020u)
07533 #define EDMA3_CCRL_QSECR_E5_SHIFT        (0x00000005u)
07534 #define EDMA3_CCRL_QSECR_E5_RESETVAL     (0x00000000u)
07535 
07536 /*----E5 Tokens----*/
07537 #define EDMA3_CCRL_QSECR_E5_CLEAR        (0x00000001u)
07538 
07539 #define EDMA3_CCRL_QSECR_E4_MASK         (0x00000010u)
07540 #define EDMA3_CCRL_QSECR_E4_SHIFT        (0x00000004u)
07541 #define EDMA3_CCRL_QSECR_E4_RESETVAL     (0x00000000u)
07542 
07543 /*----E4 Tokens----*/
07544 #define EDMA3_CCRL_QSECR_E4_CLEAR        (0x00000001u)
07545 
07546 #define EDMA3_CCRL_QSECR_E3_MASK         (0x00000008u)
07547 #define EDMA3_CCRL_QSECR_E3_SHIFT        (0x00000003u)
07548 #define EDMA3_CCRL_QSECR_E3_RESETVAL     (0x00000000u)
07549 
07550 /*----E3 Tokens----*/
07551 #define EDMA3_CCRL_QSECR_E3_CLEAR        (0x00000001u)
07552 
07553 #define EDMA3_CCRL_QSECR_E2_MASK         (0x00000004u)
07554 #define EDMA3_CCRL_QSECR_E2_SHIFT        (0x00000002u)
07555 #define EDMA3_CCRL_QSECR_E2_RESETVAL     (0x00000000u)
07556 
07557 /*----E2 Tokens----*/
07558 #define EDMA3_CCRL_QSECR_E2_CLEAR        (0x00000001u)
07559 
07560 #define EDMA3_CCRL_QSECR_E1_MASK         (0x00000002u)
07561 #define EDMA3_CCRL_QSECR_E1_SHIFT        (0x00000001u)
07562 #define EDMA3_CCRL_QSECR_E1_RESETVAL     (0x00000000u)
07563 
07564 /*----E1 Tokens----*/
07565 #define EDMA3_CCRL_QSECR_E1_CLEAR        (0x00000001u)
07566 
07567 #define EDMA3_CCRL_QSECR_E0_MASK         (0x00000001u)
07568 #define EDMA3_CCRL_QSECR_E0_SHIFT        (0x00000000u)
07569 #define EDMA3_CCRL_QSECR_E0_RESETVAL     (0x00000000u)
07570 
07571 /*----E0 Tokens----*/
07572 #define EDMA3_CCRL_QSECR_E0_CLEAR        (0x00000001u)
07573 
07574 #define EDMA3_CCRL_QSECR_RESETVAL        (0x00000000u)
07575 
07576 /* OPT */
07577 
07578 #define EDMA3_CCRL_OPT_PRIV_MASK         (0x80000000u)
07579 #define EDMA3_CCRL_OPT_PRIV_SHIFT        (0x0000001Fu)
07580 #define EDMA3_CCRL_OPT_PRIV_RESETVAL     (0x00000000u)
07581 
07582 /*----PRIV Tokens----*/
07583 #define EDMA3_CCRL_OPT_PRIV_USER         (0x00000000u)
07584 #define EDMA3_CCRL_OPT_PRIV_SUPERVISOR   (0x00000001u)
07585 
07586 #define EDMA3_CCRL_OPT_SECURE_MASK       (0x40000000u)
07587 #define EDMA3_CCRL_OPT_SECURE_SHIFT      (0x0000001Eu)
07588 #define EDMA3_CCRL_OPT_SECURE_RESETVAL   (0x00000000u)
07589 
07590 /*----SECURE Tokens----*/
07591 #define EDMA3_CCRL_OPT_SECURE_SECURE     (0x00000000u)
07592 #define EDMA3_CCRL_OPT_SECURE_NONSECURE  (0x00000001u)
07593 
07594 #define EDMA3_CCRL_OPT_PRIVID_MASK       (0x0F000000u)
07595 #define EDMA3_CCRL_OPT_PRIVID_SHIFT      (0x00000018u)
07596 #define EDMA3_CCRL_OPT_PRIVID_RESETVAL   (0x00000000u)
07597 
07598 #define EDMA3_CCRL_OPT_ITCCHEN_MASK      (0x00800000u)
07599 #define EDMA3_CCRL_OPT_ITCCHEN_SHIFT     (0x00000017u)
07600 #define EDMA3_CCRL_OPT_ITCCHEN_RESETVAL  (0x00000000u)
07601 
07602 /*----ITCCHEN Tokens----*/
07603 #define EDMA3_CCRL_OPT_ITCCHEN_DISABLE   (0x00000000u)
07604 #define EDMA3_CCRL_OPT_ITCCHEN_ENABLE    (0x00000001u)
07605 
07606 #define EDMA3_CCRL_OPT_TCCHEN_MASK       (0x00400000u)
07607 #define EDMA3_CCRL_OPT_TCCHEN_SHIFT      (0x00000016u)
07608 #define EDMA3_CCRL_OPT_TCCHEN_RESETVAL   (0x00000000u)
07609 
07610 /*----TCCHEN Tokens----*/
07611 #define EDMA3_CCRL_OPT_TCCHEN_DISABLE    (0x00000000u)
07612 #define EDMA3_CCRL_OPT_TCCHEN_ENABLE     (0x00000001u)
07613 
07614 #define EDMA3_CCRL_OPT_ITCINTEN_MASK     (0x00200000u)
07615 #define EDMA3_CCRL_OPT_ITCINTEN_SHIFT    (0x00000015u)
07616 #define EDMA3_CCRL_OPT_ITCINTEN_RESETVAL (0x00000000u)
07617 
07618 /*----ITCINTEN Tokens----*/
07619 #define EDMA3_CCRL_OPT_ITCINTEN_DISABLE  (0x00000000u)
07620 #define EDMA3_CCRL_OPT_ITCINTEN_ENABLE   (0x00000001u)
07621 
07622 #define EDMA3_CCRL_OPT_TCINTEN_MASK      (0x00100000u)
07623 #define EDMA3_CCRL_OPT_TCINTEN_SHIFT     (0x00000014u)
07624 #define EDMA3_CCRL_OPT_TCINTEN_RESETVAL  (0x00000000u)
07625 
07626 /*----TCINTEN Tokens----*/
07627 #define EDMA3_CCRL_OPT_TCINTEN_DISABLE   (0x00000000u)
07628 #define EDMA3_CCRL_OPT_TCINTEN_ENABLE    (0x00000001u)
07629 
07630 #define EDMA3_CCRL_OPT_WIMODE_MASK       (0x00080000u)
07631 #define EDMA3_CCRL_OPT_WIMODE_SHIFT      (0x00000013u)
07632 #define EDMA3_CCRL_OPT_WIMODE_RESETVAL   (0x00000000u)
07633 
07634 /*----WIMODE Tokens----*/
07635 #define EDMA3_CCRL_OPT_WIMODE_NORMAL     (0x00000000u)
07636 #define EDMA3_CCRL_OPT_WIMODE_WI         (0x00000001u)
07637 
07638 #define EDMA3_CCRL_OPT_TCC_MASK          (0x0003F000u)
07639 #define EDMA3_CCRL_OPT_TCC_SHIFT         (0x0000000Cu)
07640 #define EDMA3_CCRL_OPT_TCC_RESETVAL      (0x00000000u)
07641 
07642 #define EDMA3_CCRL_OPT_TCCMODE_MASK      (0x00000800u)
07643 #define EDMA3_CCRL_OPT_TCCMODE_SHIFT     (0x0000000Bu)
07644 #define EDMA3_CCRL_OPT_TCCMODE_RESETVAL  (0x00000000u)
07645 
07646 /*----TCCMODE Tokens----*/
07647 #define EDMA3_CCRL_OPT_TCCMODE_NORMAL    (0x00000000u)
07648 #define EDMA3_CCRL_OPT_TCCMODE_EARLY     (0x00000001u)
07649 
07650 #define EDMA3_CCRL_OPT_FWID_MASK         (0x00000700u)
07651 #define EDMA3_CCRL_OPT_FWID_SHIFT        (0x00000008u)
07652 #define EDMA3_CCRL_OPT_FWID_RESETVAL     (0x00000000u)
07653 
07654 /*----FWID Tokens----*/
07655 #define EDMA3_CCRL_OPT_FWID_8            (0x00000000u)
07656 #define EDMA3_CCRL_OPT_FWID_16           (0x00000001u)
07657 #define EDMA3_CCRL_OPT_FWID_32           (0x00000002u)
07658 #define EDMA3_CCRL_OPT_FWID_64           (0x00000003u)
07659 #define EDMA3_CCRL_OPT_FWID_128          (0x00000004u)
07660 #define EDMA3_CCRL_OPT_FWID_256          (0x00000005u)
07661 
07662 #define EDMA3_CCRL_OPT_STATIC_MASK       (0x00000008u)
07663 #define EDMA3_CCRL_OPT_STATIC_SHIFT      (0x00000003u)
07664 #define EDMA3_CCRL_OPT_STATIC_RESETVAL   (0x00000000u)
07665 
07666 /*----STATIC Tokens----*/
07667 #define EDMA3_CCRL_OPT_STATIC_NORMAL     (0x00000000u)
07668 #define EDMA3_CCRL_OPT_STATIC_STATIC     (0x00000001u)
07669 
07670 #define EDMA3_CCRL_OPT_SYNCDIM_MASK      (0x00000004u)
07671 #define EDMA3_CCRL_OPT_SYNCDIM_SHIFT     (0x00000002u)
07672 #define EDMA3_CCRL_OPT_SYNCDIM_RESETVAL  (0x00000000u)
07673 
07674 /*----SYNCDIM Tokens----*/
07675 #define EDMA3_CCRL_OPT_SYNCDIM_ASYNC     (0x00000000u)
07676 #define EDMA3_CCRL_OPT_SYNCDIM_ABSYNC    (0x00000001u)
07677 
07678 #define EDMA3_CCRL_OPT_DAM_MASK          (0x00000002u)
07679 #define EDMA3_CCRL_OPT_DAM_SHIFT         (0x00000001u)
07680 #define EDMA3_CCRL_OPT_DAM_RESETVAL      (0x00000000u)
07681 
07682 /*----DAM Tokens----*/
07683 #define EDMA3_CCRL_OPT_DAM_INCR          (0x00000000u)
07684 #define EDMA3_CCRL_OPT_DAM_FIFO          (0x00000001u)
07685 
07686 #define EDMA3_CCRL_OPT_SAM_MASK          (0x00000001u)
07687 #define EDMA3_CCRL_OPT_SAM_SHIFT         (0x00000000u)
07688 #define EDMA3_CCRL_OPT_SAM_RESETVAL      (0x00000000u)
07689 
07690 /*----SAM Tokens----*/
07691 #define EDMA3_CCRL_OPT_SAM_INCR          (0x00000000u)
07692 #define EDMA3_CCRL_OPT_SAM_FIFO          (0x00000001u)
07693 
07694 #define EDMA3_CCRL_OPT_RESETVAL          (0x00000000u)
07695 
07696 /* SRC */
07697 
07698 #define EDMA3_CCRL_SRC_SRC_MASK          (0xFFFFFFFFu)
07699 #define EDMA3_CCRL_SRC_SRC_SHIFT         (0x00000000u)
07700 #define EDMA3_CCRL_SRC_SRC_RESETVAL      (0x00000000u)
07701 
07702 #define EDMA3_CCRL_SRC_RESETVAL          (0x00000000u)
07703 
07704 /* A_B_CNT */
07705 
07706 #define EDMA3_CCRL_A_B_CNT_BCNT_MASK     (0xFFFF0000u)
07707 #define EDMA3_CCRL_A_B_CNT_BCNT_SHIFT    (0x00000010u)
07708 #define EDMA3_CCRL_A_B_CNT_BCNT_RESETVAL (0x00000000u)
07709 
07710 #define EDMA3_CCRL_A_B_CNT_ACNT_MASK     (0x0000FFFFu)
07711 #define EDMA3_CCRL_A_B_CNT_ACNT_SHIFT    (0x00000000u)
07712 #define EDMA3_CCRL_A_B_CNT_ACNT_RESETVAL (0x00000000u)
07713 
07714 #define EDMA3_CCRL_A_B_CNT_RESETVAL      (0x00000000u)
07715 
07716 /* DST */
07717 
07718 #define EDMA3_CCRL_DST_DST_MASK          (0xFFFFFFFFu)
07719 #define EDMA3_CCRL_DST_DST_SHIFT         (0x00000000u)
07720 #define EDMA3_CCRL_DST_DST_RESETVAL      (0x00000000u)
07721 
07722 #define EDMA3_CCRL_DST_RESETVAL          (0x00000000u)
07723 
07724 /* SRC_DST_BIDX */
07725 
07726 #define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_MASK (0xFFFF0000u)
07727 #define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_SHIFT (0x00000010u)
07728 #define EDMA3_CCRL_SRC_DST_BIDX_DSTBIDX_RESETVAL (0x00000000u)
07729 
07730 #define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_MASK (0x0000FFFFu)
07731 #define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_SHIFT (0x00000000u)
07732 #define EDMA3_CCRL_SRC_DST_BIDX_SRCBIDX_RESETVAL (0x00000000u)
07733 
07734 #define EDMA3_CCRL_SRC_DST_BIDX_RESETVAL (0x00000000u)
07735 
07736 /* LINK_BCNTRLD */
07737 
07738 #define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_MASK (0xFFFF0000u)
07739 #define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_SHIFT (0x00000010u)
07740 #define EDMA3_CCRL_LINK_BCNTRLD_BCNTRLD_RESETVAL (0x00000000u)
07741 
07742 #define EDMA3_CCRL_LINK_BCNTRLD_LINK_MASK (0x0000FFFFu)
07743 #define EDMA3_CCRL_LINK_BCNTRLD_LINK_SHIFT (0x00000000u)
07744 #define EDMA3_CCRL_LINK_BCNTRLD_LINK_RESETVAL (0x00000000u)
07745 
07746 #define EDMA3_CCRL_LINK_BCNTRLD_RESETVAL (0x00000000u)
07747 
07748 /* SRC_DST_CIDX */
07749 
07750 #define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_MASK (0xFFFF0000u)
07751 #define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_SHIFT (0x00000010u)
07752 #define EDMA3_CCRL_SRC_DST_CIDX_DSTCIDX_RESETVAL (0x00000000u)
07753 
07754 #define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_MASK (0x0000FFFFu)
07755 #define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_SHIFT (0x00000000u)
07756 #define EDMA3_CCRL_SRC_DST_CIDX_SRCCIDX_RESETVAL (0x00000000u)
07757 
07758 #define EDMA3_CCRL_SRC_DST_CIDX_RESETVAL (0x00000000u)
07759 
07760 /* CCNT */
07761 
07762 #define EDMA3_CCRL_CCNT_CCNT_MASK        (0x0000FFFFu)
07763 #define EDMA3_CCRL_CCNT_CCNT_SHIFT       (0x00000000u)
07764 #define EDMA3_CCRL_CCNT_CCNT_RESETVAL    (0x00000000u)
07765 
07766 #define EDMA3_CCRL_CCNT_RESETVAL         (0x00000000u)
07767 
07768 /* ER */
07769 
07770 #define EDMA3_CCRL_ER_REG_MASK           (0xFFFFFFFFu)
07771 #define EDMA3_CCRL_ER_REG_SHIFT          (0x00000000u)
07772 #define EDMA3_CCRL_ER_REG_RESETVAL       (0x00000000u)
07773 
07774 #define EDMA3_CCRL_ER_RESETVAL           (0x00000000u)
07775 
07776 /* ERH */
07777 
07778 #define EDMA3_CCRL_ERH_REG_MASK          (0xFFFFFFFFu)
07779 #define EDMA3_CCRL_ERH_REG_SHIFT         (0x00000000u)
07780 #define EDMA3_CCRL_ERH_REG_RESETVAL      (0x00000000u)
07781 
07782 #define EDMA3_CCRL_ERH_RESETVAL          (0x00000000u)
07783 
07784 /* ECR */
07785 
07786 #define EDMA3_CCRL_ECR_REG_MASK          (0xFFFFFFFFu)
07787 #define EDMA3_CCRL_ECR_REG_SHIFT         (0x00000000u)
07788 #define EDMA3_CCRL_ECR_REG_RESETVAL      (0x00000000u)
07789 
07790 #define EDMA3_CCRL_ECR_RESETVAL          (0x00000000u)
07791 
07792 /* ECRH */
07793 
07794 #define EDMA3_CCRL_ECRH_REG_MASK         (0xFFFFFFFFu)
07795 #define EDMA3_CCRL_ECRH_REG_SHIFT        (0x00000000u)
07796 #define EDMA3_CCRL_ECRH_REG_RESETVAL     (0x00000000u)
07797 
07798 #define EDMA3_CCRL_ECRH_RESETVAL         (0x00000000u)
07799 
07800 /* ESR */
07801 
07802 #define EDMA3_CCRL_ESR_REG_MASK          (0xFFFFFFFFu)
07803 #define EDMA3_CCRL_ESR_REG_SHIFT         (0x00000000u)
07804 #define EDMA3_CCRL_ESR_REG_RESETVAL      (0x00000000u)
07805 
07806 #define EDMA3_CCRL_ESR_RESETVAL          (0x00000000u)
07807 
07808 /* ESRH */
07809 
07810 #define EDMA3_CCRL_ESRH_REG_MASK         (0xFFFFFFFFu)
07811 #define EDMA3_CCRL_ESRH_REG_SHIFT        (0x00000000u)
07812 #define EDMA3_CCRL_ESRH_REG_RESETVAL     (0x00000000u)
07813 
07814 #define EDMA3_CCRL_ESRH_RESETVAL         (0x00000000u)
07815 
07816 /* CER */
07817 
07818 #define EDMA3_CCRL_CER_REG_MASK          (0xFFFFFFFFu)
07819 #define EDMA3_CCRL_CER_REG_SHIFT         (0x00000000u)
07820 #define EDMA3_CCRL_CER_REG_RESETVAL      (0x00000000u)
07821 
07822 #define EDMA3_CCRL_CER_RESETVAL          (0x00000000u)
07823 
07824 /* CERH */
07825 
07826 #define EDMA3_CCRL_CERH_REG_MASK         (0xFFFFFFFFu)
07827 #define EDMA3_CCRL_CERH_REG_SHIFT        (0x00000000u)
07828 #define EDMA3_CCRL_CERH_REG_RESETVAL     (0x00000000u)
07829 
07830 #define EDMA3_CCRL_CERH_RESETVAL         (0x00000000u)
07831 
07832 /* EER */
07833 
07834 #define EDMA3_CCRL_EER_REG_MASK          (0xFFFFFFFFu)
07835 #define EDMA3_CCRL_EER_REG_SHIFT         (0x00000000u)
07836 #define EDMA3_CCRL_EER_REG_RESETVAL      (0x00000000u)
07837 
07838 #define EDMA3_CCRL_EER_RESETVAL          (0x00000000u)
07839 
07840 /* EERH */
07841 
07842 #define EDMA3_CCRL_EERH_REG_MASK         (0xFFFFFFFFu)
07843 #define EDMA3_CCRL_EERH_REG_SHIFT        (0x00000000u)
07844 #define EDMA3_CCRL_EERH_REG_RESETVAL     (0x00000000u)
07845 
07846 #define EDMA3_CCRL_EERH_RESETVAL         (0x00000000u)
07847 
07848 /* EECR */
07849 
07850 #define EDMA3_CCRL_EECR_REG_MASK         (0xFFFFFFFFu)
07851 #define EDMA3_CCRL_EECR_REG_SHIFT        (0x00000000u)
07852 #define EDMA3_CCRL_EECR_REG_RESETVAL     (0x00000000u)
07853 
07854 #define EDMA3_CCRL_EECR_RESETVAL         (0x00000000u)
07855 
07856 /* EECRH */
07857 
07858 #define EDMA3_CCRL_EECRH_REG_MASK        (0xFFFFFFFFu)
07859 #define EDMA3_CCRL_EECRH_REG_SHIFT       (0x00000000u)
07860 #define EDMA3_CCRL_EECRH_REG_RESETVAL    (0x00000000u)
07861 
07862 #define EDMA3_CCRL_EECRH_RESETVAL        (0x00000000u)
07863 
07864 /* EESR */
07865 
07866 #define EDMA3_CCRL_EESR_REG_MASK         (0xFFFFFFFFu)
07867 #define EDMA3_CCRL_EESR_REG_SHIFT        (0x00000000u)
07868 #define EDMA3_CCRL_EESR_REG_RESETVAL     (0x00000000u)
07869 
07870 #define EDMA3_CCRL_EESR_RESETVAL         (0x00000000u)
07871 
07872 /* EESRH */
07873 
07874 #define EDMA3_CCRL_EESRH_REG_MASK        (0xFFFFFFFFu)
07875 #define EDMA3_CCRL_EESRH_REG_SHIFT       (0x00000000u)
07876 #define EDMA3_CCRL_EESRH_REG_RESETVAL    (0x00000000u)
07877 
07878 #define EDMA3_CCRL_EESRH_RESETVAL        (0x00000000u)
07879 
07880 /* SER */
07881 
07882 #define EDMA3_CCRL_SER_REG_MASK          (0xFFFFFFFFu)
07883 #define EDMA3_CCRL_SER_REG_SHIFT         (0x00000000u)
07884 #define EDMA3_CCRL_SER_REG_RESETVAL      (0x00000000u)
07885 
07886 #define EDMA3_CCRL_SER_RESETVAL          (0x00000000u)
07887 
07888 /* SERH */
07889 
07890 #define EDMA3_CCRL_SERH_REG_MASK         (0xFFFFFFFFu)
07891 #define EDMA3_CCRL_SERH_REG_SHIFT        (0x00000000u)
07892 #define EDMA3_CCRL_SERH_REG_RESETVAL     (0x00000000u)
07893 
07894 #define EDMA3_CCRL_SERH_RESETVAL         (0x00000000u)
07895 
07896 /* SECR */
07897 
07898 #define EDMA3_CCRL_SECR_REG_MASK         (0xFFFFFFFFu)
07899 #define EDMA3_CCRL_SECR_REG_SHIFT        (0x00000000u)
07900 #define EDMA3_CCRL_SECR_REG_RESETVAL     (0x00000000u)
07901 
07902 #define EDMA3_CCRL_SECR_RESETVAL         (0x00000000u)
07903 
07904 /* SECRH */
07905 
07906 #define EDMA3_CCRL_SECRH_REG_MASK        (0xFFFFFFFFu)
07907 #define EDMA3_CCRL_SECRH_REG_SHIFT       (0x00000000u)
07908 #define EDMA3_CCRL_SECRH_REG_RESETVAL    (0x00000000u)
07909 
07910 #define EDMA3_CCRL_SECRH_RESETVAL        (0x00000000u)
07911 
07912 /* IER */
07913 
07914 #define EDMA3_CCRL_IER_REG_MASK          (0xFFFFFFFFu)
07915 #define EDMA3_CCRL_IER_REG_SHIFT         (0x00000000u)
07916 #define EDMA3_CCRL_IER_REG_RESETVAL      (0x00000000u)
07917 
07918 #define EDMA3_CCRL_IER_RESETVAL          (0x00000000u)
07919 
07920 /* IERH */
07921 
07922 #define EDMA3_CCRL_IERH_REG_MASK         (0xFFFFFFFFu)
07923 #define EDMA3_CCRL_IERH_REG_SHIFT        (0x00000000u)
07924 #define EDMA3_CCRL_IERH_REG_RESETVAL     (0x00000000u)
07925 
07926 #define EDMA3_CCRL_IERH_RESETVAL         (0x00000000u)
07927 
07928 /* IECR */
07929 
07930 #define EDMA3_CCRL_IECR_REG_MASK         (0xFFFFFFFFu)
07931 #define EDMA3_CCRL_IECR_REG_SHIFT        (0x00000000u)
07932 #define EDMA3_CCRL_IECR_REG_RESETVAL     (0x00000000u)
07933 
07934 #define EDMA3_CCRL_IECR_RESETVAL         (0x00000000u)
07935 
07936 /* IECRH */
07937 
07938 #define EDMA3_CCRL_IECRH_REG_MASK        (0xFFFFFFFFu)
07939 #define EDMA3_CCRL_IECRH_REG_SHIFT       (0x00000000u)
07940 #define EDMA3_CCRL_IECRH_REG_RESETVAL    (0x00000000u)
07941 
07942 #define EDMA3_CCRL_IECRH_RESETVAL        (0x00000000u)
07943 
07944 /* IESR */
07945 
07946 #define EDMA3_CCRL_IESR_REG_MASK         (0xFFFFFFFFu)
07947 #define EDMA3_CCRL_IESR_REG_SHIFT        (0x00000000u)
07948 #define EDMA3_CCRL_IESR_REG_RESETVAL     (0x00000000u)
07949 
07950 #define EDMA3_CCRL_IESR_RESETVAL         (0x00000000u)
07951 
07952 /* IESRH */
07953 
07954 #define EDMA3_CCRL_IESRH_REG_MASK        (0xFFFFFFFFu)
07955 #define EDMA3_CCRL_IESRH_REG_SHIFT       (0x00000000u)
07956 #define EDMA3_CCRL_IESRH_REG_RESETVAL    (0x00000000u)
07957 
07958 #define EDMA3_CCRL_IESRH_RESETVAL        (0x00000000u)
07959 
07960 /* IPR */
07961 
07962 #define EDMA3_CCRL_IPR_REG_MASK          (0xFFFFFFFFu)
07963 #define EDMA3_CCRL_IPR_REG_SHIFT         (0x00000000u)
07964 #define EDMA3_CCRL_IPR_REG_RESETVAL      (0x00000000u)
07965 
07966 #define EDMA3_CCRL_IPR_RESETVAL          (0x00000000u)
07967 
07968 /* IPRH */
07969 
07970 #define EDMA3_CCRL_IPRH_REG_MASK         (0xFFFFFFFFu)
07971 #define EDMA3_CCRL_IPRH_REG_SHIFT        (0x00000000u)
07972 #define EDMA3_CCRL_IPRH_REG_RESETVAL     (0x00000000u)
07973 
07974 #define EDMA3_CCRL_IPRH_RESETVAL         (0x00000000u)
07975 
07976 /* ICR */
07977 
07978 #define EDMA3_CCRL_ICR_REG_MASK          (0xFFFFFFFFu)
07979 #define EDMA3_CCRL_ICR_REG_SHIFT         (0x00000000u)
07980 #define EDMA3_CCRL_ICR_REG_RESETVAL      (0x00000000u)
07981 
07982 #define EDMA3_CCRL_ICR_RESETVAL          (0x00000000u)
07983 
07984 /* ICRH */
07985 
07986 #define EDMA3_CCRL_ICRH_REG_MASK         (0xFFFFFFFFu)
07987 #define EDMA3_CCRL_ICRH_REG_SHIFT        (0x00000000u)
07988 #define EDMA3_CCRL_ICRH_REG_RESETVAL     (0x00000000u)
07989 
07990 #define EDMA3_CCRL_ICRH_RESETVAL         (0x00000000u)
07991 
07992 /* IEVAL */
07993 
07994 #define EDMA3_CCRL_IEVAL_REG_MASK        (0xFFFFFFFFu)
07995 #define EDMA3_CCRL_IEVAL_REG_SHIFT       (0x00000000u)
07996 #define EDMA3_CCRL_IEVAL_REG_RESETVAL    (0x00000000u)
07997 
07998 #define EDMA3_CCRL_IEVAL_RESETVAL        (0x00000000u)
07999 
08000 /* QER */
08001 
08002 #define EDMA3_CCRL_QER_REG_MASK          (0xFFFFFFFFu)
08003 #define EDMA3_CCRL_QER_REG_SHIFT         (0x00000000u)
08004 #define EDMA3_CCRL_QER_REG_RESETVAL      (0x00000000u)
08005 
08006 #define EDMA3_CCRL_QER_RESETVAL          (0x00000000u)
08007 
08008 /* QEER */
08009 
08010 #define EDMA3_CCRL_QEER_REG_MASK         (0xFFFFFFFFu)
08011 #define EDMA3_CCRL_QEER_REG_SHIFT        (0x00000000u)
08012 #define EDMA3_CCRL_QEER_REG_RESETVAL     (0x00000000u)
08013 
08014 #define EDMA3_CCRL_QEER_RESETVAL         (0x00000000u)
08015 
08016 /* QEECR */
08017 
08018 #define EDMA3_CCRL_QEECR_REG_MASK        (0xFFFFFFFFu)
08019 #define EDMA3_CCRL_QEECR_REG_SHIFT       (0x00000000u)
08020 #define EDMA3_CCRL_QEECR_REG_RESETVAL    (0x00000000u)
08021 
08022 #define EDMA3_CCRL_QEECR_RESETVAL        (0x00000000u)
08023 
08024 /* QEESR */
08025 
08026 #define EDMA3_CCRL_QEESR_REG_MASK        (0xFFFFFFFFu)
08027 #define EDMA3_CCRL_QEESR_REG_SHIFT       (0x00000000u)
08028 #define EDMA3_CCRL_QEESR_REG_RESETVAL    (0x00000000u)
08029 
08030 #define EDMA3_CCRL_QEESR_RESETVAL        (0x00000000u)
08031 
08032 /* QSER */
08033 
08034 #define EDMA3_CCRL_QSER_REG_MASK         (0xFFFFFFFFu)
08035 #define EDMA3_CCRL_QSER_REG_SHIFT        (0x00000000u)
08036 #define EDMA3_CCRL_QSER_REG_RESETVAL     (0x00000000u)
08037 
08038 #define EDMA3_CCRL_QSER_RESETVAL         (0x00000000u)
08039 
08040 /* QSECR */
08041 
08042 #define EDMA3_CCRL_QSECR_REG_MASK        (0xFFFFFFFFu)
08043 #define EDMA3_CCRL_QSECR_REG_SHIFT       (0x00000000u)
08044 #define EDMA3_CCRL_QSECR_REG_RESETVAL    (0x00000000u)
08045 
08046 #define EDMA3_CCRL_QSECR_RESETVAL        (0x00000000u)
08047 
08048 #ifdef __cplusplus
08049 }
08050 #endif /* extern "C" */
08051 
08052 #endif /* _EDMA3_RL_CC_H_ */