1 /* 2 * Copyright (c) 2012, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * */ 32 /* 33 * ======== InterruptBenelli.xdc ======== 34 * 35 */ 36 37 import ti.sdo.utils.MultiProc; 38 39 /*! 40 * ======== InterruptBenelli ======== 41 * TI81xx/Ducati based interrupt manager 42 */ 43 44 module InterruptBenelli inherits ti.sdo.ipc.notifyDrivers.IInterrupt 45 { 46 /* Base address for the Mailbox subsystem */ 47 config UInt32 mailboxBaseAddr[10]; 48 49 /* TODO: Document how this table is generated */ 50 config UInt32 mailboxTable[64]; 51 52 /* Base address for the Ducati CTRL register */ 53 config UInt32 ducatiCtrlBaseAddr = 0x40001000; 54 55 config UInt32 benelliInterruptTable[8]; 56 57 config UInt32 procIdTable[8]; 58 internal: 59 60 /*! Statically retrieve procIds to avoid doing this at runtime */ 61 config UInt eve0ProcId = MultiProc.INVALIDID; 62 config UInt eve1ProcId = MultiProc.INVALIDID; 63 config UInt eve2ProcId = MultiProc.INVALIDID; 64 config UInt eve3ProcId = MultiProc.INVALIDID; 65 config UInt dsp0ProcId = MultiProc.INVALIDID; 66 config UInt dsp1ProcId = MultiProc.INVALIDID; 67 config UInt videoProcId = MultiProc.INVALIDID; 68 config UInt vpssProcId = MultiProc.INVALIDID; 69 70 /*! Function table */ 71 struct FxnTable { 72 Fxn func; 73 UArg arg; 74 } 75 76 /*! Stub to be plugged for inter-ducati interrupts */ 77 Void intShmDucatiStub(UArg arg); 78 79 /*! Stub to be plugged for intra-ducati interrupts */ 80 Void intShmMbxStub(UArg arg); 81 82 struct Module_State { 83 /* 84 * Create a function table of length 8 (Total number of cores in the 85 * System) for each M4 core. 86 */ 87 FxnTable fxnTable[8]; 88 UInt numPlugged[10]; /* # of times interrupt registered */ 89 }; 90 } 91 /* 92 * @(#) ti.sdo.ipc.family.vayu; 1, 0, 0, 0,1; 5-22-2012 16:20:39; /db/vtree/library/trees/ipc/ipc-h32/src/ xlibrary 93 94 */ 95