1    /* 
     2     * Copyright (c) 2012, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     * */
    32    /*
    33     *  ======== InterruptArp32.xdc ========
    34     *
    35     */
    36     
    37    import ti.sdo.utils.MultiProc;
    38    
    39    /*!
    40     *  ======== InterruptArp32 ======== 
    41     *  ARP32 based interrupt manager
    42     */
    43    
    44    module InterruptArp32 inherits ti.sdo.ipc.notifyDrivers.IInterrupt
    45    {
    46        /* Base address for the Mailbox subsystem */
    47        config UInt32 mailboxBaseAddr[10];
    48    
    49        /* TODO: Document how this table is generated */
    50        config UInt32 mailboxTable[64];
    51    
    52        config UInt32 eveInterruptTable[8];
    53    
    54        config UInt32 procIdTable[8];
    55    
    56    internal:
    57    
    58        /*! Statically retrieve procIds to avoid doing this at runtime */    
    59        config UInt eve0ProcId   = MultiProc.INVALIDID;
    60        config UInt eve1ProcId   = MultiProc.INVALIDID;
    61        config UInt eve2ProcId   = MultiProc.INVALIDID;
    62        config UInt eve3ProcId   = MultiProc.INVALIDID;
    63        config UInt dsp0ProcId   = MultiProc.INVALIDID;
    64        config UInt dsp1ProcId   = MultiProc.INVALIDID;
    65        config UInt videoProcId  = MultiProc.INVALIDID;
    66        config UInt vpssProcId   = MultiProc.INVALIDID;
    67    
    68        /*! Function table */
    69        struct FxnTable {
    70            Fxn    func;
    71            UArg   arg;
    72        }
    73    
    74        /*! Stub to be plugged for dsp-arp32 interrupts */
    75        Void intShmStub(UArg arg);
    76        
    77        struct Module_State {        
    78            /* 
    79             * Create a function table of length 8 (Total number of cores in the
    80             * System) for each EVE core.
    81             */
    82            FxnTable   fxnTable[8];
    83            UInt       numPlugged[10];  /* # of times the interrupt was registered */
    84        };
    85    }
    86    /*
    87     *  @(#) ti.sdo.ipc.family.vayu; 1, 0, 0, 0,1; 5-22-2012 16:20:39; /db/vtree/library/trees/ipc/ipc-h32/src/ xlibrary
    88    
    89     */
    90