TI Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3220SF:1

Tool Chain Version: 20.2.0

BIOS Version: bios_6_82_00_13_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	189
Hwi_restore()	22
Hwi_disable()	26
Hwi dispatcher prolog	143
Hwi dispatcher epilog	334
Hwi dispatcher	472
Hardware Interrupt to Blocked Task	758
Hardware Interrupt to Software Interrupt	502
Swi_enable()	130
Swi_disable()	26
Post Software Interrupt Again	55
Post Software Interrupt without Context Switch	133
Post Software Interrupt with Context Switch	253
Create a New Task without Context Switch	4017
Set a Task Priority without a Context Switch	259
Task_yield()	272
Post Semaphore No Waiting Task	140
Post Semaphore No Task Switch	263
Post Semaphore with Task Switch	347
Pend on Semaphore No Context Switch	112
Pend on Semaphore with Task Switch	407
Clock_getTicks()	24
POSIX Create a New Task without Context Switch	7492
POSIX Set a Task Priority without a Context Switch	336
POSIX Post Semaphore No Waiting Task	165
POSIX Post Semaphore No Task Switch	292
POSIX Post Semaphore with Task Switch	378
POSIX Pend on Semaphore No Context Switch	129
POSIX Pend on Semaphore with Task Switch	436

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.