TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432E401Y

Tool Chain Version: 20.2.0

BIOS Version: bios_6_82_00_13_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	190
Hwi_restore()	13
Hwi_disable()	9
Hwi dispatcher prolog	121
Hwi dispatcher epilog	234
Hwi dispatcher	338
Hardware Interrupt to Blocked Task	538
Hardware Interrupt to Software Interrupt	350
Swi_enable()	73
Swi_disable()	14
Post Software Interrupt Again	36
Post Software Interrupt without Context Switch	93
Post Software Interrupt with Context Switch	178
Create a New Task without Context Switch	2444
Set a Task Priority without a Context Switch	155
Task_yield()	216
Post Semaphore No Waiting Task	88
Post Semaphore No Task Switch	173
Post Semaphore with Task Switch	264
Pend on Semaphore No Context Switch	73
Pend on Semaphore with Task Switch	289
Clock_getTicks()	14
POSIX Create a New Task without Context Switch	4428
POSIX Set a Task Priority without a Context Switch	205
POSIX Post Semaphore No Waiting Task	100
POSIX Post Semaphore No Task Switch	190
POSIX Post Semaphore with Task Switch	277
POSIX Pend on Semaphore No Context Switch	87
POSIX Pend on Semaphore with Task Switch	303

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.