IAR Cortex-M4 Timing Benchmarks

Target Platform: ti.platforms.simplelink:CC3220SF:1

Tool Chain Version: 8.42.1.233

BIOS Version: bios_6_82_00_13_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	231
Hwi_restore()	23
Hwi_disable()	25
Hwi dispatcher prolog	179
Hwi dispatcher epilog	362
Hwi dispatcher	529
Hardware Interrupt to Blocked Task	821
Hardware Interrupt to Software Interrupt	555
Swi_enable()	119
Swi_disable()	31
Post Software Interrupt Again	29
Post Software Interrupt without Context Switch	128
Post Software Interrupt with Context Switch	265
Create a New Task without Context Switch	3788
Set a Task Priority without a Context Switch	270
Task_yield()	316
Post Semaphore No Waiting Task	121
Post Semaphore No Task Switch	276
Post Semaphore with Task Switch	368
Pend on Semaphore No Context Switch	89
Pend on Semaphore with Task Switch	415
Clock_getTicks()	28
POSIX Create a New Task without Context Switch	6971
POSIX Set a Task Priority without a Context Switch	352
POSIX Post Semaphore No Waiting Task	155
POSIX Post Semaphore No Task Switch	307
POSIX Post Semaphore with Task Switch	390
POSIX Pend on Semaphore No Context Switch	69
POSIX Pend on Semaphore with Task Switch	429

The M4 target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi CDOCs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.