IAR Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432E401Y

Tool Chain Version: 8.42.1.233

BIOS Version: bios_6_82_00_13_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	205
Hwi_restore()	10
Hwi_disable()	10
Hwi dispatcher prolog	141
Hwi dispatcher epilog	247
Hwi dispatcher	374
Hardware Interrupt to Blocked Task	575
Hardware Interrupt to Software Interrupt	376
Swi_enable()	72
Swi_disable()	17
Post Software Interrupt Again	20
Post Software Interrupt without Context Switch	85
Post Software Interrupt with Context Switch	175
Create a New Task without Context Switch	2248
Set a Task Priority without a Context Switch	164
Task_yield()	232
Post Semaphore No Waiting Task	71
Post Semaphore No Task Switch	169
Post Semaphore with Task Switch	262
Pend on Semaphore No Context Switch	58
Pend on Semaphore with Task Switch	300
Clock_getTicks()	13
POSIX Create a New Task without Context Switch	4016
POSIX Set a Task Priority without a Context Switch	206
POSIX Post Semaphore No Waiting Task	88
POSIX Post Semaphore No Task Switch	185
POSIX Post Semaphore with Task Switch	276
POSIX Pend on Semaphore No Context Switch	48
POSIX Pend on Semaphore with Task Switch	304

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.