GCC Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432E401Y

Tool Chain Version: 9.2.1

BIOS Version: bios_6_82_00_13_eng

XDCTools Version: xdctools_3_61_00_16_core

Benchmark	Cycles
Interrupt Latency	358
Hwi_restore()	9
Hwi_disable()	13
Hwi dispatcher prolog	161
Hwi dispatcher epilog	263
Hwi dispatcher	416
Hardware Interrupt to Blocked Task	714
Hardware Interrupt to Software Interrupt	453
Swi_enable()	78
Swi_disable()	19
Post Software Interrupt Again	34
Post Software Interrupt without Context Switch	94
Post Software Interrupt with Context Switch	217
Create a New Task without Context Switch	3637
Set a Task Priority without a Context Switch	189
Task_yield()	283
Post Semaphore No Waiting Task	111
Post Semaphore No Task Switch	265
Post Semaphore with Task Switch	377
Pend on Semaphore No Context Switch	71
Pend on Semaphore with Task Switch	402
Clock_getTicks()	12
POSIX Create a New Task without Context Switch	6987
POSIX Set a Task Priority without a Context Switch	256
POSIX Post Semaphore No Waiting Task	120
POSIX Post Semaphore No Task Switch	279
POSIX Post Semaphore with Task Switch	394
POSIX Pend on Semaphore No Context Switch	85
POSIX Pend on Semaphore with Task Switch	418

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.