TI Cortex-M4 Timing Benchmarks
Target Platform: ti.platforms.simplelink:CC3200:1
Tool Chain Version: 18.12.2
BIOS Version: bios_6_76_01_11_eng_k3
XDCTools Version: xdctools_3_55_01_20_core_eng
Benchmark | Cycles |
---|---|
Interrupt Latency | 126 |
Hwi_restore() | 11 |
Hwi_disable() | 15 |
Hwi dispatcher prolog | 114 |
Hwi dispatcher epilog | 235 |
Hwi dispatcher | 342 |
Hardware Interrupt to Blocked Task | 564 |
Hardware Interrupt to Software Interrupt | 396 |
Swi_enable() | 80 |
Swi_disable() | 14 |
Post Software Interrupt Again | 39 |
Post Software Interrupt without Context Switch | 107 |
Post Software Interrupt with Context Switch | 226 |
Create a New Task without Context Switch | 2817 |
Set a Task Priority without a Context Switch | 182 |
Task_yield() | 224 |
Post Semaphore No Waiting Task | 104 |
Post Semaphore No Task Switch | 205 |
Post Semaphore with Task Switch | 277 |
Pend on Semaphore No Context Switch | 85 |
Pend on Semaphore with Task Switch | 310 |
Clock_getTicks() | 12 |
POSIX Create a New Task without Context Switch | 5197 |
POSIX Set a Task Priority without a Context Switch | 251 |
POSIX Post Semaphore No Waiting Task | 117 |
POSIX Post Semaphore No Task Switch | 219 |
POSIX Post Semaphore with Task Switch | 291 |
POSIX Pend on Semaphore No Context Switch | 100 |
POSIX Pend on Semaphore with Task Switch | 330 |
The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –float_support=vfplib –abi=eabi -q -ms –opt_for_speed=2 –program_level_compile -o3”.
To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.
See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.