TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 18.12.2

BIOS Version: bios_6_76_01_11_eng_k3

XDCTools Version: xdctools_3_55_01_20_core_eng

Benchmark	Cycles
Interrupt Latency	136
Hwi_restore()	6
Hwi_disable()	8
Hwi dispatcher prolog	110
Hwi dispatcher epilog	212
Hwi dispatcher	312
Hardware Interrupt to Blocked Task	500
Hardware Interrupt to Software Interrupt	328
Swi_enable()	60
Swi_disable()	9
Post Software Interrupt Again	31
Post Software Interrupt without Context Switch	86
Post Software Interrupt with Context Switch	162
Create a New Task without Context Switch	2174
Set a Task Priority without a Context Switch	136
Task_yield()	204
Post Semaphore No Waiting Task	78
Post Semaphore No Task Switch	160
Post Semaphore with Task Switch	250
Pend on Semaphore No Context Switch	64
Pend on Semaphore with Task Switch	263
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	3876
POSIX Set a Task Priority without a Context Switch	183
POSIX Post Semaphore No Waiting Task	87
POSIX Post Semaphore No Task Switch	172
POSIX Post Semaphore with Task Switch	263
POSIX Pend on Semaphore No Context Switch	76
POSIX Pend on Semaphore with Task Switch	278

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.