TI Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.msp432:MSP432P401R:1

Tool Chain Version: 18.12.2

BIOS Version: bios_6_76_01_11_eng_k3

XDCTools Version: xdctools_3_55_01_20_core_eng

Benchmark	Cycles
Interrupt Latency	137
Hwi_restore()	6
Hwi_disable()	7
Hwi dispatcher prolog	114
Hwi dispatcher epilog	223
Hwi dispatcher	326
Hardware Interrupt to Blocked Task	516
Hardware Interrupt to Software Interrupt	344
Swi_enable()	60
Swi_disable()	9
Post Software Interrupt Again	31
Post Software Interrupt without Context Switch	88
Post Software Interrupt with Context Switch	168
Create a New Task without Context Switch	2255
Set a Task Priority without a Context Switch	140
Task_yield()	205
Post Semaphore No Waiting Task	80
Post Semaphore No Task Switch	164
Post Semaphore with Task Switch	254
Pend on Semaphore No Context Switch	66
Pend on Semaphore with Task Switch	270
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	4036
POSIX Set a Task Priority without a Context Switch	185
POSIX Post Semaphore No Waiting Task	89
POSIX Post Semaphore No Task Switch	175
POSIX Post Semaphore with Task Switch	266
POSIX Pend on Semaphore No Context Switch	79
POSIX Pend on Semaphore with Task Switch	284

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings: “–endian=little -mv7M4 –abi=eabi –float_support=fpv4spd16 -ms –opt_for_speed=2 –program_level_compile -o3”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

To minimize the effects of wait states, the performance measurements are collected at optimal CPU clock speeds on MSP432 and Tiva devices.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.