GCC Cortex-M4 with hard FP Timing Benchmarks

Target Platform: ti.platforms.tiva:TM4C123GH6PM:1

Tool Chain Version: 7.2.1

BIOS Version: bios_6_76_01_11_eng_k3

XDCTools Version: xdctools_3_55_01_20_core_eng

Benchmark	Cycles
Interrupt Latency	151
Hwi_restore()	8
Hwi_disable()	9
Hwi dispatcher prolog	141
Hwi dispatcher epilog	240
Hwi dispatcher	372
Hardware Interrupt to Blocked Task	627
Hardware Interrupt to Software Interrupt	404
Swi_enable()	72
Swi_disable()	14
Post Software Interrupt Again	30
Post Software Interrupt without Context Switch	85
Post Software Interrupt with Context Switch	190
Create a New Task without Context Switch	3484
Set a Task Priority without a Context Switch	157
Task_yield()	257
Post Semaphore No Waiting Task	96
Post Semaphore No Task Switch	229
Post Semaphore with Task Switch	335
Pend on Semaphore No Context Switch	58
Pend on Semaphore with Task Switch	355
Clock_getTicks()	8
POSIX Create a New Task without Context Switch	6879
POSIX Set a Task Priority without a Context Switch	223
POSIX Post Semaphore No Waiting Task	107
POSIX Post Semaphore No Task Switch	242
POSIX Post Semaphore with Task Switch	348
POSIX Pend on Semaphore No Context Switch	71
POSIX Pend on Semaphore with Task Switch	366

The benchmark application was built using BIOS.LibType_Custom with the following BIOS.customCCOpts settings:

“-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mabi=aapcs -O3 -Wunused -Wunknown-pragmas -ffunction-sections -fdata-sections -Dti_sysbios_Build_useHwiMacros -Dfar= -D__DYNAMIC_REENT__”.

The M4F target also supports zero latency interrupts. See ti.sysbios.family.arm.m3.Hwi cdocs for details.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.