GCC Cortex-A9 with hard FP Timing Benchmarks

Target Platform: ti.platforms.sdp4430

Tool Chain Version: 7.2.1

BIOS Version: bios_6_76_01_10_eng_k3

XDCTools Version: xdctools_3_55_01_20_core_eng

Benchmark	Cycles
Interrupt Latency	314
Hwi_restore()	9
Hwi_disable()	5
Hwi dispatcher prolog	194
Hwi dispatcher epilog	166
Hwi dispatcher	366
Hardware Interrupt to Blocked Task	580
Hardware Interrupt to Software Interrupt	386
Swi_enable()	62
Swi_disable()	1
Post Software Interrupt Again	25
Post Software Interrupt without Context Switch	82
Post Software Interrupt with Context Switch	152
Create a New Task without Context Switch	1899
Set a Task Priority without a Context Switch	103
Task_yield()	225
Post Semaphore No Waiting Task	82
Post Semaphore No Task Switch	167
Post Semaphore with Task Switch	266
Pend on Semaphore No Context Switch	36
Pend on Semaphore with Task Switch	267
Clock_getTicks()	7
POSIX Create a New Task without Context Switch	3664
POSIX Set a Task Priority without a Context Switch	100
POSIX Post Semaphore No Waiting Task	85
POSIX Post Semaphore No Task Switch	170
POSIX Post Semaphore with Task Switch	291
POSIX Pend on Semaphore No Context Switch	48
POSIX Pend on Semaphore with Task Switch	268

As the timer used to run these benchmarks is run at 1/2 the CPU frequency, an deviation of +-2 cycles is to be expected.

See the SYS/BIOS User’s Guide for more information regarding how interrupt latency is calculated.