This module provides APIs to connect an IRQ source to
an IRQ line on the target cpu's interrupt controller
using the Interrupt Crossbar module in the hardware.
Below is an example of how to override the default mapping of
interrupt 23 on a M4 so that the interrupt source is I2C module 1
rather than Display Controller interrupt request(mapped by default):
#include <ti/sysbios/family/arm/m3/Hwi.h>
#include <ti/sysbios/family/shared/vayu/IntXbar.h>
Void myI2CHandler(UArg arg)
{
// Handler Code
}
Int main(Int argc, Char* argv[])
{
Hwi_Params params;
Hwi_Params_init(¶ms);
// Connect IRQ 23 to Interrupt source index 51 (I2C1_IRQ)
IntXbar_connectIRQ(23, 51);
// Alternately, IntXbar_connect API can be used. This
// API expects XBAR instance number as an argument.
//
// Connect Xbar Instance 1 (IRQ 23) to Interrupt
// source index 51 (I2C1_IRQ)
//
// IntXbar_connect(1, 51);
// create a corresponding interrupt handler
params.arg = 23; // pass the Interrupt number to the handler
Hwi_create(23, myI2CHandler, ¶ms, NULL);
BIOS_start();
return (0);
}
Here is how you would define the same interrupt handler statically
in a configuration script:
var Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
// Connect IRQ 23 to Interrupt source index 51 (I2C1_IRQ)
IntXbar.connectIRQMeta(23, 51);
// Alternately, the connectIRQMeta API can be used. This
// API expects XBAR instance number as an argument.
//
// Connect Xbar Instance 1 (IRQ 23) to Interrupt
// source index 51 (I2C1_IRQ)
//
// IntXbar.connectMeta(1, 51);
var hwiParams = new Hwi.Params();
hwiParams.arg = 23;
Program.global.staticHwi = Hwi.create(23, '&myTimerHandler', hwiParams);
const IntXbar_MMR_LOCK2_LOCK |
|
MMR Lock 2 lock value
#define IntXbar_MMR_LOCK2_LOCK (UInt32)0xFDF45530
const IntXbar_MMR_LOCK2_UNLOCK |
|
MMR Lock 2 unlock value
#define IntXbar_MMR_LOCK2_UNLOCK (UInt32)0xF757FDC0
const IntXbar_MMR_OFFSET_A15 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__MPU_IRQ_4_5" register
#define IntXbar_MMR_OFFSET_A15 (UInt32)0xA48
const IntXbar_MMR_OFFSET_BENELLI_IPU1 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__IPU1_IRQ_23_24" register
#define IntXbar_MMR_OFFSET_BENELLI_IPU1 (UInt32)0x7E0
const IntXbar_MMR_OFFSET_BENELLI_IPU2 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__IPU2_IRQ_23_24" register
#define IntXbar_MMR_OFFSET_BENELLI_IPU2 (UInt32)0x854
const IntXbar_MMR_OFFSET_DSP0 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__DSP1_IRQ_32_33" register
#define IntXbar_MMR_OFFSET_DSP0 (UInt32)0x948
const IntXbar_MMR_OFFSET_DSP1 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__DSP2_IRQ_32_33" register
#define IntXbar_MMR_OFFSET_DSP1 (UInt32)0x9c8
const IntXbar_MMR_OFFSET_EVE0 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__EVE1_IRQ_0_1" register
#define IntXbar_MMR_OFFSET_EVE0 (UInt32)0x7A0
const IntXbar_MMR_OFFSET_EVE1 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__EVE2_IRQ_0_1" register
#define IntXbar_MMR_OFFSET_EVE1 (UInt32)0x7B0
const IntXbar_MMR_OFFSET_EVE2 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__EVE3_IRQ_0_1" register
#define IntXbar_MMR_OFFSET_EVE2 (UInt32)0x7C0
const IntXbar_MMR_OFFSET_EVE3 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__EVE4_IRQ_0_1" register
#define IntXbar_MMR_OFFSET_EVE3 (UInt32)0x7D0
const IntXbar_MMR_OFFSET_LOCK2 |
|
Offset of MMR Lock 2 register
#define IntXbar_MMR_OFFSET_LOCK2 (UInt32)0x544
DETAILS
Register to lock memory region starting at address offset 0x000007A0
and ending at address offset 0x00000D9F
const IntXbar_NUM_A15_XBAR_INST |
|
Number of XBAR instances per A15 Core
#define IntXbar_NUM_A15_XBAR_INST (UInt16)152
const IntXbar_NUM_BENELLI_XBAR_INST |
|
Number of XBAR instances per Benelli Core
#define IntXbar_NUM_BENELLI_XBAR_INST (UInt16)57
const IntXbar_NUM_DSP_XBAR_INST |
|
Number of XBAR instances per DSP core
#define IntXbar_NUM_DSP_XBAR_INST (UInt16)64
const IntXbar_NUM_EVE_XBAR_INST |
|
Number of XBAR instances per EVE core
#define IntXbar_NUM_EVE_XBAR_INST (UInt16)8
const IntXbar_numIrqXbarInputs |
|
Number of IRQ XBAR inputs
#define IntXbar_numIrqXbarInputs (UInt16)420
config IntXbar_A_badA15IRQNum // module-wide |
|
Assert if A15 IRQ number is < 4 or == 5 or == 6 or == 131 or == 132 or
== 139 or == 140 or > 159
extern const Assert_Id IntXbar_A_badA15IRQNum;
config IntXbar_A_badA15XbarInstanceNum // module-wide |
|
Assert if A15 XBAR instance number < 1 or > 152
extern const Assert_Id IntXbar_A_badA15XbarInstanceNum;
config IntXbar_A_badBenelliIRQNum // module-wide |
|
Assert if Benelli/IPU IRQ number is < 23 or > 79
extern const Assert_Id IntXbar_A_badBenelliIRQNum;
config IntXbar_A_badBenelliIpuId // module-wide |
|
Assert if Benelli IPU Id invalid
extern const Assert_Id IntXbar_A_badBenelliIpuId;
config IntXbar_A_badBenelliXbarInstanceNum // module-wide |
|
Assert if Benelli XBAR instance number < 1 or > 57
extern const Assert_Id IntXbar_A_badBenelliXbarInstanceNum;
config IntXbar_A_badDspCpuId // module-wide |
|
Assert if DSP CPU Id invalid
extern const Assert_Id IntXbar_A_badDspCpuId;
config IntXbar_A_badDspIRQNum // module-wide |
|
Assert if DSP IRQ number is < 32 or > 95
extern const Assert_Id IntXbar_A_badDspIRQNum;
config IntXbar_A_badDspXbarInstanceNum // module-wide |
|
Assert if DSP XBAR instance number < 1 or > 64
extern const Assert_Id IntXbar_A_badDspXbarInstanceNum;
config IntXbar_A_badEveCpuId // module-wide |
|
Assert if EVE CPU Id invalid
extern const Assert_Id IntXbar_A_badEveCpuId;
config IntXbar_A_badEveIRQNum // module-wide |
|
Assert if EVE IRQ number > 7
extern const Assert_Id IntXbar_A_badEveIRQNum;
config IntXbar_A_badEveXbarInstanceNum // module-wide |
|
Assert if EVE XBAR instance number < 1 or > 8
extern const Assert_Id IntXbar_A_badEveXbarInstanceNum;
config IntXbar_A_badIntSourceIdx // module-wide |
|
Assert if IRQ crossbar input index is out of range
extern const Assert_Id IntXbar_A_badIntSourceIdx;
config IntXbar_mmrBaseAddr // module-wide |
|
Base address of interrupt crossbar MMR registers
extern const UInt32 IntXbar_mmrBaseAddr;
IntXbar_connect() // module-wide |
|
Connect the XBAR instance associated with an interrupt
Void IntXbar_connect(UInt xbarInstance, UInt intSource);
ARGUMENTS
xbarInstance
XBAR instance number
(1-8) For EVE Cores
(1-64) For DSP Cores
(1-57) For M4 Cores
(1-152) For A15 Cores
intSource
IRQ crossbar input index
DETAILS
Dynamically connects the XBAR instance associated with
an interrupt on the current core to the selected
interrupt source.
IntXbar_connectIRQ() // module-wide |
|
Make a XBAR connection for the given IRQ number
Void IntXbar_connectIRQ(UInt cpuIRQNum, UInt intSource);
ARGUMENTS
cpuIRQNum
CPU's IRQ number
intSource
IRQ crossbar input index
DETAILS
Dynamically connects the XBAR instance associated with
the given IRQ number on the current core to the selected
interrupt source.
Please note that IRQ number is same as Event Id on C66 DSP.
IntXbar_disconnect() // module-wide |
|
Disconnect the XBAR instance associated with an interrupt
Void IntXbar_disconnect(UInt xbarInstance);
ARGUMENTS
xbarInstance
XBAR instance number
(1-8) For EVE Cores
(1-64) For DSP Cores
(1-57) For M4 Cores
(1-152) For A15 Cores
DETAILS
Dynamically disconnects the XBAR instance associated with
an interrupt on the current core by clearing the
interrupt source index.
IntXbar_disconnectIRQ() // module-wide |
|
Disconnect the XBAR connection associated with the given IRQ number
Void IntXbar_disconnectIRQ(UInt cpuIRQNum);
ARGUMENTS
cpuIRQNum
CPU's IRQ number
DETAILS
Dynamically disconnects the XBAR instance associated with
the given IRQ number on the current core by clearing the
interrupt source index.
Please note that IRQ number is same as Event Id on C66 DSP.
Module-Wide Built-Ins |
|
// Get this module's unique id
Bool IntXbar_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool IntXbar_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 IntXbar_Module_getMask();
// Returns the diagnostics mask for this module
Void IntXbar_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
const IntXbar.MMR_LOCK2_LOCK |
|
MMR Lock 2 lock value
const IntXbar.MMR_LOCK2_LOCK = 0xFDF45530;
C SYNOPSIS
const IntXbar.MMR_LOCK2_UNLOCK |
|
MMR Lock 2 unlock value
const IntXbar.MMR_LOCK2_UNLOCK = 0xF757FDC0;
C SYNOPSIS
const IntXbar.MMR_OFFSET_A15 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__MPU_IRQ_4_5" register
const IntXbar.MMR_OFFSET_A15 = 0xA48;
C SYNOPSIS
const IntXbar.MMR_OFFSET_BENELLI_IPU1 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__IPU1_IRQ_23_24" register
const IntXbar.MMR_OFFSET_BENELLI_IPU1 = 0x7E0;
C SYNOPSIS
const IntXbar.MMR_OFFSET_BENELLI_IPU2 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__IPU2_IRQ_23_24" register
const IntXbar.MMR_OFFSET_BENELLI_IPU2 = 0x854;
C SYNOPSIS
const IntXbar.MMR_OFFSET_DSP0 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__DSP1_IRQ_32_33" register
const IntXbar.MMR_OFFSET_DSP0 = 0x948;
C SYNOPSIS
const IntXbar.MMR_OFFSET_DSP1 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__DSP2_IRQ_32_33" register
const IntXbar.MMR_OFFSET_DSP1 = 0x9c8;
C SYNOPSIS
const IntXbar.MMR_OFFSET_EVE0 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__EVE1_IRQ_0_1" register
const IntXbar.MMR_OFFSET_EVE0 = 0x7A0;
C SYNOPSIS
const IntXbar.MMR_OFFSET_EVE1 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__EVE2_IRQ_0_1" register
const IntXbar.MMR_OFFSET_EVE1 = 0x7B0;
C SYNOPSIS
const IntXbar.MMR_OFFSET_EVE2 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__EVE3_IRQ_0_1" register
const IntXbar.MMR_OFFSET_EVE2 = 0x7C0;
C SYNOPSIS
const IntXbar.MMR_OFFSET_EVE3 |
|
Offset of "AVATAR_INTR_DMA_OCPINTF__EVE4_IRQ_0_1" register
const IntXbar.MMR_OFFSET_EVE3 = 0x7D0;
C SYNOPSIS
const IntXbar.MMR_OFFSET_LOCK2 |
|
Offset of MMR Lock 2 register
const IntXbar.MMR_OFFSET_LOCK2 = 0x544;
DETAILS
Register to lock memory region starting at address offset 0x000007A0
and ending at address offset 0x00000D9F
C SYNOPSIS
const IntXbar.NUM_A15_XBAR_INST |
|
Number of XBAR instances per A15 Core
const IntXbar.NUM_A15_XBAR_INST = 152;
C SYNOPSIS
const IntXbar.NUM_BENELLI_XBAR_INST |
|
Number of XBAR instances per Benelli Core
const IntXbar.NUM_BENELLI_XBAR_INST = 57;
C SYNOPSIS
const IntXbar.NUM_DSP_XBAR_INST |
|
Number of XBAR instances per DSP core
const IntXbar.NUM_DSP_XBAR_INST = 64;
C SYNOPSIS
const IntXbar.NUM_EVE_XBAR_INST |
|
Number of XBAR instances per EVE core
const IntXbar.NUM_EVE_XBAR_INST = 8;
C SYNOPSIS
const IntXbar.numIrqXbarInputs |
|
Number of IRQ XBAR inputs
const IntXbar.numIrqXbarInputs = 420;
C SYNOPSIS
config IntXbar.A_badA15IRQNum // module-wide |
|
Assert if A15 IRQ number is < 4 or == 5 or == 6 or == 131 or == 132 or
== 139 or == 140 or > 159
msg: "A_badA15IRQNum: No XBAR instance corresponding to given IRQ num"
};
C SYNOPSIS
config IntXbar.A_badA15XbarInstanceNum // module-wide |
|
Assert if A15 XBAR instance number < 1 or > 152
msg: "A_badA15XbarInstanceNum: xbarInstance must be >= 1 and <= 152"
};
C SYNOPSIS
config IntXbar.A_badBenelliIRQNum // module-wide |
|
Assert if Benelli/IPU IRQ number is < 23 or > 79
msg: "A_badBenelliIRQNum: IRQ number must be >= 23 and <= 79"
};
C SYNOPSIS
config IntXbar.A_badBenelliIpuId // module-wide |
|
Assert if Benelli IPU Id invalid
msg: "A_badBenelliIpuId: Ipu Id must be 1 or 2"
};
C SYNOPSIS
config IntXbar.A_badBenelliXbarInstanceNum // module-wide |
|
Assert if Benelli XBAR instance number < 1 or > 57
msg: "A_badBenelliXbarInstanceNum: xbarInstance must be >= 1 and <= 57"
};
C SYNOPSIS
config IntXbar.A_badDspCpuId // module-wide |
|
Assert if DSP CPU Id invalid
msg: "A_badDspCpuId: CPU Id must be 0 or 1"
};
C SYNOPSIS
config IntXbar.A_badDspIRQNum // module-wide |
|
Assert if DSP IRQ number is < 32 or > 95
msg: "A_badDspIRQNum: IRQ number must be >= 32 and <= 95"
};
C SYNOPSIS
config IntXbar.A_badDspXbarInstanceNum // module-wide |
|
Assert if DSP XBAR instance number < 1 or > 64
msg: "A_badDspXbarInstanceNum: xbarInstance must be >= 1 and <= 64"
};
C SYNOPSIS
config IntXbar.A_badEveCpuId // module-wide |
|
Assert if EVE CPU Id invalid
msg: "A_badEveCpuId: CPU Id must be 0, 1, 2 or 3"
};
C SYNOPSIS
config IntXbar.A_badEveIRQNum // module-wide |
|
Assert if EVE IRQ number > 7
msg: "A_badEveIRQNum: IRQ number must be <= 7"
};
C SYNOPSIS
config IntXbar.A_badEveXbarInstanceNum // module-wide |
|
Assert if EVE XBAR instance number < 1 or > 8
msg: "A_badEveXbarInstanceNum: xbarInstance must be >= 1 and <= 8"
};
C SYNOPSIS
config IntXbar.A_badIntSourceIdx // module-wide |
|
Assert if IRQ crossbar input index is out of range
msg: "A_badIntSourceIdx: IRQ crossbar input index (intSource) out of range."
};
C SYNOPSIS
config IntXbar.mmrBaseAddr // module-wide |
|
Base address of interrupt crossbar MMR registers
IntXbar.mmrBaseAddr = UInt32 0x4A002000;
C SYNOPSIS
metaonly config IntXbar.common$ // module-wide |
|
Common module configuration parameters
DETAILS
All modules have this configuration parameter. Its name
contains the '$' character to ensure it does not conflict with
configuration parameters declared by the module. This allows
new configuration parameters to be added in the future without
any chance of breaking existing modules.
metaonly IntXbar.connectIRQMeta() // module-wide |
|
Make a XBAR connection for the given IRQ number
IntXbar.connectIRQMeta(UInt cpuIRQNum, UInt intSource) returns Void
ARGUMENTS
cpuIRQNum
CPU's IRQ number
intSource
IRQ crossbar input index
DETAILS
Dynamically connects the XBAR instance associated with
the given IRQ number on the current core to the selected
interrupt source.
Please note that IRQ number is same as Event Id on C66 DSP.
metaonly IntXbar.connectMeta() // module-wide |
|
Connect the XBAR instance associated with an interrupt
IntXbar.connectMeta(UInt xbarInstance, UInt intSource) returns Void
ARGUMENTS
xbarInstance
XBAR instance number
(1-8) For EVE Cores
(1-64) For DSP Cores
(1-57) For M4 Cores
(1-152) For A15 Cores
intSource
IRQ crossbar input index
DETAILS
Dynamically connects the XBAR instance associated with
an interrupt on the current core to the selected
interrupt source.