module ti.sysbios.family.shared.vayu.IntXbar

IntXbar module

This module provides APIs to connect an IRQ source to an IRQ line on the target cpu's interrupt controller using the Interrupt Crossbar module in the hardware. [ more ... ]
C synopsis target-domain sourced in ti/sysbios/family/shared/vayu/IntXbar.xdc
#include <ti/sysbios/family/shared/vayu/IntXbar.h>
Functions
Void 
Void 
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Void 
Functions common to all target modules
Defines
#define
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Constants
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const Assert_Id 
extern const UInt32 
 
DETAILS
This module provides APIs to connect an IRQ source to an IRQ line on the target cpu's interrupt controller using the Interrupt Crossbar module in the hardware.
Below is an example of how to override the default mapping of interrupt 23 on a M4 so that the interrupt source is I2C module 1 rather than Display Controller interrupt request(mapped by default):
  #include <ti/sysbios/family/arm/m3/Hwi.h>
  #include <ti/sysbios/family/shared/vayu/IntXbar.h>

  Void myI2CHandler(UArg arg)
  {
      // Handler Code
  }

  Int main(Int argc, Char* argv[])
  {
      Hwi_Params params;

      Hwi_Params_init(&params);

      // Connect IRQ 23 to Interrupt source index 51 (I2C1_IRQ)
      IntXbar_connectIRQ(23, 51);

      // Alternately, IntXbar_connect API can be used. This
      // API expects XBAR instance number as an argument.
      //
      // Connect Xbar Instance 1 (IRQ 23) to Interrupt
      // source index 51 (I2C1_IRQ)
      //
      // IntXbar_connect(1, 51);

      // create a corresponding interrupt handler
      params.arg = 23; // pass the Interrupt number to the handler

      Hwi_create(23, myI2CHandler, &params, NULL);

      BIOS_start();

      return (0);
  }
Here is how you would define the same interrupt handler statically in a configuration script:
  var Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
  var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');

  // Connect IRQ 23 to Interrupt source index 51 (I2C1_IRQ)
  IntXbar.connectIRQMeta(23, 51);

  // Alternately, the connectIRQMeta API can be used. This
  // API expects XBAR instance number as an argument.
  //
  // Connect Xbar Instance 1 (IRQ 23) to Interrupt
  // source index 51 (I2C1_IRQ)
  //
  // IntXbar.connectMeta(1, 51);

  var hwiParams = new Hwi.Params();
  hwiParams.arg = 23;

  Program.global.staticHwi = Hwi.create(23, '&myTimerHandler', hwiParams);

Calling Context

Function Hwi Swi Task Main Startup
connect Y Y Y Y Y
disconnect Y Y Y Y Y
Definitions:
  • Hwi: API is callable from a Hwi thread.
  • Swi: API is callable from a Swi thread.
  • Task: API is callable from a Task thread.
  • Main: API is callable during any of these phases:
    • In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE).
    • During xdc.runtime.Startup.lastFxns.
    • During main().
    • During BIOS.startupFxns.
  • Startup: API is callable during any of these phases:
    • During xdc.runtime.Startup.firstFxns.
    • In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).
 
const IntXbar_MMR_LOCK2_LOCK

MMR Lock 2 lock value

C synopsis target-domain
#define IntXbar_MMR_LOCK2_LOCK (UInt32)0xFDF45530
 
 
const IntXbar_MMR_LOCK2_UNLOCK

MMR Lock 2 unlock value

C synopsis target-domain
#define IntXbar_MMR_LOCK2_UNLOCK (UInt32)0xF757FDC0
 
 
const IntXbar_MMR_OFFSET_A15

Offset of "AVATAR_INTR_DMA_OCPINTF__MPU_IRQ_4_5" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_A15 (UInt32)0xA48
 
 
const IntXbar_MMR_OFFSET_BENELLI_IPU1

Offset of "AVATAR_INTR_DMA_OCPINTF__IPU1_IRQ_23_24" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_BENELLI_IPU1 (UInt32)0x7E0
 
 
const IntXbar_MMR_OFFSET_BENELLI_IPU2

Offset of "AVATAR_INTR_DMA_OCPINTF__IPU2_IRQ_23_24" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_BENELLI_IPU2 (UInt32)0x854
 
 
const IntXbar_MMR_OFFSET_DSP0

Offset of "AVATAR_INTR_DMA_OCPINTF__DSP1_IRQ_32_33" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_DSP0 (UInt32)0x948
 
 
const IntXbar_MMR_OFFSET_DSP1

Offset of "AVATAR_INTR_DMA_OCPINTF__DSP2_IRQ_32_33" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_DSP1 (UInt32)0x9c8
 
 
const IntXbar_MMR_OFFSET_EVE0

Offset of "AVATAR_INTR_DMA_OCPINTF__EVE1_IRQ_0_1" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_EVE0 (UInt32)0x7A0
 
 
const IntXbar_MMR_OFFSET_EVE1

Offset of "AVATAR_INTR_DMA_OCPINTF__EVE2_IRQ_0_1" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_EVE1 (UInt32)0x7B0
 
 
const IntXbar_MMR_OFFSET_EVE2

Offset of "AVATAR_INTR_DMA_OCPINTF__EVE3_IRQ_0_1" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_EVE2 (UInt32)0x7C0
 
 
const IntXbar_MMR_OFFSET_EVE3

Offset of "AVATAR_INTR_DMA_OCPINTF__EVE4_IRQ_0_1" register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_EVE3 (UInt32)0x7D0
 
 
const IntXbar_MMR_OFFSET_LOCK2

Offset of MMR Lock 2 register

C synopsis target-domain
#define IntXbar_MMR_OFFSET_LOCK2 (UInt32)0x544
 
DETAILS
Register to lock memory region starting at address offset 0x000007A0 and ending at address offset 0x00000D9F
 
const IntXbar_NUM_A15_XBAR_INST

Number of XBAR instances per A15 Core

C synopsis target-domain
#define IntXbar_NUM_A15_XBAR_INST (UInt16)152
 
 
const IntXbar_NUM_BENELLI_XBAR_INST

Number of XBAR instances per Benelli Core

C synopsis target-domain
#define IntXbar_NUM_BENELLI_XBAR_INST (UInt16)57
 
 
const IntXbar_NUM_DSP_XBAR_INST

Number of XBAR instances per DSP core

C synopsis target-domain
#define IntXbar_NUM_DSP_XBAR_INST (UInt16)64
 
 
const IntXbar_NUM_EVE_XBAR_INST

Number of XBAR instances per EVE core

C synopsis target-domain
#define IntXbar_NUM_EVE_XBAR_INST (UInt16)8
 
 
const IntXbar_numIrqXbarInputs

Number of IRQ XBAR inputs

C synopsis target-domain
#define IntXbar_numIrqXbarInputs (UInt16)420
 
 
config IntXbar_A_badA15IRQNum  // module-wide

Assert if A15 IRQ number is < 4 or == 5 or == 6 or == 131 or == 132 or == 139 or == 140 or > 159

C synopsis target-domain
extern const Assert_Id IntXbar_A_badA15IRQNum;
 
 
config IntXbar_A_badA15XbarInstanceNum  // module-wide

Assert if A15 XBAR instance number < 1 or > 152

C synopsis target-domain
extern const Assert_Id IntXbar_A_badA15XbarInstanceNum;
 
 
config IntXbar_A_badBenelliIRQNum  // module-wide

Assert if Benelli/IPU IRQ number is < 23 or > 79

C synopsis target-domain
extern const Assert_Id IntXbar_A_badBenelliIRQNum;
 
 
config IntXbar_A_badBenelliIpuId  // module-wide

Assert if Benelli IPU Id invalid

C synopsis target-domain
extern const Assert_Id IntXbar_A_badBenelliIpuId;
 
 
config IntXbar_A_badBenelliXbarInstanceNum  // module-wide

Assert if Benelli XBAR instance number < 1 or > 57

C synopsis target-domain
extern const Assert_Id IntXbar_A_badBenelliXbarInstanceNum;
 
 
config IntXbar_A_badDspCpuId  // module-wide

Assert if DSP CPU Id invalid

C synopsis target-domain
extern const Assert_Id IntXbar_A_badDspCpuId;
 
 
config IntXbar_A_badDspIRQNum  // module-wide

Assert if DSP IRQ number is < 32 or > 95

C synopsis target-domain
extern const Assert_Id IntXbar_A_badDspIRQNum;
 
 
config IntXbar_A_badDspXbarInstanceNum  // module-wide

Assert if DSP XBAR instance number < 1 or > 64

C synopsis target-domain
extern const Assert_Id IntXbar_A_badDspXbarInstanceNum;
 
 
config IntXbar_A_badEveCpuId  // module-wide

Assert if EVE CPU Id invalid

C synopsis target-domain
extern const Assert_Id IntXbar_A_badEveCpuId;
 
 
config IntXbar_A_badEveIRQNum  // module-wide

Assert if EVE IRQ number > 7

C synopsis target-domain
extern const Assert_Id IntXbar_A_badEveIRQNum;
 
 
config IntXbar_A_badEveXbarInstanceNum  // module-wide

Assert if EVE XBAR instance number < 1 or > 8

C synopsis target-domain
extern const Assert_Id IntXbar_A_badEveXbarInstanceNum;
 
 
config IntXbar_A_badIntSourceIdx  // module-wide

Assert if IRQ crossbar input index is out of range

C synopsis target-domain
extern const Assert_Id IntXbar_A_badIntSourceIdx;
 
 
config IntXbar_mmrBaseAddr  // module-wide

Base address of interrupt crossbar MMR registers

C synopsis target-domain
extern const UInt32 IntXbar_mmrBaseAddr;
 
 
IntXbar_connect()  // module-wide

Connect the XBAR instance associated with an interrupt

C synopsis target-domain
Void IntXbar_connect(UInt xbarInstance, UInt intSource);
 
ARGUMENTS
xbarInstance — XBAR instance number
              (1-8)   For EVE Cores
              (1-64)  For DSP Cores
              (1-57)  For M4 Cores
              (1-152) For A15 Cores
intSource — IRQ crossbar input index
DETAILS
Dynamically connects the XBAR instance associated with an interrupt on the current core to the selected interrupt source.
 
IntXbar_connectIRQ()  // module-wide

Make a XBAR connection for the given IRQ number

C synopsis target-domain
Void IntXbar_connectIRQ(UInt cpuIRQNum, UInt intSource);
 
ARGUMENTS
cpuIRQNum — CPU's IRQ number
intSource — IRQ crossbar input index
DETAILS
Dynamically connects the XBAR instance associated with the given IRQ number on the current core to the selected interrupt source.
Please note that IRQ number is same as Event Id on C66 DSP.
 
IntXbar_disconnect()  // module-wide

Disconnect the XBAR instance associated with an interrupt

C synopsis target-domain
Void IntXbar_disconnect(UInt xbarInstance);
 
ARGUMENTS
xbarInstance — XBAR instance number
              (1-8)   For EVE Cores
              (1-64)  For DSP Cores
              (1-57)  For M4 Cores
              (1-152) For A15 Cores
DETAILS
Dynamically disconnects the XBAR instance associated with an interrupt on the current core by clearing the interrupt source index.
 
IntXbar_disconnectIRQ()  // module-wide

Disconnect the XBAR connection associated with the given IRQ number

C synopsis target-domain
Void IntXbar_disconnectIRQ(UInt cpuIRQNum);
 
ARGUMENTS
cpuIRQNum — CPU's IRQ number
DETAILS
Dynamically disconnects the XBAR instance associated with the given IRQ number on the current core by clearing the interrupt source index.
Please note that IRQ number is same as Event Id on C66 DSP.
Module-Wide Built-Ins

C synopsis target-domain
Types_ModuleId IntXbar_Module_id();
// Get this module's unique id
 
Bool IntXbar_Module_startupDone();
// Test if this module has completed startup
 
IHeap_Handle IntXbar_Module_heap();
// The heap from which this module allocates memory
 
Bool IntXbar_Module_hasMask();
// Test whether this module has a diagnostics mask
 
Bits16 IntXbar_Module_getMask();
// Returns the diagnostics mask for this module
 
Void IntXbar_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module
 
Configuration settings sourced in ti/sysbios/family/shared/vayu/IntXbar.xdc
var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
module-wide constants & types
module-wide config parameters
        msg: "A_badA15IRQNum: No XBAR instance corresponding to given IRQ num"
    };
        msg: "A_badA15XbarInstanceNum: xbarInstance must be >= 1 and <= 152"
    };
        msg: "A_badBenelliIRQNum: IRQ number must be >= 23 and <= 79"
    };
        msg: "A_badBenelliIpuId: Ipu Id must be 1 or 2"
    };
        msg: "A_badBenelliXbarInstanceNum: xbarInstance must be >= 1 and <= 57"
    };
        msg: "A_badDspCpuId: CPU Id must be 0 or 1"
    };
        msg: "A_badDspIRQNum: IRQ number must be >= 32 and <= 95"
    };
        msg: "A_badDspXbarInstanceNum: xbarInstance must be >= 1 and <= 64"
    };
        msg: "A_badEveCpuId: CPU Id must be 0, 1, 2 or 3"
    };
        msg: "A_badEveIRQNum: IRQ number must be <= 7"
    };
        msg: "A_badEveXbarInstanceNum: xbarInstance must be >= 1 and <= 8"
    };
        msg: "A_badIntSourceIdx: IRQ crossbar input index (intSource) out of range."
    };
 
module-wide functions
    IntXbar.connectIRQMeta// Make a XBAR connection for the given IRQ number(UInt cpuIRQNum, UInt intSource) returns Void
    IntXbar.connectMeta// Connect the XBAR instance associated with an interrupt(UInt xbarInstance, UInt intSource) returns Void
 
 
const IntXbar.MMR_LOCK2_LOCK

MMR Lock 2 lock value

Configuration settings
const IntXbar.MMR_LOCK2_LOCK = 0xFDF45530;
 
C SYNOPSIS
 
const IntXbar.MMR_LOCK2_UNLOCK

MMR Lock 2 unlock value

Configuration settings
const IntXbar.MMR_LOCK2_UNLOCK = 0xF757FDC0;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_A15

Offset of "AVATAR_INTR_DMA_OCPINTF__MPU_IRQ_4_5" register

Configuration settings
const IntXbar.MMR_OFFSET_A15 = 0xA48;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_BENELLI_IPU1

Offset of "AVATAR_INTR_DMA_OCPINTF__IPU1_IRQ_23_24" register

Configuration settings
const IntXbar.MMR_OFFSET_BENELLI_IPU1 = 0x7E0;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_BENELLI_IPU2

Offset of "AVATAR_INTR_DMA_OCPINTF__IPU2_IRQ_23_24" register

Configuration settings
const IntXbar.MMR_OFFSET_BENELLI_IPU2 = 0x854;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_DSP0

Offset of "AVATAR_INTR_DMA_OCPINTF__DSP1_IRQ_32_33" register

Configuration settings
const IntXbar.MMR_OFFSET_DSP0 = 0x948;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_DSP1

Offset of "AVATAR_INTR_DMA_OCPINTF__DSP2_IRQ_32_33" register

Configuration settings
const IntXbar.MMR_OFFSET_DSP1 = 0x9c8;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_EVE0

Offset of "AVATAR_INTR_DMA_OCPINTF__EVE1_IRQ_0_1" register

Configuration settings
const IntXbar.MMR_OFFSET_EVE0 = 0x7A0;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_EVE1

Offset of "AVATAR_INTR_DMA_OCPINTF__EVE2_IRQ_0_1" register

Configuration settings
const IntXbar.MMR_OFFSET_EVE1 = 0x7B0;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_EVE2

Offset of "AVATAR_INTR_DMA_OCPINTF__EVE3_IRQ_0_1" register

Configuration settings
const IntXbar.MMR_OFFSET_EVE2 = 0x7C0;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_EVE3

Offset of "AVATAR_INTR_DMA_OCPINTF__EVE4_IRQ_0_1" register

Configuration settings
const IntXbar.MMR_OFFSET_EVE3 = 0x7D0;
 
C SYNOPSIS
 
const IntXbar.MMR_OFFSET_LOCK2

Offset of MMR Lock 2 register

Configuration settings
const IntXbar.MMR_OFFSET_LOCK2 = 0x544;
 
DETAILS
Register to lock memory region starting at address offset 0x000007A0 and ending at address offset 0x00000D9F
C SYNOPSIS
 
const IntXbar.NUM_A15_XBAR_INST

Number of XBAR instances per A15 Core

Configuration settings
const IntXbar.NUM_A15_XBAR_INST = 152;
 
C SYNOPSIS
 
const IntXbar.NUM_BENELLI_XBAR_INST

Number of XBAR instances per Benelli Core

Configuration settings
const IntXbar.NUM_BENELLI_XBAR_INST = 57;
 
C SYNOPSIS
 
const IntXbar.NUM_DSP_XBAR_INST

Number of XBAR instances per DSP core

Configuration settings
const IntXbar.NUM_DSP_XBAR_INST = 64;
 
C SYNOPSIS
 
const IntXbar.NUM_EVE_XBAR_INST

Number of XBAR instances per EVE core

Configuration settings
const IntXbar.NUM_EVE_XBAR_INST = 8;
 
C SYNOPSIS
 
const IntXbar.numIrqXbarInputs

Number of IRQ XBAR inputs

Configuration settings
const IntXbar.numIrqXbarInputs = 420;
 
C SYNOPSIS
 
config IntXbar.A_badA15IRQNum  // module-wide

Assert if A15 IRQ number is < 4 or == 5 or == 6 or == 131 or == 132 or == 139 or == 140 or > 159

Configuration settings
IntXbar.A_badA15IRQNum = Assert.Desc {
    msg: "A_badA15IRQNum: No XBAR instance corresponding to given IRQ num"
};
 
C SYNOPSIS
 
config IntXbar.A_badA15XbarInstanceNum  // module-wide

Assert if A15 XBAR instance number < 1 or > 152

Configuration settings
IntXbar.A_badA15XbarInstanceNum = Assert.Desc {
    msg: "A_badA15XbarInstanceNum: xbarInstance must be >= 1 and <= 152"
};
 
C SYNOPSIS
 
config IntXbar.A_badBenelliIRQNum  // module-wide

Assert if Benelli/IPU IRQ number is < 23 or > 79

Configuration settings
IntXbar.A_badBenelliIRQNum = Assert.Desc {
    msg: "A_badBenelliIRQNum: IRQ number must be >= 23 and <= 79"
};
 
C SYNOPSIS
 
config IntXbar.A_badBenelliIpuId  // module-wide

Assert if Benelli IPU Id invalid

Configuration settings
IntXbar.A_badBenelliIpuId = Assert.Desc {
    msg: "A_badBenelliIpuId: Ipu Id must be 1 or 2"
};
 
C SYNOPSIS
 
config IntXbar.A_badBenelliXbarInstanceNum  // module-wide

Assert if Benelli XBAR instance number < 1 or > 57

Configuration settings
IntXbar.A_badBenelliXbarInstanceNum = Assert.Desc {
    msg: "A_badBenelliXbarInstanceNum: xbarInstance must be >= 1 and <= 57"
};
 
C SYNOPSIS
 
config IntXbar.A_badDspCpuId  // module-wide

Assert if DSP CPU Id invalid

Configuration settings
IntXbar.A_badDspCpuId = Assert.Desc {
    msg: "A_badDspCpuId: CPU Id must be 0 or 1"
};
 
C SYNOPSIS
 
config IntXbar.A_badDspIRQNum  // module-wide

Assert if DSP IRQ number is < 32 or > 95

Configuration settings
IntXbar.A_badDspIRQNum = Assert.Desc {
    msg: "A_badDspIRQNum: IRQ number must be >= 32 and <= 95"
};
 
C SYNOPSIS
 
config IntXbar.A_badDspXbarInstanceNum  // module-wide

Assert if DSP XBAR instance number < 1 or > 64

Configuration settings
IntXbar.A_badDspXbarInstanceNum = Assert.Desc {
    msg: "A_badDspXbarInstanceNum: xbarInstance must be >= 1 and <= 64"
};
 
C SYNOPSIS
 
config IntXbar.A_badEveCpuId  // module-wide

Assert if EVE CPU Id invalid

Configuration settings
IntXbar.A_badEveCpuId = Assert.Desc {
    msg: "A_badEveCpuId: CPU Id must be 0, 1, 2 or 3"
};
 
C SYNOPSIS
 
config IntXbar.A_badEveIRQNum  // module-wide

Assert if EVE IRQ number > 7

Configuration settings
IntXbar.A_badEveIRQNum = Assert.Desc {
    msg: "A_badEveIRQNum: IRQ number must be <= 7"
};
 
C SYNOPSIS
 
config IntXbar.A_badEveXbarInstanceNum  // module-wide

Assert if EVE XBAR instance number < 1 or > 8

Configuration settings
IntXbar.A_badEveXbarInstanceNum = Assert.Desc {
    msg: "A_badEveXbarInstanceNum: xbarInstance must be >= 1 and <= 8"
};
 
C SYNOPSIS
 
config IntXbar.A_badIntSourceIdx  // module-wide

Assert if IRQ crossbar input index is out of range

Configuration settings
IntXbar.A_badIntSourceIdx = Assert.Desc {
    msg: "A_badIntSourceIdx: IRQ crossbar input index (intSource) out of range."
};
 
C SYNOPSIS
 
config IntXbar.mmrBaseAddr  // module-wide

Base address of interrupt crossbar MMR registers

Configuration settings
IntXbar.mmrBaseAddr = UInt32 0x4A002000;
 
C SYNOPSIS
 
metaonly config IntXbar.common$  // module-wide

Common module configuration parameters

Configuration settings
IntXbar.common$ = Types.Common$ undefined;
 
DETAILS
All modules have this configuration parameter. Its name contains the '$' character to ensure it does not conflict with configuration parameters declared by the module. This allows new configuration parameters to be added in the future without any chance of breaking existing modules.
 
metaonly IntXbar.connectIRQMeta()  // module-wide

Make a XBAR connection for the given IRQ number

Configuration settings
IntXbar.connectIRQMeta(UInt cpuIRQNum, UInt intSource) returns Void
 
ARGUMENTS
cpuIRQNum — CPU's IRQ number
intSource — IRQ crossbar input index
DETAILS
Dynamically connects the XBAR instance associated with the given IRQ number on the current core to the selected interrupt source.
Please note that IRQ number is same as Event Id on C66 DSP.
 
metaonly IntXbar.connectMeta()  // module-wide

Connect the XBAR instance associated with an interrupt

Configuration settings
IntXbar.connectMeta(UInt xbarInstance, UInt intSource) returns Void
 
ARGUMENTS
xbarInstance — XBAR instance number
              (1-8)   For EVE Cores
              (1-64)  For DSP Cores
              (1-57)  For M4 Cores
              (1-152) For A15 Cores
intSource — IRQ crossbar input index
DETAILS
Dynamically connects the XBAR instance associated with an interrupt on the current core to the selected interrupt source.
generated on Thu, 23 May 2019 00:22:28 GMT