1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32 33 34
35
36 package ti.sysbios.family.c66;
37
38 import xdc.rov.ViewInfo;
39
40 import xdc.runtime.Error;
41
42 /*!
43 * ======== Cache ========
44 * Cache Module
45 *
46 * This Cache module provides C66 family-specific implementations of the
47 * APIs defined in {@link ti.sysbios.interfaces.ICache ICache}. It also
48 * provides additional C66 specific cache functions.
49 *
50 * Unconstrained Functions
51 * All functions
52 *
53 * @p(html)
54 * <h3> Calling Context </h3>
55 * <table border="1" cellpadding="3">
56 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
57 *
58 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
59 * <!-- -->
60 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
61 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
62 * <tr><td> {@link #getMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
63 * <tr><td> {@link #getMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
64 * <tr><td> {@link #getSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
65 * <tr><td> {@link #inv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
66 * <tr><td> {@link #invL1pAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
67 * <tr><td> {@link #setMar*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
68 * <tr><td> {@link #setMode*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
69 * <tr><td> {@link #setSize*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
70 * <tr><td> {@link #wait} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
71 * <tr><td> {@link #wb} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
72 * <tr><td> {@link #wbAll*} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
73 * <tr><td> {@link #wbL1dAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
74 * <tr><td> {@link #wbInv} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
75 * <tr><td> {@link #wbInvAll} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
76 * <tr><td> {@link #wbInvL1dAll}</td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
77 * <tr><td colspan="6"> Definitions: <br />
78 * <ul>
79 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
80 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
81 * <li> <b>Task</b>: API is callable from a Task thread. </li>
82 * <li> <b>Main</b>: API is callable during any of these phases: </li>
83 * <ul>
84 * <li> In your module startup after this module is started (e.g. Mod_Module_startupDone() returns TRUE). </li>
85 * <li> During xdc.runtime.Startup.lastFxns. </li>
86 * <li> During main().</li>
87 * <li> During BIOS.startupFxns.</li>
88 * </ul>
89 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
90 * <ul>
91 * <li> During xdc.runtime.Startup.firstFxns.</li>
92 * <li> In your module startup before this module is started (e.g. Mod_Module_startupDone() returns FALSE).</li>
93 * </ul>
94 * <li> <b>*</b>: These APIs are intended to be made at initialization time, but are not restricted to this. </li>
95 * </ul>
96 * </td></tr>
97 *
98 * </table>
99 * @p
100 */
101
102
103 @ModuleStartup
104
105 module Cache inherits ti.sysbios.interfaces.ICache
106 {
107
108
109 /*!
110 * ======== ModuleView ========
111 * @_nodoc
112 */
113 metaonly struct ModuleView {
114 String L1PCacheSize;
115 String L1PMode;
116 String L1DCacheSize;
117 String L1DMode;
118 String L2CacheSize;
119 String L2Mode;
120 };
121
122 /*!
123 * ======== MarRegisterView ========
124 * @_nodoc
125 */
126 metaonly struct MarRegisterView {
127 UInt number;
128 Ptr addr;
129 Ptr startAddrRange;
130 Ptr endAddrRange;
131 Bool cacheable;
132 Bool prefetchable;
133 String marRegisterValue;
134 };
135
136 /*!
137 * ======== rovViewInfo ========
138 * @_nodoc
139 */
140 @Facet
141 metaonly config ViewInfo.Instance rovViewInfo =
142 ViewInfo.create({
143 viewMap: [
144 ['Module',
145 {
146 type: ViewInfo.MODULE,
147 viewInitFxn: 'viewInitModule',
148 structName: 'ModuleView'
149 }
150 ],
151 ['MARs',
152 {
153 type: xdc.rov.ViewInfo.MODULE_DATA,
154 viewInitFxn: 'viewInitMarRegisters',
155 structName: 'MarRegisterView'
156 }
157 ]
158 ]
159 });
160
161 /*! Lists of cache modes for L1/L2 caches */
162 enum Mode {
163 Mode_FREEZE, /*! No new cache lines are allocated */
164 Mode_BYPASS, /*! All access result in long-distance access */
165 Mode_NORMAL /*! Normal operation of cache */
166 };
167
168 /*! Level 1 cache size type definition. Can be used for both L1D & L1P */
169 enum L1Size {
170 L1Size_0K = 0, /*! Amount of cache is 0K, Amount of SRAM is 32K */
171 L1Size_4K = 1, /*! Amount of cache is 4K, Amount of SRAM is 28K */
172 L1Size_8K = 2, /*! Amount of cache is 8K, Amount of SRAM is 24K */
173 L1Size_16K = 3, /*! Amount of cache is 16K, Amount of SRAM is 16K */
174 L1Size_32K = 4 /*! Amount of cache is 32K, Amount of SRAM is 0K */
175 };
176
177 /*! Level 2 cache size type definition. */
178 enum L2Size {
179 L2Size_0K = 0, /*! L2 is all SRAM */
180 L2Size_32K = 1, /*! Amount of cache is 32K */
181 L2Size_64K = 2, /*! Amount of cache is 64K */
182 L2Size_128K = 3, /*! Amount of cache is 128K */
183 L2Size_256K = 4, /*! Amount of cache is 256K */
184 L2Size_512K = 5, /*! Amount of cache is 512K */
185 L2Size_1024K = 6 /*! Amount of cache is 1024K */
186 };
187
188 /*! MAR register setting type definition. */
189 enum Mar {
190 Mar_DISABLE = 0, /*! The Permit Copy bit of MAR register is disabled */
191 Mar_ENABLE = 1 /*! The Permit Copy bit of MAR register is enabled */
192 };
193
194 const UInt32 PC = 1; /*! Permit Caching */
195 const UInt32 WTE = 2; /*! Write through enabled */
196 const UInt32 PCX = 4; /*! Permit caching in external cache */
197 const UInt32 PFX = 8; /*! Prefetchable by external engines */
198
199 /*! Structure for specifying all cache sizes. */
200 struct Size {
201 L1Size l1pSize; /*! L1 Program cache size */
202 L1Size l1dSize; /*! L1 Data data size */
203 L2Size l2Size; /*! L2 cache size */
204 };
205
206 /*! Default sizes of caches.
207 * @_nodoc
208 */
209 config Size initSize = {
210 l1pSize: L1Size_32K,
211 l1dSize: L1Size_32K,
212 l2Size: L2Size_0K
213 };
214
215 /*! @_nodoc
216 * MAR 00 - 31 register bitmask. (for addresses 0x00000000 - 0x1FFFFFFF)
217 *
218 * If undefined by the user, this parameter is configured to match the
219 * memory map of the platform.
220 * Each memory region defined in the platform will have all of its
221 * corresponding MAR bits set.
222 *
223 * To override the default behavior you must initialize this parameter
224 * in your configuration script:
225 *
226 * @p(code)
227 * // disable MAR bits for addresses 0x00000000 to 0x1FFFFFFF
228 * Cache.MAR0_31 = 0x00000000;
229 * @p
230 */
231 metaonly config UInt32 MAR0_31;
232
233 /*! @_nodoc
234 * MAR 32 - 63 register bitmask (for addresses 0x20000000 - 0x3FFFFFFF)
235 *
236 * see {@link #MAR0_31} for more info
237 */
238 metaonly config UInt32 MAR32_63;
239
240 /*! @_nodoc
241 * MAR 64 - 95 register bitmask (for addresses 0x40000000 - 0x5FFFFFFF)
242 *
243 * see {@link #MAR0_31} for more info
244 */
245 metaonly config UInt32 MAR64_95;
246
247 /*! @_nodoc
248 * MAR 96 - 127 register bitmask (for addresses 0x60000000 - 0x7FFFFFFF)
249 *
250 * see {@link #MAR0_31} for more info
251 */
252 metaonly config UInt32 MAR96_127;
253
254 /*! @_nodoc
255 * MAR 128 - 159 register bitmask (for addresses 0x80000000 - 0x9FFFFFFF)
256 *
257 * see {@link #MAR0_31} for more info
258 */
259 metaonly config UInt32 MAR128_159;
260
261 /*! @_nodoc
262 * MAR 160 - 191 register bitmask (for addresses 0xA0000000 - 0xBFFFFFFF)
263 *
264 * see {@link #MAR0_31} for more info
265 */
266 metaonly config UInt32 MAR160_191;
267
268 /*! @_nodoc
269 * MAR 192 - 223 register bitmask (for addresses 0xC0000000 - 0xDFFFFFFF)
270 *
271 * see {@link #MAR0_31} for more info
272 */
273 metaonly config UInt32 MAR192_223;
274
275 /*! @_nodoc
276 * MAR 224 - 255 register bitmask (for addresses 0xE0000000 - 0xFFFFFFFF)
277 *
278 * see {@link #MAR0_31} for more info
279 */
280 metaonly config UInt32 MAR224_255;
281
282 /*!
283 * Error raised when invalid L1 cache size defined
284 */
285 config Error.Id E_invalidL1CacheSize = {
286 msg: "E_invalidL1CacheSize: Invalid L1 cache size %d"
287 };
288
289 /*!
290 * Error raised when invalid L2 cache size defined
291 */
292 config Error.Id E_invalidL2CacheSize = {
293 msg: "E_invalidL2CacheSize: Invalid L2 cache size %d"
294 };
295
296 /*! @_nodoc
297 *
298 * This parameter is used to break up large blocks into multiple
299 * small blocks which are done atomically. Each block of the
300 * specified size waits for the cache operation to finish before
301 * starting the next block. Setting this size to 0, means the
302 * cache operations are not done atomically.
303 */
304 config UInt32 atomicBlockSize = 1024;
305
306 /*!
307 * ======== registerRTSSynch ========
308 * Boolean flag controlling registration of data synchronization
309 * functions that are called by the RTS when accessing shared RTS
310 * data objects. The compiler option "--multithread" needs to be
311 * applied in order for this feature to be functional (otherwise,
312 * empty stubs are used in RTS).
313 */
314 config Bool registerRTSSynch = false;
315
316 /*!
317 * ======== getMarMeta ========
318 * Gets the current MAR value for the specified base address
319 *
320 * @param(baseAddr) address for which MAR value is requested
321 *
322 * @b(returns) MAR value for specified address
323 */
324 metaonly UInt32 getMarMeta(Ptr baseAddr);
325
326 /*!
327 * ======== setMarMeta ========
328 * Set MAR register(s) that corresponds to the specified address range.
329 *
330 * The 'pc' ("Permit Caching") field is enabled for all memory regions
331 * in the device platform. Only set the fields of the Mar structure
332 * which need to be modified. Any field not set retains its reset value.
333 *
334 * All MAR registers that corresponds within the specified base address
335 * and base address + size are set to the specified value.
336 *
337 * @a(Note)
338 * The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on
339 * C66x CorePac devices.
340 *
341 * @param(baseAddr) start address for which to set MAR
342 * @param(byteSize) size (in bytes) of memory block
343 * @param(value) value for setting MAR register
344 */
345 metaonly Void setMarMeta(Ptr baseAddr, SizeT byteSize, UInt32 value);
346
347 /*!
348 * ======== disable ========
349 * Disables the 'type' cache(s)
350 *
351 * Disabling of L2 cache is currently not supported.
352 */
353 override Void disable(Bits16 type);
354
355 /*!
356 * ======== getMode ========
357 * Get mode of a cache
358 *
359 * @param(type) bit mask of cache type
360 * @b(returns) mode of specified level of cache
361 */
362 Mode getMode(Bits16 type);
363
364 /*!
365 * ======== setMode ========
366 * Set mode of a cache
367 *
368 * @param(type) bit mask of cache type
369 * @param(mode) mode of cache
370 *
371 * @b(returns) previous mode of cache
372 */
373 Mode setMode(Bits16 type, Mode mode);
374
375 /*!
376 * ======== getSize ========
377 * Get sizes of all caches
378 *
379 * @param(size) pointer to structure of type Cache_Size
380 */
381 Void getSize(Size *size);
382
383 /*!
384 * ======== setSize ========
385 * Set sizes of all caches
386 *
387 * @param(size) pointer to structure of type Cache_Size
388 */
389 Void setSize(Size *size);
390
391 /*!
392 * ======== getMar ========
393 * Gets the MAR register for the specified base address
394 *
395 * @param(baseAddr) address for which MAR is requested
396 *
397 * @b(returns) value of MAR register
398 */
399 UInt32 getMar(Ptr baseAddr);
400
401 /*!
402 * ======== setMar ========
403 * Set MAR register(s) that corresponds to the specified address range.
404 *
405 * All cached entries in L1 and L2 are written back and invalidated.
406 *
407 * All MAR registers that corresponds within the specified base address
408 * and base address + size are set to the specified value.
409 *
410 * @a(Note)
411 * The 'wte' (Bit 1) and 'pcx' (Bit 2) MAR bits are reserved on
412 * C66x CorePac devices.
413 *
414 * @param(baseAddr) start address for which to set MAR
415 * @param(byteSize) size (in bytes) of memory block
416 * @param(value) value for setting MAR register
417 */
418 Void setMar(Ptr baseAddr, SizeT byteSize, UInt32 value);
419
420 /*!
421 * ======== inv ========
422 * Invalidate the range of memory within the specified starting address and
423 * byte count. The range of addresses operated on gets quantized to whole
424 * cache lines in each cache. All cache lines in range are invalidated in
425 * L1P cache. All cache lines in range are invalidated in L1D cache.
426 * All cache lines in range are invaliated in L2 cache.
427 */
428 override Void inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
429
430 /*!
431 * ======== wb ========
432 * Writes back the range of memory within the specified starting address
433 * and byte count. The range of addresses operated on gets quantized to
434 * whole cache lines in each cache. There is no effect on L1P cache.
435 * All cache lines within the range are left valid in L1D cache and the
436 * data within the range in L1D cache will be written back to L2 or
437 * external memory. All cache lines within the range are left valid in
438 * L2 cache and the data within the range in L2 cache will be written back
439 * to external memory.
440 */
441 override Void wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
442
443 /*!
444 * ======== wbInv ========
445 * Writes back and invalidates the range of memory within the specified
446 * starting address and byte count. The range of addresses operated on
447 * gets quantized to whole cache lines in each cache. All cache lines
448 * within range are invalidated in L1P cache. All cache lines within the
449 * range are written back to L2 or external and then invalidated in L1D
450 * cache. All cache lines within the range are written back to external
451 * memory and then invalidated in L2 cache.
452 */
453 override Void wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
454
455 /*!
456 * ======== invL1pAll ========
457 * Invalidate all of L1 Program cache
458 *
459 * Performs a global invalidate of L1P cache.
460 * Polls the L1P invalidate register until done.
461 */
462 Void invL1pAll();
463
464 /*!
465 * ======== wbAll ========
466 * Write back all caches
467 *
468 * Perform a global write back. There is no effect on L1P cache.
469 * All cache lines are left valid in L1D cache and dirty lines in L1D cache
470 * are written back to L2 or external. All cache lines are left valid in
471 * L2 cache and dirty lines in L2 cache are written back to external.
472 * This function does not wait for write back operation to perculate
473 * through the whole memory system before returing. Call Cache_wait(),
474 * after this function if necessary.
475 */
476 override Void wbAll();
477
478 /*!
479 * ======== wbL1dAll ========
480 * Write back L1D cache
481 *
482 * Perform a global write back of L1D cache. There is no effect on L1P
483 * or L2 cache. All cache lines are left valid in L1D cache and the
484 * dirty lines in L1D cache are written back to L2 or external.
485 * This function does not wait for write back operation to perculate
486 * through the whole memory system before returing. Call Cache_wait(),
487 * after this function if necessary.
488 */
489 Void wbL1dAll();
490
491 /*!
492 * ======== wbInvAll ========
493 * Write back invalidate all caches
494 *
495 * Performs a global write back and invalidate. All cache lines are
496 * invalidated in L1P cache. All dirty cache lines are written back to L2
497 * or external and then invalidated in L1D cache. All dirty cache lines
498 * are written back to external and then invalidated in L2 cache.
499 * This function does not wait for write back operation to perculate
500 * through the whole memory system before returing. Call Cache_wait(),
501 * after this function if necessary.
502 */
503 override Void wbInvAll();
504
505 /*!
506 * ======== wbInvL1dAll ========
507 * Write back invalidate L1D cache
508 *
509 * Performs a global write back and invalidate of L1D cache.
510 * All dirty cache lines are written back to L2 or
511 * external and then invalidated in L1D cache.
512 * This function does not wait for write back operation to perculate
513 * through the whole memory system before returing. Call Cache_wait(),
514 * after this function if necessary.
515 */
516 Void wbInvL1dAll();
517
518 internal:
519
520 /*!
521 * ======== RTSSynchInv ========
522 * @_nodoc
523 * Called by RTS for shared data synch invalidate
524 */
525 Void RTSSynchInv(Ptr blockPtr, SizeT byteCnt);
526
527 /*!
528 * ======== RTSSynchWb ========
529 * @_nodoc
530 * Called by RTS for shared data synch writeback
531 */
532 Void RTSSynchWb(Ptr blockPtr, SizeT byteCnt);
533
534 /*!
535 * ======== RTSSynchWbInv ========
536 * @_nodoc
537 * Called by RTS for shared data synch writeback/invalidate
538 */
539 Void RTSSynchWbInv(Ptr blockPtr, SizeT byteCnt);
540
541 /*!
542 * ======== invPrefetchBuffer ========
543 * Invalidate the prefetch buffer
544 */
545 Void invPrefetchBuffer();
546
547 548 549
550 Void all(volatile UInt32 *cacheReg);
551
552 553 554 555
556 Void block(Ptr blockPtr, SizeT byteCnt, Bool wait,
557 volatile UInt32 *barReg);
558
559 560 561
562 Void getL1DInitSize(Size *size);
563
564 565 566
567 Void getL1PInitSize(Size *size);
568
569 570 571
572 Void getL2InitSize(Size *size);
573
574
575 const UInt32 L2CFG = 0x01840000;
576 const UInt32 L1PCFG = 0x01840020;
577 const UInt32 L1PCC = 0x01840024;
578 const UInt32 L1DCFG = 0x01840040;
579 const UInt32 L1DCC = 0x01840044;
580 const UInt32 MAR = 0x01848000;
581
582
583 config UInt32 marvalues[256];
584
585 586 587 588
589 Void startup();
590 }