The Boot module supports boot initialization for the C28 cores.
Two special Boot init functions are created based on the configuration
settings for this module. One function is an xdc.runtime.Reset
function (called early at boot prior to cinit processing), and the second
function is an xdc.runtime.Startup first function (called before main()).
The code to support the boot module is placed in a separate section
named
".text:.bootCodeSection" to allow placement of this section in
the linker .cmd file if necessary. This section is a subsection of the
".text" section so this code will be placed into the .text section unless
explicitly placed, either through
Program.sectMap or through a linker
command file.
metaonly enum Boot.Div |
|
CM Clock Divider value
values of type Boot.Div
const Boot.Div_1;
// /1
const Boot.Div_2;
// /2
const Boot.Div_3;
// /3
const Boot.Div_4;
// /4
const Boot.Div_5;
// /5
const Boot.Div_6;
// /6
const Boot.Div_7;
// /7
const Boot.Div_8;
// /8
metaonly enum Boot.OscClk |
|
Oscillator Clock Source Select Bit for OSCCLK
values of type Boot.OscClk
const Boot.OscClk_INTOSC2;
// INTOSC2 (default on reset)
const Boot.OscClk_XTAL;
// External oscillator
const Boot.OscClk_INTOSC1;
// INTOSC1
const Boot.OscClk_RESERVED;
// Reserved (default to INTOSC1)
metaonly enum Boot.SrcCM |
|
CM Clock Source Select
values of type Boot.SrcCM
const Boot.SrcCM_AuxPLL;
// Auxillary PLL
const Boot.SrcCM_SystemPLL;
// System PLL
metaonly struct Boot.ModuleView |
|
var obj = new Boot.ModuleView;
obj.disableWatchdog = Bool ...
obj.configureClocks = Bool ...
obj.configureFlashController = Bool ...
obj.configureFlashWaitStates = Bool ...
obj.enableFlashProgramCache = Bool ...
obj.enableFlashDataCache = Bool ...
obj.configureSharedRAMs = Bool ...
obj.bootFromFlash = Bool ...
config Boot.configureClocks // module-wide |
|
Clock configuration flag, default is false
Boot.configureClocks = Bool false;
DETAILS
Set to true to configure the PLL and system subsystem clock
dividers.
C SYNOPSIS
metaonly config Boot.CMCLKDIV // module-wide |
|
CM Clock Divider Select (CMCLKDIV) value
metaonly config Boot.CMDIVSRCSEL // module-wide |
|
CM Clock source select bit (CMDIVSRCSEL)
metaonly config Boot.OSCCLK // module-wide |
|
OSCCLK input frequency to PLL, in MHz
DETAILS
This is the frequency of the oscillator clock (OSCCLK) input to the
PLL. The default internal oscillator is 10 Mhz.
metaonly config Boot.OSCCLKSRCSEL // module-wide |
|
Oscillator Clock source select bit for OSCCLK
DETAILS
The default on reset is INTOSC2
metaonly config Boot.SPLLIMULT // module-wide |
|
System PLL Integer Multiplier (SPLLIMULT) value
Boot.SPLLIMULT = UInt 38;
metaonly config Boot.SPLLODIV // module-wide |
|
System PLL Output Clock Divider (ODIV) value
metaonly config Boot.SPLLREFDIV // module-wide |
|
System PLL Reference Clock Divider (REFDIV) value
Boot.SPLLREFDIV = UInt 0;
metaonly config Boot.SYSCLKDIVSEL // module-wide |
|
System Clock Divider Select (SYSCLKDIVSEL) value
Boot.SYSCLKDIVSEL = UInt 0;
metaonly config Boot.bootFromFlash // module-wide |
|
Boot from Flash flag. Default is true
Boot.bootFromFlash = Bool true;
DETAILS
Set to true to enable booting CPU1 from Flash.
metaonly config Boot.configureFlashController // module-wide |
|
Flash controller configuration flag, default is true
Boot.configureFlashController = Bool true;
DETAILS
Set to true to enable the configuration of the Flash controller
wait states, program and data cache.
metaonly config Boot.configureFlashWaitStates // module-wide |
|
Flash controller wait states configuration flag, default is true
Boot.configureFlashWaitStates = Bool true;
DETAILS
Set to true to configure the Flash controller wait states. The number
of wait states is computed based upon the CPU frequency.
metaonly config Boot.configureSharedRAMs // module-wide |
|
Configure Shared RAM region ownership.
Default is false
Boot.configureSharedRAMs = Bool false;
DETAILS
Set to true to enable configuration of Shared RAM region
ownership.
metaonly config Boot.disableWatchdog // module-wide |
|
Watchdog disable flag, default is false
Boot.disableWatchdog = Bool false;
DETAILS
Set to true to disable the watchdog timer.
metaonly config Boot.enableFlashDataCache // module-wide |
|
Flash controller data cache enable flag, default is true
Boot.enableFlashDataCache = Bool true;
DETAILS
Set to true to enable the Flash controller's data cache.
metaonly config Boot.enableFlashProgramCache // module-wide |
|
Flash controller program cache enable flag, default is true
Boot.enableFlashProgramCache = Bool true;
DETAILS
Set to true to enable the Flash controller's program cache.
metaonly config Boot.limpAbortFunction // module-wide |
|
Function to be called when Limp mode is detected
Boot.limpAbortFunction = Fxn undefined;
DETAILS
This function is called when the Boot module is about to configure
the PLL, but finds the device operating in Limp mode (i.e., the mode
when a missing OSCCLK input has been detected).
If this function is not specified by the application, a default
function will be used, which spins in an infinite loop.
metaonly config Boot.loadSegment // module-wide |
|
Specifies where to load the Flash controller configuration function
(include the 'PAGE' number)
Boot.loadSegment = String undefined;
DETAILS
If 'configureFlashController' is true, then this parameter
determines where the ".ti_sysbios_family_c28_f2838x_init_flashfuncs"
section gets loaded.
metaonly config Boot.rovViewInfo // module-wide |
|
metaonly config Boot.runSegment // module-wide |
|
Specifies where to run the Flash controller configuration function
(include the 'PAGE' number)
Boot.runSegment = String undefined;
DETAILS
If 'configureFlashController' is true then this parameter
determines where the ".ti_sysbios_family_c28_f2838x_init_flashfuncs"
section gets executed at runtime.
metaonly config Boot.sharedMemoryOwnerMask // module-wide |
|
Shared RAM owner select mask
Boot.sharedMemoryOwnerMask = Bits32 0;
DETAILS
This parameter is used for writing the GSxMSEL register.
By default, each value of each shared RAM select bit is '0'.
This means the CPU1 is the owner and has write access.
Setting a '1' in any bit position makes CPU2 the owner of that
shared RAM segment.