1    /*
     2     * Copyright (c) 2018-2019, Texas Instruments Incorporated
     3     * All rights reserved.
     4     *
     5     * Redistribution and use in source and binary forms, with or without
     6     * modification, are permitted provided that the following conditions
     7     * are met:
     8     *
     9     * *  Redistributions of source code must retain the above copyright
    10     *    notice, this list of conditions and the following disclaimer.
    11     *
    12     * *  Redistributions in binary form must reproduce the above copyright
    13     *    notice, this list of conditions and the following disclaimer in the
    14     *    documentation and/or other materials provided with the distribution.
    15     *
    16     * *  Neither the name of Texas Instruments Incorporated nor the names of
    17     *    its contributors may be used to endorse or promote products derived
    18     *    from this software without specific prior written permission.
    19     *
    20     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
    21     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
    22     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
    23     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
    24     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
    25     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
    26     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
    27     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
    28     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
    29     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
    30     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    31     */
    32    /*
    33     *  ======== Boot.xdc ========
    34     *
    35     */
    36    
    37    package ti.sysbios.family.c28.f2838x.init;
    38    
    39    import xdc.rov.ViewInfo;
    40    
    41    /*!
    42     *  ======== Boot ========
    43     *  TMS320F2838X Boot Support.
    44     *
    45     *  The Boot module supports boot initialization for the C28 cores.
    46     *  Two special Boot init functions are created based on the configuration
    47     *  settings for this module.  One function is an xdc.runtime.Reset
    48     *  function (called early at boot prior to cinit processing), and the second
    49     *  function is an xdc.runtime.Startup first function (called before main()).
    50     *
    51     *  The code to support the boot module is placed in a separate section
    52     *  named `".text:.bootCodeSection"` to allow placement of this section in
    53     *  the linker .cmd file if necessary. This section is a subsection of the
    54     *  `".text"` section so this code will be placed into the .text section unless
    55     *  explicitly placed, either through
    56     *  `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
    57     *  command file.
    58     */
    59    @Template("./Boot.xdt")
    60    @NoRuntime
    61    module Boot
    62    {
    63        /*! Oscillator Clock Source Select Bit for OSCCLK */
    64        metaonly enum OscClk {
    65            OscClk_INTOSC2  = 0x0, /*! INTOSC2 (default on reset) */
    66            OscClk_XTAL     = 0x1, /*! External oscillator */
    67            OscClk_INTOSC1  = 0x2, /*! INTOSC1 */
    68            OscClk_RESERVED = 0x3  /*! Reserved (default to INTOSC1) */
    69        }
    70    
    71        /*! CM Clock Source Select */
    72        metaonly enum SrcCM {
    73            SrcCM_AuxPLL = 0,      /*! Auxillary PLL */
    74            SrcCM_SystemPLL = 1    /*! System PLL */
    75        };
    76    
    77        /*! CM Clock Divider value */
    78        metaonly enum Div {
    79            Div_1 = 0,   /*! /1 */
    80            Div_2 = 1,   /*! /2 */
    81            Div_3 = 2,   /*! /3 */
    82            Div_4 = 3,   /*! /4 */
    83            Div_5 = 4,   /*! /5 */
    84            Div_6 = 5,   /*! /6 */
    85            Div_7 = 6,   /*! /7 */
    86            Div_8 = 7    /*! /8 */
    87        };
    88    
    89        metaonly struct ModuleView {
    90            Bool disableWatchdog;
    91            Bool configureClocks;
    92            Bool configureFlashController;
    93            Bool configureFlashWaitStates;
    94            Bool enableFlashProgramCache;
    95            Bool enableFlashDataCache;
    96            Bool configureSharedRAMs;
    97            Bool bootFromFlash;
    98        }
    99    
   100        @Facet
   101        metaonly config ViewInfo.Instance rovViewInfo =
   102            ViewInfo.create({
   103                viewMap: [
   104                [
   105                    'Module',
   106                    {
   107                        type: ViewInfo.MODULE,
   108                        viewInitFxn: 'viewInitModule',
   109                        structName: 'ModuleView'
   110                    }
   111                ],
   112                ]
   113            });
   114    
   115        /*!
   116         *  Watchdog disable flag, default is false.
   117         *
   118         *  Set to true to disable the watchdog timer.
   119         */
   120        metaonly config Bool disableWatchdog = false;
   121    
   122        /*!
   123         *  Clock configuration flag, default is false.
   124         *
   125         *  Set to true to configure the PLL and system subsystem clock
   126         *  dividers.
   127         */
   128        config Bool configureClocks = false;
   129    
   130        /*!
   131         *  Oscillator Clock source select bit for OSCCLK
   132         *
   133         *  The default on reset is INTOSC2
   134         */
   135        metaonly config OscClk OSCCLKSRCSEL = OscClk_INTOSC2;
   136    
   137        /*!
   138         *  OSCCLK input frequency to PLL, in MHz.
   139         *
   140         *  This is the frequency of the oscillator clock (OSCCLK) input to the
   141         *  PLL.  The default internal oscillator is 10 Mhz.
   142         */
   143        metaonly config UInt OSCCLK = 10;
   144    
   145        /*! System PLL Integer Multiplier (SPLLIMULT) value */
   146        metaonly config UInt SPLLIMULT = 38;
   147    
   148        /*! System PLL Reference Clock Divider (REFDIV) value */
   149        metaonly config UInt SPLLREFDIV = 0;
   150    
   151        /*! System PLL Output Clock Divider (ODIV) value */
   152        metaonly config UInt SPLLODIV = 1;
   153    
   154        /*! System Clock Divider Select (SYSCLKDIVSEL) value */
   155        metaonly config UInt SYSCLKDIVSEL = 0;
   156    
   157        /*! CM Clock source select bit (CMDIVSRCSEL) */
   158        metaonly config SrcCM CMDIVSRCSEL = SrcCM_SystemPLL;
   159    
   160        /*! CM Clock Divider Select (CMCLKDIV) value */
   161        metaonly config Div CMCLKDIV = Div_2;
   162    
   163        /*!
   164         *  Function to be called when Limp mode is detected.
   165         *
   166         *  This function is called when the Boot module is about to configure
   167         *  the PLL, but finds the device operating in Limp mode (i.e., the mode
   168         *  when a missing OSCCLK input has been detected).
   169         *
   170         *  If this function is not specified by the application, a default
   171         *  function will be used, which spins in an infinite loop.
   172         */
   173        metaonly config Fxn limpAbortFunction;
   174    
   175        /*!
   176         *  Flash controller configuration flag, default is true.
   177         *
   178         *  Set to true to enable the configuration of the Flash controller
   179         *  wait states, program and data cache.
   180         */
   181        metaonly config Bool configureFlashController = true;
   182    
   183        /*!
   184         *  Flash controller wait states configuration flag, default is true.
   185         *
   186         *  Set to true to configure the Flash controller wait states.  The number
   187         *  of wait states is computed based upon the CPU frequency.
   188         */
   189        metaonly config Bool configureFlashWaitStates = true;
   190    
   191        /*!
   192         *  Flash controller program cache enable flag, default is true.
   193         *
   194         *  Set to true to enable the Flash controller's program cache.
   195         */
   196        metaonly config Bool enableFlashProgramCache = true;
   197    
   198        /*!
   199         *  Flash controller data cache enable flag, default is true.
   200         *
   201         *  Set to true to enable the Flash controller's data cache.
   202         */
   203        metaonly config Bool enableFlashDataCache = true;
   204    
   205        /*!
   206         *  Boot from Flash flag.  Default is true.
   207         *
   208         *  Set to true to enable booting CPU1 from Flash.
   209         */
   210        metaonly config Bool bootFromFlash = true;
   211    
   212        /*!
   213         *  Configure Shared RAM region ownership.
   214         *  Default is false.
   215         *
   216         *  Set to true to enable configuration of Shared RAM region
   217         *  ownership.
   218         */
   219        metaonly config Bool configureSharedRAMs = false;
   220    
   221       /*!
   222         *  ======== sharedMemoryOwnerMask ========
   223         *  Shared RAM owner select mask.
   224         *
   225         *  This parameter is used for writing the GSxMSEL register.
   226         *  By default, each value of each shared RAM select bit is '0'.
   227         *  This means the CPU1 is the owner and has write access.
   228         *  Setting a '1' in any bit position makes CPU2 the owner of that
   229         *  shared RAM segment.
   230         */
   231        metaonly config Bits32 sharedMemoryOwnerMask = 0;
   232    
   233        /*!
   234         *  ======== loadSegment ========
   235         *  Specifies where to load the Flash controller configuration function
   236         *  (include the 'PAGE' number)
   237         *
   238         *  If 'configureFlashController' is true, then this parameter
   239         *  determines where the ".ti_sysbios_family_c28_f2838x_init_flashfuncs"
   240         *  section gets loaded.
   241         */
   242        metaonly config String loadSegment;
   243    
   244        /*!
   245         *  ======== runSegment ========
   246         *  Specifies where to run the Flash controller configuration function
   247         *  (include the 'PAGE' number)
   248         *
   249         *  If 'configureFlashController' is true then this parameter
   250         *  determines where the ".ti_sysbios_family_c28_f2838x_init_flashfuncs"
   251         *  section gets executed at runtime.
   252         */
   253        metaonly config String runSegment;
   254    
   255        /*!
   256         *  @_nodoc
   257         *  ======== getFrequency ========
   258         *  Gets the resulting CPU frequency (in Hz) given the Clock
   259         *  configuration parameters.
   260         *
   261         */
   262        UInt32 getFrequency();
   263    
   264        /*!
   265         *  @_nodoc
   266         *  ======== registerFreqListener ========
   267         *  Register a module to be notified whenever the frequency changes.
   268         *
   269         *  The registered module must have a function named 'fireFrequencyUpdate'
   270         *  which takes the new frequency as an argument.
   271         */
   272        function registerFreqListener();
   273    
   274    internal:
   275    
   276        /* The computed timestamp frequency */
   277        metaonly config UInt timestampFreq;
   278    
   279        /* Used to display the computed CPU frequency value */
   280        metaonly config String displayFrequency;
   281    
   282        /* The computed Flash wait states */
   283        metaonly config UInt flashWaitStates;
   284    };