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33 34 35 36
37 package ti.sysbios.family.arm.v8m;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Diags;
41 import xdc.runtime.Log;
42 import xdc.runtime.Assert;
43 import xdc.runtime.Error;
44 import xdc.runtime.Types;
45
46 import ti.sysbios.BIOS;
47 import ti.sysbios.interfaces.IHwi;
48
49 /*!
50 * ======== Hwi ========
51 * Cortex V8M Hardware Interrupt Manager
52 *
53 * The Cortex-M devices' Nested Vectored Interrupt Controller (NVIC)
54 * supports up to 256 interrupts/exceptions. In practice, most
55 * devices support much fewer (ie the SimpleLink CC13XX/CC26XX
56 * family of devices have only 50 total interrupts defined).
57 *
58 * SYS/BIOS Interrupt IDs or interrupt numbers correspond
59 * to an interrupt's position in the interrupt vector table.
60 *
61 * ID 0 corresponds to vector 0 which is used by the NVIC
62 * to hold the initial (reset) stack pointer value.
63 *
64 * ID 1 corresponds to vector 1 which is the reset vector which is
65 * usually initialized to point to an application's entry point
66 * (ie for the TI compiler tool chain, the entry point is "_c_int00")
67 *
68 * IDs 2-13 are, by default, hard wired to the internal exception handler
69 * which will save important context information that can be viewed
70 * using the ROV tool within either the Code Composer Studio debugger
71 * or the IAR Workbench debugger.
72 *
73 * ID 14 is the "pendSV" handler which is used exclusively by the shared
74 * interrupt dispatcher to orchestrate the execution of
75 * {@link ti.sysbios.knl.Swi Swis} posted
76 * from within interrupts, as well as to manage asynchronous
77 * task pre-emption upon returning from interrupts which have
78 * readied a task of higher priority than the task that
79 * was interrupted.
80 *
81 * ID 15 is the SysTick timer interrupt.
82 *
83 * ID's 16-255 are mapped to the NVIC's "User" interrupts 0-239
84 * which are tied to platform specific interrupt sources.
85 *
86 * @a(Zero Latency Interrupts)
87 * The V8M Hwi module supports "zero latency" interrupts.
88 * Interrupts configured with priority greater (in actual
89 * hardware priority, but lower in number) than the configured
90 * {@link #disablePriority Hwi.disablePriority} are NOT
91 * disabled by {@link #disable Hwi_disable()}, and they are not managed by
92 * the internal interrupt dispatcher.
93 *
94 * Zero Latency interrupts fall into the commonly used category
95 * of "Unmanaged Interrupts". However they are somewhat distinct from
96 * that definition in that in addition to being unmanaged, they are
97 * also almost never disabled by SYS/BIOS code, thus gaining the
98 * "Zero Latency" title.
99 *
100 * Zero latency interrupts are distinguished from regular dispatched
101 * interrupts at create time solely by their interrupt priority being
102 * set greater than the configured Hwi.disablePriority.
103 *
104 * Note that since zero latency interrupts don't use the dispatcher,
105 * the {@link ti.sysbios.interfaces.IHwi#arg arg} parameter is not
106 * functional. Also note that due to the Cortex-M's native automatic
107 * stacking of saved-by-caller C context on the way to an ISR, zero
108 * latency interrupt handlers are implemented using regular C functions
109 * (ie no 'interrupt' keyword is required).
110 *
111 * @a(WARNING)
112 * Zero latency interrupts are NOT HANDLED by the SYS/BIOS
113 * interrupt dispatcher! Instead, they are vectored to directly.
114 * As such, and because they are NOT DISABLED BY Hwi_disable(),
115 * these interrupt handlers are SEVERELY RESTRICTED in terms of the
116 * SYS/BIOS APIs they can invoke and THREAD SAFETY MUST BE CAREFULLY
117 * CONSIDERED! See the descriptions of {@link #disable Hwi_disable()} and
118 * and {@link #disablePriority Hwi.disablePriority} for more details.
119 *
120 * @a(Interrupt Masking Options)
121 *
122 * The NVIC interrupt controller is designed for priority based
123 * interrupts.
124 *
125 * In this Hwi module, the {@link #maskSetting} instance configuration
126 * parameter is ignored.
127 * Effectively, only the {@link #MaskingOption_LOWER} is supported.
128 *
129 * @a(Interrupt Priorities)
130 *
131 * In general, the NVIC supports priority values of 0 thru 255.
132 *
133 * In practice, the number of priorities and their values are device
134 * dependent, and their nesting behaviors depend on the
135 * {@link #priGroup Hwi.priGroup} setting.
136 *
137 * For most TI MCU devices, 8 priorities are supported. A peculiarity
138 * of ARM's NVIC is that, although the priority field is an 8 bit value,
139 * the range of supported priority values are left-justified within this
140 * 8 bit field. Consequently, the 8 priority values are not 0 thru 7 as
141 * one might expect, but rather:
142 *
143 * @p(code)
144 * 0x00 // highest priority, non dispatched, Zero Latency priority
145 * 0x20 // highest dispatched interrupt priority
146 * 0x40
147 * 0x60
148 * 0x80
149 * 0xa0
150 * 0xc0
151 * 0xe0 // lowest dispatched interrupt priority, (default)
152 * @p
153 *
154 * Priority 0 is the highest priority and by default is
155 * reserved for zero latency interrupts
156 * (see {@link #disablePriority Hwi.disablePriority}).
157 *
158 * See the {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/CIHIGCIF.html Cortex M4 Devices Generic User Guide}
159 * for details on the behavior of interrupt priorities and their relationship
160 * to the {@link #priGroup Hwi.priGroup} setting.
161 *
162 * @a(Interrupt Vector Tables)
163 * SimpleLink CC13XX/CC26XX devices:
164 *
165 * By default, two vector tables are created for SimpleLink devices:
166 *
167 * A 15 entry boot vector table is placed at address 0x00000000 in
168 * FLASH.
169 *
170 * A 50 entry vector table is placed at address 0x20000000 in RAM.
171 *
172 * The FLASH boot vector table contains the reset vector and exception
173 * handler vectors used until the RAM based vector table is initialized.
174 *
175 * The RAM vector table contains those same first 15 vectors as well as
176 * the SysTick vector and the remainder of the user interrupt vectors.
177 *
178 * During system startup, the NVIC Vector Table Offset Registor is
179 * intialized to point to the RAM vector table after it has been
180 * initialized.
181 *
182 * @p(html)
183 * <h3> Calling Context </h3>
184 * <table border="1" cellpadding="3">
185 * <colgroup span="1"></colgroup> <colgroup span="5" align="center"></colgroup>
186 *
187 * <tr><th> Function </th><th> Hwi </th><th> Swi </th><th> Task </th><th> Main </th><th> Startup </th></tr>
188 * <!-- -->
189 * <tr><td> {@link #clearInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
190 * <tr><td> {@link #create} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
191 * <tr><td> {@link #disable} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
192 * <tr><td> {@link #disableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
193 * <tr><td> {@link #enable} </td><td> Y </td><td> Y </td><td> Y </td><td> N </td><td> N </td></tr>
194 * <tr><td> {@link #enableInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
195 * <tr><td> {@link #Params_init} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
196 * <tr><td> {@link #restore} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
197 * <tr><td> {@link #restoreInterrupt} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td></tr>
198 * <tr><td> {@link #construct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
199 * <tr><td> {@link #delete} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
200 * <tr><td> {@link #destruct} </td><td> N </td><td> N </td><td> Y </td><td> Y </td><td> N </td></tr>
201 * <tr><td> {@link #getHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
202 * <tr><td> {@link #setFunc} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
203 * <tr><td> {@link #setHookContext} </td><td> Y </td><td> Y </td><td> Y </td><td> Y </td><td> N </td></tr>
204 * <tr><td colspan="6"> Definitions: <br />
205 * <ul>
206 * <li> <b>Hwi</b>: API is callable from a Hwi thread. </li>
207 * <li> <b>Swi</b>: API is callable from a Swi thread. </li>
208 * <li> <b>Task</b>: API is callable from a Task thread. </li>
209 * <li> <b>Main</b>: API is callable during any of these phases: </li>
210 * <ul>
211 * <li> In your module startup after this module is started (e.g. Hwi_Module_startupDone() returns TRUE). </li>
212 * <li> During xdc.runtime.Startup.lastFxns. </li>
213 * <li> During main().</li>
214 * <li> During BIOS.startupFxns.</li>
215 * </ul>
216 * <li> <b>Startup</b>: API is callable during any of these phases:</li>
217 * <ul>
218 * <li> During xdc.runtime.Startup.firstFxns.</li>
219 * <li> In your module startup before this module is started (e.g. Hwi_Module_startupDone() returns FALSE).</li>
220 * </ul>
221 * </ul>
222 * </td></tr>
223 *
224 * </table>
225 * @p
226 */
227
228
229 @Template("./Hwi.xdt")
230 @ModuleStartup
231 @InstanceInitStatic
232
233 module Hwi inherits ti.sysbios.interfaces.IHwi
234 {
235
236
237 /*!
238 * The Cortex V8M NVIC supports up to 256 interrupts/exceptions.
239 *
240 * The actual number supported is device specific and provided by
241 * the catalog device specification.
242 */
243 config Int NUM_INTERRUPTS;
244
245 /*!
246 * The Cortex V8M NVIC supports up to 256 interrupt priorities.
247 *
248 * The actual number supported is device specific and provided by
249 * the catalog device specification. For all TI SimpleLink devices,
250 * 8 priorities are supported.
251 */
252 config Int NUM_PRIORITIES;
253
254
255
256 /*! Hwi vector function type definition. */
257 typedef Void (*VectorFuncPtr)(void);
258
259 /*! Exception hook function type definition. */
260 typedef Void (*ExceptionHookFuncPtr)(ExcContext *);
261
262 /*! NVIC Configuration Control Register (CCR). */
263 struct CCR {
264 Bits8 STKOFHFNMIGN; /*! Stack Limit Faults ignored */
265 Bits8 BFHFNMIGN; /*! All faults ignore BUS Faults */
266 Bits8 DIV_0_TRP; /*! Trap on divide by zero */
267 Bits8 UNALIGN_TRP; /*! Trap on all unaligned accesses */
268 Bits8 USERSETMPEND; /*! Allow user to trigger interrupts */
269 };
270
271 /*! @_nodoc
272 * Nested Vectored Interrupt Controller.
273 */
274 struct NVIC {
275 UInt32 RES_00; /*! 0xE000E000 reserved */
276 UInt32 ICTR; /*! 0xE000E004 Interrupt Control Type */
277 UInt32 RES_08; /*! 0xE000E008 reserved */
278 UInt32 RES_0C; /*! 0xE000E00C reserved */
279 UInt32 STCSR; /*! 0xE000E010 SysTick Control & Status Register */
280 UInt32 STRVR; /*! 0xE000E014 SysTick Reload Value Register */
281 UInt32 STCVR; /*! 0xE000E018 SysTick Current Value Register */
282 UInt32 STCALIB; /*! 0xE000E01C SysTick Calibration Value Register */
283 UInt32 RES_20 [56]; /*! 0xE000E020-0xE000E0FC reserved */
284 UInt32 ISER [16]; /*! 0xE000E100-0xE000E13C Interrupt Set Enable Registers */
285 UInt32 RES_140 [16]; /*! 0xE000E140-0xE000E17C reserved */
286 UInt32 ICER [16]; /*! 0xE000E180-0xE000E1BC Interrupt Clear Enable Registers */
287 UInt32 RES_1C0 [16]; /*! 0xE000E1C0-0xE000E1FC reserved */
288 UInt32 ISPR [16]; /*! 0xE000E200-0xE000E23C Interrupt Set Pending Registers */
289 UInt32 RES_240 [16]; /*! 0xE000E240-0xE000E7C reserved */
290 UInt32 ICPR [16]; /*! 0xE000E280-0xE000E2BC Interrupt Clear Pending Registers */
291 UInt32 RES_2C0 [16]; /*! 0xE000E2C0-0xE000E2FC reserved */
292 UInt32 IABR [16]; /*! 0xE000E300-0xE000E33C Interrupt Active Bit Registers */
293 UInt32 RES_340 [16]; /*! 0xE000E340-0xE000E37C reserved */
294 UInt32 ITNS [16]; /*! 0xE000E380-0xE000E3BC Interrupt Target Non-Secure Registers */
295 UInt32 RES_3C0 [16]; /*! 0xE000E3C0-0xE000E3FC reserved */
296 UInt8 IPR [492]; /*! 0xE000E400-0xE000E5EC Interrupt Priority Registers */
297 UInt32 RES_5F0 [453];/*! 0xE000E5F0-0xE000ECFC reserved */
298 UInt32 CPUIDBR; /*! 0xE000ED00 CPUID Base Register */
299 UInt32 ICSR; /*! 0xE000ED04 Interrupt Control State Register */
300 UInt32 VTOR; /*! 0xE000ED08 Vector Table Offset Register */
301 UInt32 AIRCR; /*! 0xE000ED0C Application Interrupt/Reset Control Register */
302 UInt32 SCR; /*! 0xE000ED10 System Control Register */
303 UInt32 CCR; /*! 0xE000ED14 Configuration Control Register */
304 UInt8 SHPR[12]; /*! 0xE000ED18 System Handlers 4-15 Priority Registers */
305 UInt32 SHCSR; /*! 0xE000ED24 System Handler Control & State Register */
306 UInt8 MMFSR; /*! 0xE000ED28 Memory Manage Fault Status Register */
307 UInt8 BFSR; /*! 0xE000ED29 Bus Fault Status Register */
308 UInt16 UFSR; /*! 0xE000ED2A Usage Fault Status Register */
309 UInt32 HFSR; /*! 0xE000ED2C Hard Fault Status Register */
310 UInt32 DFSR; /*! 0xE000ED30 Debug Fault Status Register */
311 UInt32 MMAR; /*! 0xE000ED34 Memory Manager Address Register */
312 UInt32 BFAR; /*! 0xE000ED38 Bus Fault Address Register */
313 UInt32 AFSR; /*! 0xE000ED3C Auxiliary Fault Status Register */
314 UInt32 PFR0; /*! 0xE000ED40 Processor Feature Register */
315 UInt32 PFR1; /*! 0xE000ED44 Processor Feature Register */
316 UInt32 DFR0; /*! 0xE000ED48 Debug Feature Register */
317 UInt32 AFR0; /*! 0xE000ED4C Auxiliary Feature Register */
318 UInt32 MMFR0; /*! 0xE000ED50 Memory Model Fault Register0 */
319 UInt32 MMFR1; /*! 0xE000ED54 Memory Model Fault Register1 */
320 UInt32 MMFR2; /*! 0xE000ED58 Memory Model Fault Register2 */
321 UInt32 MMFR3; /*! 0xE000ED5C Memory Model Fault Register3 */
322 UInt32 ISAR0; /*! 0xE000ED60 ISA Feature Register0 */
323 UInt32 ISAR1; /*! 0xE000ED64 ISA Feature Register1 */
324 UInt32 ISAR2; /*! 0xE000ED68 ISA Feature Register2 */
325 UInt32 ISAR3; /*! 0xE000ED6C ISA Feature Register3 */
326 UInt32 ISAR4; /*! 0xE000ED70 ISA Feature Register4 */
327 UInt32 ISAR5; /*! 0xE000ED74 ISA Feature Register5 */
328 UInt32 CLIDR; /*! 0xE000ED78 Cache Level ID Register */
329 UInt32 CTR; /*! 0xE000ED7C Cache Type Register */
330 UInt32 CCSIDR; /*! 0xE000ED80 Current Cache Size ID Register */
331 UInt32 CSSELR; /*! 0xE000ED84 Cache Size Selection Register */
332 UInt32 CPACR; /*! 0xE000ED88 Coprocessor Access Control Register */
333 UInt32 NSACR; /*! 0xE000ED8C Non-secure Access Control Register */
334
335 UInt32 MPU_TYPE; /*! 0xE000ED90 MPU Type Register */
336 UInt32 MPU_CTRL; /*! 0xE000ED94 MPU Control Register */
337 UInt32 MPU_RNR; /*! 0xE000ED98 MPU Region Number Register */
338 UInt32 MPU_RBAR; /*! 0xE000ED9C MPU Region Base Address Register */
339 UInt32 MPU_RLAR; /*! 0xE000EDA0 MPU Region Limit Address Register */
340 UInt32 MPU_RBAR_An; /*! 0xE000EDA4 MPU Region Base Address Register Alias n */
341 UInt32 MPU_RLAR_An; /*! 0xE000EDA8 MPU Region Limit Address Register Alias n */
342 UInt32 RES_DAC[5]; /*! 0xE000EDAC-0xE000EDBC */
343 UInt32 MPU_MAIR0; /*! 0xE000EDC0 MPU Memory Attribute Indirection Register 0 */
344 UInt32 MPU_MAIR1; /*! 0xE000EDC4 MPU Memory Attribute Indirection Register 1 */
345 UInt32 RES_DC8[2];
346
347 UInt32 SAU_CTRL; /*! 0xE000EDD0 SAU Control Register */
348 UInt32 SAU_TYPE; /*! 0xE000EDD4 SAU Type Register */
349 UInt32 SAU_RNR; /*! 0xE000EDD8 SAU Region Number Register */
350 UInt32 SAU_RBAR; /*! 0xE000EDDC SAU Region Base Address Register */
351 UInt32 SAU_RLAR; /*! 0xE000EDE0 SAU Region Limit Address Register */
352 UInt32 SFSR; /*! 0xE000EDE4 Secure Fault Status Register */
353 UInt32 SFAR; /*! 0xE000EDE8 Secure Fault Address Register */
354 UInt32 RES_DEC;
355
356 UInt32 DHCSR; /*! 0xE000EDF0 Debug Halting Control and Status Register */
357 UInt32 DCRSR; /*! 0xE000EDF4 Debug Core Register Select Register */
358 UInt32 DCRDR; /*! 0xE000EDF8 Debug Core Register Data Register */
359 UInt32 DEMCR; /*! 0xE000EDFC Debug Exception and Monitor Control Register */
360 UInt32 RES_E00;
361 UInt32 DAUTHCTRL; /*! 0xE000EE04 Debug Authentication Control Register */
362 UInt32 DSCSR; /*! 0xE000EE08 Debug Security Control and Status Register */
363 UInt32 RES_E0C[61]; /*! 0xE000EE0C-0xE000EEFC reserved */
364
365 UInt32 STI; /*! 0xE000EF00 Software Trigger Interrupt Register */
366 UInt32 RES_F04[12]; /*! 0xE000EF04-0xE000EF30 reserved */
367
368 UInt32 FPCCR; /*! 0xE000EF34 FP Context Control Register */
369 UInt32 FPCAR; /*! 0xE000EF38 FP Context Address Register */
370 UInt32 FPDSCR; /*! 0xE000EF3C FP Default Status Control Register */
371 UInt32 MVFR0; /*! 0xE000EF40 Media & FP Feature Register0 */
372 UInt32 MVFR1; /*! 0xE000EF44 Media & FP Feature Register1 */
373 UInt32 MVFR2; /*! 0xE000EF48 Media & FP Feature Register2 */
374 UInt32 RES_F48; /*! 0xE000EF4C reserved */
375
376 UInt32 ICIALLU; /*! 0xE000EF50 Instruction Cache Invalidate All to PoU */
377 UInt32 RES_F54; /*! 0xE000EF54 reserved */
378 UInt32 ICIMVAU; /*! 0xE000EF58 Instruction Cache line Invalidate by Address to PoU */
379 UInt32 DCIMVAC; /*! 0xE000EF5C Data Cache line Invalidate by Address to PoC */
380 UInt32 DCISW; /*! 0xE000EF60 Data Cache line Invalidate by Set/Way */
381 UInt32 DCCMVAU; /*! 0xE000EF64 Data Cache line Clean by address to PoU */
382 UInt32 DCCMVAC; /*! 0xE000EF68 Data Cache line Clean by Address to PoC */
383 UInt32 DCCSW; /*! 0xE000EF6C Data Cache Clean line by Set/Way */
384 UInt32 DCCIMVAC; /*! 0xE000EF70 Data Cache line Clean and Invalidate by Address to PoC */
385 UInt32 DCCISW; /*! 0xE000EF74 Data Cache line Clean and Invalidate by Set/Way */
386 UInt32 BPIALL; /*! 0xE000EF78 Branch Predictor Invalidate All */
387
388 UInt32 RES_F7C[13];
389 UInt32 DLAR; /*! 0xE000EFB0 SCS Software Lock Access Register */
390 UInt32 DLSR; /*! 0xE000EFB4 SCS Software Lock Status Register */
391 UInt32 DAUTHSTATUS; /*! 0xE000EFB8 Debug Authentication Status Register */
392 UInt32 DDEVARCH; /*! 0xE000EFBC SCS Device Architecture Register */
393 UInt32 RES_FC0[3];
394 UInt32 DDEVTYPE; /*! 0xE000EFCC SCS Device Type Register */
395 UInt32 DPIDR4; /*! 0xE000EFD0 SCS Peripheral Identification Register 4 */
396 UInt32 DPIDR5; /*! 0xE000EFD4 SCS Peripheral Identification Register 5 */
397 UInt32 DPIDR6; /*! 0xE000EFD8 SCS Peripheral Identification Register 6 */
398 UInt32 DPIDR7; /*! 0xE000EFDC SCS Peripheral Identification Register 7 */
399 UInt32 DPIDR0; /*! 0xE000EFE0 SCS Peripheral Identification Register 0 */
400 UInt32 DPIDR1; /*! 0xE000EFE4 SCS Peripheral Identification Register 1 */
401 UInt32 DPIDR2; /*! 0xE000EFE8 SCS Peripheral Identification Register 2 */
402 UInt32 DPIDR3; /*! 0xE000EFEC SCS Peripheral Identification Register 3 */
403 UInt32 DCIDR0; /*! 0xE000EFF0 SCS Component Identification Register 0 */
404 UInt32 DCIDR1; /*! 0xE000EFF4 SCS Component Identification Register 1 */
405 UInt32 DCIDR2; /*! 0xE000EFF8 SCS Component Identification Register 2 */
406 UInt32 DCIDR3; /*! 0xE000EFFC SCS Component Identification Register 3 */
407 }
408
409 /*!
410 * Physical Nested Vectored Interrupt Controller Device.
411 * Short name is "Hwi_nvic"
412 * Long name is "ti_sysbios_family_arm_v8m_Hwi_nvic"
413 */
414 extern volatile NVIC nvic;
415
416 /*!
417 * Exception Context - Register contents at the time of an exception.
418 */
419 struct ExcContext {
420
421 BIOS.ThreadType threadType;
422
423 Ptr threadHandle;
424
425 Ptr threadStack;
426
427
428 SizeT threadStackSize;
429
430
431 Ptr r0;
432 Ptr r1;
433 Ptr r2;
434 Ptr r3;
435 Ptr r4;
436 Ptr r5;
437 Ptr r6;
438 Ptr r7;
439 Ptr r8;
440 Ptr r9;
441 Ptr r10;
442 Ptr r11;
443 Ptr r12;
444 Ptr sp;
445 Ptr lr;
446 Ptr pc;
447 Ptr psr;
448
449
450 Ptr ICSR;
451 Ptr MMFSR;
452 Ptr BFSR;
453 Ptr UFSR;
454 Ptr HFSR;
455 Ptr DFSR;
456 Ptr MMAR;
457 Ptr BFAR;
458 Ptr AFSR;
459 }
460
461 struct Struct2__ {
462 Ptr fxns;
463 UArg arg;
464 FuncPtr fxn;
465 Irp irp;
466 UInt8 priority;
467 Int16 intNum;
468 Ptr hookEnv;
469 Types.CordAddr name;
470 };
471
472 typedef Struct2__ Struct2;
473
474 /*! @_nodoc */
475 metaonly struct BasicView {
476 Ptr halHwiHandle;
477 String label;
478 String type;
479 Int intNum;
480 Int priority;
481 Int group;
482 Int subPriority;
483 String fxn;
484 UArg arg;
485 };
486
487 /*! @_nodoc */
488 metaonly struct DetailedView {
489 Ptr halHwiHandle;
490 String label;
491 String type;
492 Int intNum;
493 Int priority;
494 Int group;
495 Int subPriority;
496 String fxn;
497 UArg arg;
498 Ptr irp;
499 String status;
500 };
501
502 /*! @_nodoc */
503 metaonly struct ModuleView {
504 String options[4];
505 String processorState;
506 String activeInterrupt;
507 String pendingInterrupt;
508 String exception;
509 String hwiStackPeak;
510 SizeT hwiStackSize;
511 Ptr hwiStackBase;
512 };
513
514 /*! @_nodoc */
515 metaonly struct VectorTableView {
516 UInt vectorNum;
517 Ptr vector;
518 String vectorLabel;
519 String type;
520 String priority;
521 Int preemptPriority;
522 Int subPriority;
523 String status;
524 String hwiHandle;
525 String hwiFxn;
526 UArg hwiArg;
527 Ptr hwiIrp;
528 };
529
530 /*! @_nodoc */
531 @Facet
532 metaonly config ViewInfo.Instance rovViewInfo =
533 ViewInfo.create({
534 viewMap: [
535 ['Basic',
536 {
537 type: ViewInfo.INSTANCE,
538 viewInitFxn: 'viewInitBasic',
539 structName: 'BasicView'
540 }
541 ],
542 ['Detailed',
543 {
544 type: ViewInfo.INSTANCE,
545 viewInitFxn: 'viewInitDetailed',
546 structName: 'DetailedView'
547 }
548 ],
549 ['Module',
550 {
551 type: ViewInfo.MODULE,
552 viewInitFxn: 'viewInitModule',
553 structName: 'ModuleView'
554 }
555 ],
556 ['Exception',
557 {
558 type: ViewInfo.TREE,
559 viewInitFxn: 'viewInitException',
560 structName: 'ExcContext'
561 }
562 ],
563 ['Vector Table',
564 {
565 type: ViewInfo.MODULE_DATA,
566 viewInitFxn: 'viewInitVectorTable',
567 structName: 'VectorTableView'
568 }
569 ]
570 ]
571 });
572
573
574
575
576
577 /*!
578 * Issued just prior to Hwi function invocation (with interrupts disabled)
579 */
580 config Log.Event LM_begin = {
581 mask: Diags.USER1 | Diags.USER2,
582 msg: "LM_begin: hwi: 0x%x, func: 0x%x, preThread: %d, intNum: %d, irp: 0x%x"
583 };
584
585 /*!
586 * Issued just after return from Hwi function (with interrupts disabled)
587 */
588 config Log.Event LD_end = {
589 mask: Diags.USER2,
590 msg: "LD_end: hwi: 0x%x"
591 };
592
593
594
595 /*! Assert when bad maskSetting parameter provided */
596 config Assert.Id A_unsupportedMaskingOption = {
597 msg: "A_unsupportedMaskingOption: unsupported maskSetting."
598 };
599
600
601
602 /*!
603 * Error raised if an attempt is made to create a Hwi
604 * with an interrupt number greater than Hwi_NUM_INTERRUPTS - 1.
605 */
606 config Error.Id E_badIntNum = {
607 msg: "E_badIntNum, intnum: %d is out of range"
608 };
609
610 /*!
611 * Error raised when Hwi is already defined
612 */
613 config Error.Id E_alreadyDefined = {
614 msg: "E_alreadyDefined: Hwi already defined: intr# %d"
615 };
616
617 /*!
618 * Error raised when the number of interrupts being created
619 * exceeds the number supported.
620 */
621 config Error.Id E_hwiLimitExceeded = {
622 msg: "E_hwiLimitExceeded: Too many interrupts defined"
623 };
624
625 /*!
626 * Error raised when an exception occurs
627 */
628 config Error.Id E_exception = {
629 msg: "E_exception: id = %d, pc = %08x.\nTo see more exception detail, set ti.sysbios.family.arm.v8m.Hwi.enableException = true or,\nexamine the Exception view for the ti.sysbios.family.arm.v8m.Hwi module using ROV."
630 };
631
632 /*!
633 * Error raised when an uninitialized interrupt occurs
634 */
635 config Error.Id E_noIsr = {
636 msg: "E_noIsr: id = %d, pc = %08x"
637 };
638
639 /*!
640 * Error raised when NMI exception occurs
641 */
642 config Error.Id E_NMI = {
643 msg: "E_NMI: %s"
644 };
645
646 /*!
647 * Error raised when hard fault exception occurs
648 */
649 config Error.Id E_hardFault = {
650 msg: "E_hardFault: %s"
651 };
652
653 /*!
654 * Error raised when memory fault exception occurs
655 */
656 config Error.Id E_memFault = {
657 msg: "E_memFault: %s, address: %08x"
658 };
659
660 /*!
661 * Error raised when bus fault exception occurs
662 */
663 config Error.Id E_busFault = {
664 msg: "E_busFault: %s, address: %08x"
665 };
666
667 /*!
668 * Error raised when usage fault exception occurs
669 */
670 config Error.Id E_usageFault = {
671 msg: "E_usageFault: %s"
672 };
673
674 /*!
675 * Error raised when svCall exception occurs
676 */
677 config Error.Id E_svCall = {
678 msg: "E_svCall: svNum = %d"
679 };
680
681 /*!
682 * Error raised when debugMon exception occurs
683 */
684 config Error.Id E_debugMon = {
685 msg: "E_debugMon: %s"
686 };
687
688 /*!
689 * Error raised when reserved exception occurs
690 */
691 config Error.Id E_reserved = {
692 msg: "E_reserved: %s %d"
693 };
694
695
696
697 /*!
698 * Size (in number of interrupts) of the table used by the interrupt
699 * dispatcher to locate the corresponding Hwi object. By default,
700 * Hwi.dispatchTableSize will be internally set
701 * to the number of interrupts supported by the device.
702 *
703 * When the Hwi dispatch table size is equal to the number of interrupts
704 * supported {@link #NUM_INTERRUPTS} by the device, a linear-indexed
705 * dispatch table mechanism is used that will consume 4 bytes of RAM
706 * for each interrupt supported.
707 *
708 * If the dispatch table size is set to a number less than the number
709 * of interrupts supported by the device, then a non linear-indexed
710 * dispatch table mechanism is employed that uses 12 bytes of RAM for
711 * each interrupt supported.
712 *
713 * Consequently, for applications that use less than 1/3 of the total
714 * number of interrupts supported by the device, setting this parameter
715 * to the number of interrupts ACTUALLY USED will result in less RAM
716 * memory being used than otherwise.
717 *
718 * For applications that use very few interrupts, this can be a significant RAM memory savings.</p>
719 */
720 metaonly config UInt dispatchTableSize;
721
722 /*!
723 * Location of the Runtime Interrupt Vector Table.
724 * Default is device dependent.
725 *
726 * This parameter allows the user to override the default placement
727 * of the runtime interrupt vector table.
728 * The NVIC's Vector Table Offset
729 * Register (VTOR) is also programmed to this value.
730 *
731 * Some systems require the runtime vector table to be placed at
732 * an address
733 * other than 0 but still need a copy of the two V8M boot vectors
734 * (SP and reset PC), located there. To achieve this, a separate
735 * parameter {@link #resetVectorAdress} is provided. If the
736 * resetVectorAddress has a different value then the vectorTableAddress
737 * then a separate vector table is generated and placed at that
738 * address.
739 *
740 * The vector table must be placed at an address at or lower than
741 * 0x3FFFFC00 and must be aligned on an even 64 word boundary.
742 */
743 metaonly config Ptr vectorTableAddress = 0x00000000;
744
745 /*!
746 * Reset vector table address. Default is 0x00000000.
747 *
748 * This parameter is the address of the vector table used
749 * at system reset time. Typically this is placed at 0x00000000.
750 *
751 * If the Hwi.resetVectorAddress has a different value than
752 * the {@link #vectorTableAddress Hwi.vectorTableAddress}
753 * then two vector tables are generated, one at the Hwi.resetVectorAddress
754 * and another at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
755 *
756 * After the initial boot code has been executed at startup, the NVIC's
757 * Vector Table Offset Register will be programmed to point to the
758 * vector table at the {@link #vectorTableAddress Hwi.vectorTableAddress}.
759 *
760 * is created and placed in the ".resetVecs" section.
761 */
762 metaonly config Ptr resetVectorAddress = 0x00000000;
763
764 /*! Reset Handler (ID/vector #1). Default is c_int00 */
765 metaonly config VectorFuncPtr resetFunc;
766
767 /*! NMI Handler (ID/vector #2). Default is set to an internal exception handler */
768 metaonly config VectorFuncPtr nmiFunc;
769
770 /*! Hard Fault Handler (ID/vector #3). Default is set to an internal exception handler */
771 metaonly config VectorFuncPtr hardFaultFunc;
772
773 /*! Mem Fault Handler (ID/vector #4). Default is set to an internal exception handler */
774 metaonly config VectorFuncPtr memFaultFunc;
775
776 /*! Bus Fault Handler (ID/vector #5). Default is set to an internal exception handler */
777 metaonly config VectorFuncPtr busFaultFunc;
778
779 /*! Usage Fault Handler (ID/vector #6). Default is set to an internal exception handler */
780 metaonly config VectorFuncPtr usageFaultFunc;
781
782 /*! SVCall Handler (ID/vector #11). Default is set to an internal exception handler */
783 metaonly config VectorFuncPtr svCallFunc;
784
785 /*! Debug Mon Handler (ID/vector #12). Default is set to an internal exception handler */
786 metaonly config VectorFuncPtr debugMonFunc;
787
788 /*! Reserved Exception Handler (ID/vector #13). Default is set to an internal exception handler */
789 metaonly config VectorFuncPtr reservedFunc;
790
791 /*! Uninitialized ISR Handler. Default is set to an internal exception handler */
792 config VectorFuncPtr nullIsrFunc;
793
794 /*! Hwi exception handler function type definition. */
795 typedef Void (*ExcHandlerFuncPtr)(UInt *, UInt);
796
797 /*!
798 * Exception handler function pointer.
799 *
800 * The default is determined by the value of Hwi.enableException.
801 *
802 * If the user does NOT set this parameter, then the following default
803 * behavior is followed:
804 *
805 * If Hwi.enableException is true, then the internal 'Hwi_excHandlerMax'
806 * function is used. This exception handler saves the exception context
807 * then does a complete exception decode and dump to the console, then
808 * raises an Error. The exception context can be viewed within CCS
809 * in the ROV Hwi module's Exception view.
810 *
811 * If Hwi.enableException is false, then the internal 'Hwi_excHandlerMin'
812 * function is used. This exception handler saves the exception context
813 * then raises an Error. The exception context can be viewed within CCS
814 * in the ROV Hwi module's Exception view.
815 *
816 * If the user sets this parameter to their own function, then the user's
817 * function will be invoked with the following arguments:
818 *
819 * Void myExceptionHandler(UInt *excStack, UInt lr);
820 *
821 * Where 'excStack' is the address of the stack containing the
822 * register context at the time of the exception, and 'lr' is the
823 * link register value when the low-level-assembly-coded exception
824 * handler was vectored to.
825 *
826 * If this parameter is set to 'null', then an infinite while loop is
827 * entered when an exception occurs. This setting minimizes code and
828 * data footprint but provides no automatic exception decoding.
829 */
830 config ExcHandlerFuncPtr excHandlerFunc = excHandlerMax;
831
832 /*!
833 * Enable full exception decoding
834 *
835 * When this is enabled, the exception handler will fully
836 * decode an exception and dump the registers to the
837 * system console.
838 */
839 metaonly config Bool enableException = true;
840
841 /*!
842 * User Exception Context Buffer Address
843 *
844 * By default, when an exception occurs, an {@link #ExcContext}
845 * structure is allocated on the ISR stack and filled in within the
846 * exception handler.
847 *
848 * If {@link #excContextBuffer} is initialized by the user, the
849 * {@link #ExcContext} structure will be placed at that address instead.
850 *
851 * The buffer must be large enough to contain an {@link #ExcContext}
852 * structure.
853 */
854 metaonly config Ptr excContextBuffer;
855
856 /*!
857 * User Exception Stack Buffer Address
858 *
859 * By default, when an exception occurs, a pointer to the base address
860 * of the stack being used by the thread causing the exception is placed
861 *
862 * If {@link #excStackBuffer} is initialized by the user, the
863 * stack contents of the thread causing the exception will be
864 * copied to that address instead.
865 *
866 * The buffer must be large enough to contain the largest task stack
867 * or ISR stack defined in the application.
868 */
869 metaonly config Ptr excStackBuffer;
870
871
872 /*!
873 * User Exception hook function.
874 *
875 * Called just after the exception context has been initialized.
876 *
877 * This function will be run on the ISR stack.
878 *
879 * This function must run to completion.
880 *
881 * It is called without any Task or Swi scheduling protection
882 * and therefore can not call any functions that may cause a Swi or Task
883 * scheduling operation (Swi_post(), Semaphore_post(), Event_post(), etc).
884 */
885 config ExceptionHookFuncPtr excHookFunc = null;
886
887 /*!
888 * NVIC CCR register settings
889 *
890 * These setting are written to Hwi_nvic.CCR at startup time.
891 *
892 * See the {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Bhcjabhi.html Configuration and Control Register}
893 * description provided by ARM for more details
894 * on the meanings of these parameters.
895 */
896 metaonly config CCR nvicCCR = {
897 STKOFHFNMIGN: 0,
898 BFHFNMIGN: 0,
899 DIV_0_TRP: 0,
900 UNALIGN_TRP: 0,
901 USERSETMPEND: 0
902 };
903
904 /*!
905 * The priority that BASEPRI is set to by Hwi_disable().
906 *
907 * All interrupts configured with equal or less priority (equal or
908 * higher number) than disablePriority are disabled by
909 * {@link #disable Hwi_disable}.
910 * Interrupts configured with higher priority (smaller number) than
911 * Hwi.disablePriority are non-maskable (ie zero-latency).
912 *
913 * The default setting is the second highest interrupt priority
914 * defined for the device (typically '0x20' for devices
915 * which support 8 priority values).
916 * This results in priority 0 (and all
917 * other values in the same priority group, ie 0x00 thru 0x1f)
918 * being the zero-latency, non-maskable interrupt priority.
919 * All other priorities are disabled with Hwi_disable().
920 */
921 config UInt disablePriority;
922
923 /*!
924 * The PRIGROUP setting. Default is 0.
925 *
926 * This value will be written to the PRIGROUP field
927 * within the NVIC's Application Interrupt and Reset Control
928 * Register (Hwi_nvic.AIRCR). It defines how the 8 bit priority
929 * values are interpreted by the hardware.
930 *
931 * Valid settings are 0-7.
932 *
933 * The default setting of 0 causes bits 7-1 of an interrupt's
934 * priority value to be used as pre-emption priority, while bit 0
935 * is used to determine which of two simultaneous interrupts with
936 * the same pre-emption priority will be serviced first.
937 *
938 * For most TI MCU devices, this means that each of the 8 supported
939 * priority values are unique pre-emption priorities and are not
940 * subdivided into priority groups.
941 *
942 * For more details regarding priority groups see the
943 * {@link http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Cihehdge.html AIRCR}
944 * register description provided by ARM.
945 */
946 config UInt priGroup = 0;
947
948 /*!
949 * Allow Non Secure code to use floating point coprocessor
950 */
951 metaonly config Bool enableNonSecureFloatingPointAccess = true;
952
953 /*!
954 * Allow Non Secure side Fault Handling
955 *
956 * When set to true, the non-secure side's fault handler vectors
957 * will be used when in non-secure mode.
958 *
959 * When set to false, the secure side's fault handler vectors
960 * will be used when in non-secure mode.
961 */
962 metaonly config Bool enableNonSecureFaultHandling = true;
963
964
965
966 /*!
967 * ======== construct2 ========
968 * Construct a Hwi object
969 *
970 * Hwi_construct2 constructs a Hwi object. This function is identical
971 * to Hwi_construct(), but does not take an Error_Block parameter, and
972 * returns a Hwi_Handle.
973 *
974 * The following C code sets Hwi parameters and
975 * constructs a Hwi object:
976 *
977 * @p(code)
978 *
979 * Hwi_Struct2 hwiStruct2;
980 * Hwi_Handle hwi;
981 *
982 * Void main()
983 * {
984 * Hwi_Params hwiParams;
985 *
986 * Hwi_Params_init(&hwiParams);
987 * hwiParams.arg = (UArg)arg;
988 * hwiParams.priority = intPriority;
989 *
990 * hwi = Hwi_construct2(&hwiStruct2, intNum, hwiFxn, &hwiParams);
991 * if (hwi == NULL) {
992 * // Failure
993 * }
994 *
995 * BIOS_start();
996 * }
997 * @p
998 *
999 * @param(hwi) Pointer to Hwi_Struct2 object.
1000 * @param(intNum) Interrupt priority
1001 * @param(hwiFxn) Hwi Function
1002 * @param(prms) Pointer to Hwi_Params structure
1003 *
1004 * @b(returns) A Hwi handle
1005 */
1006 Handle construct2(Struct2 *hwi, Int intNum, FuncPtr hwiFxn,
1007 const Params *prms);
1008
1009 /*!
1010 * ======== disable ========
1011 * Disable all non zero-latency interrupts
1012 *
1013 * Hwi_disable disables all non zero-latency hardware interrupts and
1014 * returns an
1015 * opaque key indicating whether interrupts were globally enabled or
1016 * disabled on entry to Hwi_disable().
1017 * The actual value of the key is target/device specific and is meant
1018 * to be passed to Hwi_restore().
1019 *
1020 * Call Hwi_disable before a portion of a function that needs
1021 * to run without interruption. When critical processing is complete, call
1022 * Hwi_restore or Hwi_enable to reenable hardware interrupts.
1023 *
1024 * Servicing of interrupts that occur while interrupts are disabled is
1025 * postponed until interrupts are reenabled. However, if the same type
1026 * of interrupt occurs several times while interrupts are disabled,
1027 * the interrupt's function is executed only once when interrupts are
1028 * reenabled.
1029 *
1030 * A context switch can occur when calling Hwi_enable or Hwi_restore if
1031 * an enabled interrupt occurred while interrupts are disabled.
1032 *
1033 * Hwi_disable may be called from main(). However, since Hwi interrupts
1034 * are already disabled in main(), such a call has no effect.
1035 *
1036 * @a(Implementation Note)
1037 * In order to support zero latency interrupts, rather
1038 * than setting PRIMASK (which would globally disable all NVIC
1039 * interrupts), Hwi_disable() instead writes the value of
1040 * {@link #disablePriority Hwi.disablePriority}
1041 * to the BASEPRI register. In doing so, all interrupts of equal or
1042 * lower priority than Hwi.disablePriority are disabled.
1043 *
1044 * @a(constraints)
1045 * If a Task switching API such as
1046 * {@link ti.sysbios.knl.Semaphore#pend Semaphore_pend()},
1047 * {@link ti.sysbios.knl.Semaphore#post Semaphore_post()},
1048 * {@link ti.sysbios.knl.Task#sleep Task_sleep()}, or
1049 * {@link ti.sysbios.knl.Task#yield Task_yield()}
1050 * is invoked which results in a context switch while
1051 * interrupts are disabled, an embedded call to
1052 * {@link #enable Hwi_enable} occurs
1053 * on the way to the new thread context which unconditionally re-enables
1054 * interrupts. Interrupts will remain enabled until a subsequent
1055 * {@link #disable Hwi_disable}
1056 * invocation.
1057 *
1058 * Swis always run with interrupts enabled.
1059 * See {@link ti.sysbios.knl.Swi#post Swi_post()} for a discussion Swis and
1060 * interrupts.
1061 *
1062 * @b(returns) opaque key for use by Hwi_restore()
1063 */
1064 @Macro
1065 override UInt disable();
1066
1067 /*!
1068 * ======== enable ========
1069 */
1070 @Macro
1071 override UInt enable();
1072
1073 /*!
1074 * ======== restore ========
1075 */
1076 @Macro
1077 override Void restore(UInt key);
1078
1079 /*!
1080 * @_nodoc
1081 * ======== disableFxn ========
1082 * function call implementation
1083 */
1084 UInt disableFxn();
1085
1086 /*!
1087 * @_nodoc
1088 * ======== enableFxn ========
1089 * function call implementation
1090 */
1091 UInt enableFxn();
1092
1093 /*!
1094 * @_nodoc
1095 * ======== restoreFxn ========
1096 * function call implementation
1097 */
1098 Void restoreFxn(UInt key);
1099
1100 /*!
1101 * ======== inUseMeta ========
1102 * @_nodoc
1103 * Check for Hwi already in use.
1104 * For internal SYS/BIOS use only.
1105 * Should be called prior to any internal Hwi.create().
1106 *
1107 * @param(intNum) interrupt number
1108 */
1109 metaonly Bool inUseMeta(UInt intNum);
1110
1111 /*!
1112 * ======== plug ========
1113 * Plug a non dispatched interrupt vector with an ISR address.
1114 *
1115 * Used internally by Hwi_create() and Hwi_construct().
1116 *
1117 * This API is provided for external use primarily to allow users
1118 * to plug the NMI vector (interrupt #2) at runtime.
1119 *
1120 * @a(Note)
1121 * Interrupt vectors plugged using Hwi_plug() are NOT managed by
1122 * the Hwi interrupt dispatcher. Consequently, it is not safe to
1123 * call SYS/BIOS APIs from within these ISRs.
1124 *
1125 * @param(intNum) interrupt number
1126 * @param(fxn) pointer to ISR function
1127 */
1128 Void plug(UInt intNum, Void *fxn);
1129
1130 /*!
1131 * ======== getHandle ========
1132 * Returns Hwi_handle associated with intNum
1133 *
1134 * @param(intNum) interrupt number
1135 */
1136 Handle getHandle(UInt intNum);
1137
1138 /*!
1139 * ======== setPriority ========
1140 * Set an interrupt's relative priority.
1141 *
1142 * Valid priorities are 0 - 255. 0 is highest priority.
1143 *
1144 * @a(WARNING)
1145 * Setting the priority of a dispatched Hwi to a value higher
1146 * than {@link #disablePriority Hwi.disablePriority} will make
1147 * it become non-maskable by {@link #disable Hwi_disable()}.
1148 * The behavior of your application after that will be
1149 * unpredictable and will likely yield catastrophic results!
1150 *
1151 * @param(intNum) ID of interrupt
1152 * @param(priority) priority
1153 */
1154 Void setPriority(UInt intNum, UInt priority);
1155
1156 /*!
1157 * ======== excSetBuffers ========
1158 * Set the exception context and stack buffer pointers
1159 *
1160 * @param(excContextBuffer) Address to place ExcContext
1161 * @param(excStackBuffer) Address to place ExcStack
1162 */
1163 Void excSetBuffers(Ptr excContextBuffer, Ptr excStackBuffer);
1164
1165 /*!
1166 * @_nodoc
1167 * ======== initNVIC ========
1168 * initialize everything but leave ints disabled
1169 */
1170 Void initNVIC();
1171
1172 /*!
1173 * @_nodoc
1174 * ======== initStacks ========
1175 * set up split stacks
1176 */
1177 Void initStacks(Ptr hwiStack);
1178
1179 instance:
1180
1181 /*!
1182 * Interrupt priority.
1183 * The default is 255 which is the lowest priority.
1184 *
1185 * Priority 0 is the highest priority and by default is
1186 * reserved for zero latency interrupts
1187 * (see {@link #disablePriority}).
1188 *
1189 * Valid priorities values are device dependent and their
1190 * nesting behaviors depend on the {@link #priGroup} setting.
1191 *
1192 * See the Cortex M33 architecture reference manual for details
1193 * on the meanings of these parameters.
1194 */
1195 override config Int priority = 255;
1196
1197 /*!
1198 * Interrupt Masking Option. Only MaskingOption_LOWER is supported.
1199 *
1200 * The NVIC interrupt controller is designed for priority based
1201 * interrupts. No support is provided for anything but
1202 * Hwi.MaskingOption_LOWER.
1203 */
1204 override config IHwi.MaskingOption maskSetting = IHwi.MaskingOption_LOWER;
1205
1206 /*!
1207 * Use the interrupt dispatcher with this interrupt. Default is true.
1208 *
1209 * If set to false, the interrupt dispatcher is NOT used. Instead,
1210 * the configured Hwi function address is placed directly in the
1211 * vector table, which results in the dispatcher being bypassed.
1212 *
1213 * @a(Warning)
1214 * Interrupts configured to bupass the dispatcher are not allowed
1215 * to call ANY SYS/BIOS APIs that effect thread scheduling. Examples
1216 * of API that should no be invoked are:
1217 *
1218 * @p(dlist)
1219 * - Swi_post(),
1220 * - Semaphore_post(),
1221 * - Event_post(),
1222 * - Task_yield()
1223 * @p
1224 *
1225 * Additionally, although the signature for a non-dispatched interrupt
1226 * function is the same as that for a dispatched interrupt
1227 * (see {@link #FuncPtr}), no argument is actually passed
1228 * to the non-dispatched ISR handler.
1229 */
1230 config Bool useDispatcher = true;
1231
1232 /*!
1233 * ======== reconfig ========
1234 * Reconfigure a dispatched interrupt.
1235 */
1236 Void reconfig(FuncPtr fxn, const Params *params);
1237
1238 internal:
1239
1240 /*!
1241 * If Hwi.dispatchTableSize is initialized by the user then
1242 * Hwi.numSparseInterrupts is set to the value of Hwi.dispatchTableSize
1243 *
1244 * If Hwi.dispatchTableSize is NOT set by the user, the normal
1245 * intNum-indexed Hwi dispatchTable mechanism is used by
1246 * the dispatcher to find the corresponding Hwi object.
1247 *
1248 * If Hwi.dispatchTableSize is set by the user, then a
1249 * RAM-based fixed sized interrupt jump table is generated
1250 * that contains a repeating pattern of the following 3 word
1251 * assembly code snippets:
1252 *
1253 * hwiX: ldr r3, hwiObjectX
1254 * ldr pc, ti_sysbios_family_arm_v8m_Hwi_dispatch__I
1255 * hwiObjectX: .word 0
1256 * hwiY: ldr r3, hwiObjectY
1257 * ldr pc, ti_sysbios_family_arm_v8m_Hwi_dispatch__I
1258 * hwiObjectY: .word 0
1259 * ...
1260 *
1261 * Each dispatched interrupt vector is then initialized to point
1262 * to one of these tuples, and the address of the corresponding Hwi
1263 * object is written into the hwiObjectX field.
1264 *
1265 * The low level assembly code in Hwi_dispatch__I preserves the
1266 * value of r3 when it calls Hwi_dispatchC(), which results in
1267 * the Hwi object being passed as the arg3.
1268 *
1269 * Depending on the boolean value of Hwi_numSparseInterrupts, the
1270 * dispatcher either uses the value passed in arg3 as the
1271 * Hwi object, or uses intNum to index into the standard
1272 * dispatchTable to fetch the Hwi object.
1273 */
1274 config UInt numSparseInterrupts = 0;
1275
1276 1277 1278 1279
1280 metaonly config Bool isTiva = false;
1281
1282 1283 1284 1285 1286 1287
1288 config UInt (*swiDisable)();
1289 config Void (*swiRestoreHwi)(UInt);
1290 config UInt (*taskDisable)();
1291 config Void (*taskRestoreHwi)(UInt);
1292
1293
1294 config UInt32 ccr;
1295
1296 /*!
1297 * const array to hold all HookSet objects.
1298 */
1299 config HookSet hooks[length] = [];
1300
1301 1302 1303 1304
1305 Int postInit(Object *hwi, Error.Block *eb);
1306
1307 /*!
1308 * ======== excHandlerAsm ========
1309 * asm code exception handler
1310 */
1311 Void excHandlerAsm();
1312
1313 /*!
1314 * ======== excHandler ========
1315 * exception Handler routes to
1316 * either min, max, or spin exception handler
1317 */
1318 Void excHandler(UInt *excStack, UInt lr);
1319
1320 /*!
1321 * ======== excHandlerMin ========
1322 * Minimal Exception Handler
1323 */
1324 Void excHandlerMin(UInt *excStack, UInt lr);
1325
1326 /*!
1327 * ======== excHandlerMax ========
1328 * Full Featured Exception Handler
1329 */
1330 Void excHandlerMax(UInt *excStack, UInt lr);
1331
1332 /*!
1333 * ======== excFillContext ========
1334 */
1335 Void excFillContext(UInt *excStack);
1336
1337 /*!
1338 * ======== excNmi ========
1339 */
1340 Void excNmi(UInt *excStack);
1341
1342 /*!
1343 * ======== excHardFault ========
1344 */
1345 Void excHardFault(UInt *excStack);
1346
1347 /*!
1348 * ======== excMemFault ========
1349 */
1350 Void excMemFault(UInt *excStack);
1351
1352 /*!
1353 * ======== excBusFault ========
1354 */
1355 Void excBusFault(UInt *excStack);
1356
1357 /*!
1358 * ======== excUsageFault ========
1359 */
1360 Void excUsageFault(UInt *excStack);
1361
1362 /*!
1363 * ======== excSvCall ========
1364 */
1365 Void excSvCall(UInt *excStack);
1366
1367 /*!
1368 * ======== excDebugMon ========
1369 */
1370 Void excDebugMon(UInt *excStack);
1371
1372 /*!
1373 * ======== excReserved ========
1374 */
1375 Void excReserved(UInt *excStack, UInt excNum);
1376
1377 /*!
1378 * ======== excNoIsr ========
1379 */
1380 Void excNoIsr(UInt *excStack, UInt excNum);
1381
1382 /*!
1383 * ======== excDumpRegs ========
1384 */
1385 Void excDumpRegs(UInt lr);
1386
1387 /*!
1388 * ======== pendSV ========
1389 * Used by dispatcher
1390 */
1391 Void pendSV();
1392
1393 1394 1395
1396 Void setStackLimit(Ptr stackBase);
1397
1398 /*! Hwi vector function type definition. */
1399 typedef Void (*HandlerFuncPtr)(Handle, UInt);
1400
1401
1402 Void dispatch();
1403
1404
1405 extern UInt32 ramVectors[];
1406
1407 1408 1409 1410 1411 1412
1413 Void romInitNVIC();
1414
1415 1416 1417 1418
1419 UInt dispatchC(Irp irp, UInt32 dummy1, UInt32 dummy2, Object *hwi);
1420
1421
1422 Void doSwiRestore(UInt tskKey);
1423
1424
1425 Void doTaskRestore(UInt tskKey);
1426
1427
1428 Void enableNonSecureFloatingPoint();
1429
1430
1431 Void enableNonSecureFaultHandlers();
1432
1433 /*! Meta World Only Hwi Configuration Object. */
1434 metaonly struct InterruptObj {
1435 String name;
1436 Bool used;
1437 Bool useDispatcher;
1438 UInt priority;
1439 FuncPtr fxn;
1440 Handle hwi;
1441 };
1442
1443 /*!
1444 * Meta-only array of interrupt objects.
1445 * This meta-only array of Hwi config objects is initialized
1446 * in Hwi.xs:module$meta$init().
1447 */
1448 metaonly config InterruptObj interrupt[];
1449
1450 struct Instance_State {
1451 UArg arg;
1452 FuncPtr fxn;
1453 Irp irp;
1454
1455 UInt8 priority;
1456 Int16 intNum;
1457
1458
1459 Ptr hookEnv[];
1460 };
1461
1462 struct Module_State {
1463 Char *taskSP;
1464
1465 Bool excActive;
1466 ExcContext *excContext;
1467 Ptr excStack;
1468 Ptr isrStack;
1469 Ptr isrStackBase;
1470 Ptr isrStackSize;
1471 Ptr vectorTableBase;
1472 UInt swiTaskKeys;
1473 Ptr dispatchTable;
1474 };
1475 }