1 /*
2 * Copyright (c) 2018, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32 /*
33 * ======== Core.xdc ========
34 */
35
36 package ti.sysbios.family.arm.v8a.smp;
37
38 import xdc.runtime.Error;
39 import ti.sysbios.family.arm.v8a.smp.GateSmp;
40
41 /*!
42 * ======== Core ========
43 * Core Identification Module.
44 *
45 * This Core module supports 2-core SMP mode on cluster 0
46 * and 4-core SMP mode with Core 0 being core 0 on cluster 0.
47 *
48 * 2-core SMP mode on Cluster 1 is explicitly NOT SUPPORTED.
49 */
50
51 @ModuleStartup
52 @CustomHeader
53
54 module Core inherits ti.sysbios.interfaces.ICore
55 {
56 /*!
57 * @_nodoc
58 * ======== CPUMASK ========
59 */
60 config UInt CPUMASK;
61
62 /*!
63 * @_nodoc
64 * ======== baseClusterId ========
65 */
66 config UInt baseClusterId = 0;
67
68 /*!
69 * @_nodoc
70 * ======== IpcFuncPtr ========
71 * IPC Callback function type definition.
72 */
73 typedef Void (*IpcFuncPtr)(UArg);
74
75 @Macro
76 override UInt hwiDisable();
77
78 @Macro
79 override UInt hwiEnable();
80
81 @Macro
82 override Void hwiRestore(UInt key);
83
84 /*!
85 * @_nodoc
86 * ======== getRevisionNumber ========
87 * Returns the major and minor revision number for the Cortex-A
88 * processor as a 2-nibble quantity [Major revision: Minor revision]
89 *
90 * This API is used internally by different modules to check
91 * the ARM IP revision number and determine whether or not an
92 * errata applies and requires a workaround.
93 */
94 UInt8 getRevisionNumber();
95
96 /*!
97 * @_nodoc
98 * ======== notifySpinLock ========
99 */
100 UInt notifySpinLock();
101
102 /*!
103 * @_nodoc
104 * ======== notifySpinUnlock ========
105 */
106 Void notifySpinUnlock(UInt key);
107
108 /*!
109 * @_nodoc
110 * ======== notify ========
111 * notify all cores specified by 'cpuMask' to execute callback function
112 * and wait for other cores to complete operation.
113 *
114 * @param(func) The callback function that is called by each
115 * interrupted core. If function pointer is NULL,
116 * the IPC handler simply returns.
117 * @param(arg) Argument to be passed to the callback function.
118 * @param(cpuMask) Bit mask of all CPUs that should be interrupted.
119 * If the MPCore sub-system has 4 CPUs and all need
120 * to be interrupted, a bit mask of 0b1111 or 0xF
121 * needs to be passed to Core_notify().
122 *
123 * @a(NOTE)
124 * SGI numbers 0, 1, 2 ..., N, where N is the number of cores in MPCore
125 * sub-system, are reserved for the internal use of the kernel.
126 *
127 * @a(NOTE)
128 * The call to this function should be protected with a
129 * Core_notifySpinLock()/Core_notifySpinUnlock(). This function should
130 * not be called with the inter-core lock already taken or it will spin
131 * forever as the other cores will not be able to service the notify
132 * interrupts.
133 */
134 Void notify(IpcFuncPtr func, UArg arg, UInt cpuMask);
135
136 internal:
137
138 /*
139 * ======== IpcMsg ========
140 * IPC message structure
141 */
142 struct IpcMsg {
143 IpcFuncPtr func;
144 UArg arg;
145 };
146
147 config GateSmp.Handle gate;
148
149 config Bool initStackFlag = true;
150
151 /*
152 * ======== startCoreX ========
153 */
154 Void startCoreX();
155
156 /*
157 * ======== exit ========
158 */
159 Void exit(UArg arg);
160
161 /*
162 * ======== hwiFunc ========
163 *
164 * Hwi func attached to Core.interruptCore()
165 */
166 Void hwiFunc(UArg arg);
167
168 /*
169 * ======== startup ========
170 * Other core's first function
171 */
172 Void startup();
173
174 /*!
175 * ======== atexit ========
176 * atexit() func used to signal the other core to halt
177 */
178 Void atexit(Int arg);
179
180 struct Module_State {
181 Bool startupCalled;
182 Bool gateEntered[];
183 UInt schedulerInts[];
184 UInt interrupts[][];
185 volatile Bool syncCores[][];
186 volatile IpcMsg ipcMsg[];
187 volatile Bool notifyLock;
188 };
189 }