1 /* 2 * Copyright (c) 2016-2018, Texas Instruments Incorporated 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * ======== Core.xdc ======== 34 */ 35 36 /*! 37 * ======== Core ======== 38 * ICore implementation for default BIOS CoreDelegate 39 */ 40 module Core inherits ti.sysbios.interfaces.ICore 41 { 42 /*! 43 * ======== id ======== 44 * Non SMP Core ID, default is Core 0 45 * 46 * Used for making static decisions based on Core ID 47 */ 48 config UInt id = 0; 49 50 /*! 51 * @_nodoc 52 * ======== baseClusterId ======== 53 */ 54 config UInt baseClusterId = 0; 55 56 override config UInt numCores = 1; 57 58 /*! 59 * ======== bootMaster ======== 60 * Boolean flag indicating whether this core is boot master 61 * 62 * If a core is marked as a boot master then, it will initialize 63 * shared global peripherals like the GIC distributor. This 64 * config param should be set to false for secondary cores 65 * running in an AMP system. 66 */ 67 metaonly config Bool bootMaster = true; 68 69 /*! 70 * ======== getClusterId ======== 71 * Returns the core's cluster Id 72 */ 73 UInt getClusterId(); 74 75 /*! 76 * @_nodoc 77 * ======== getRevisionNumber ======== 78 * Returns the major and minor revision number for the Cortex-A 79 * processor as a 2-nibble quantity [Major revision: Minor revision] 80 * 81 * This API is used internally by different modules to check 82 * the ARM IP revision number and determine whether or not an 83 * errata applies and requires a workaround. 84 */ 85 UInt8 getRevisionNumber(); 86 87 internal: 88 89 /* 90 * ======== reset ======== 91 * Switch CPU execution level from EL3/EL2 to EL1 92 */ 93 Void reset(); 94 95 /* 96 * ======== disableCaches ======== 97 */ 98 Void disableCaches(); 99 100 /* 101 * ======== getGicxAddr ======== 102 * Return GIC redistributor RD_base/SGI_base address for this core 103 */ 104 Ptr getGicrBaseAddr(Ptr gicRedistributorBaseAddress); 105 }