This module manages the data and instruction caches on ARMv8A
processors.
It provides a list of functions that perform cache operations. The
functions operate on a per cache line except for the 'All' functions
which operate on the entire cache specified. Any Address that is not
aligned to a cache line gets rounded down to the address of
the nearest cache line.
The L1 data and program caches as well as the L2 cache are enabled
by default early during the startup sequence (prior to any
Module_startup()s).
Data caching requires the MMU to be enabled and the cacheable
attribute of the section/page descriptor for a corresponding
memory region to be enabled.
Program caching does not require the MMU to be enabled and therefore
occurs when the L1 program cache is enabled.
Note: The invalidate instruction is treated by A53/A57/A72 as a
clean/invalidate instruction. Therefore, calls to Cache_inv()
will behave like Cache_wbInv().
enum Cache_Type |
|
Lists of bitmask cache types
typedef enum Cache_Type {
Cache_Type_L1P,
// Level 1 Program cache
Cache_Type_L1D,
// Level 1 Data cache
Cache_Type_L1,
// Level 1 caches
Cache_Type_L2P,
// Level 2 Program cache
Cache_Type_L2D,
// Level 2 Data cache
Cache_Type_L2,
// Level 2 caches
Cache_Type_ALLP,
// All Program caches
Cache_Type_ALLD,
// All Data caches
Cache_Type_ALL
// All caches
} Cache_Type;
config Cache_enableCache // module-wide |
|
Enable L1 and L2 data and program caches
extern const Bool Cache_enableCache;
DETAILS
Not implemented by all architectures. Refer to specific
architecture Cache module for details.
To enable a subset of the caches, set this parameter
to 'false' and call Cache_enable() within main, passing it only
the
Cache_Type(s) to be enabled.
Data caching requires the MMU and the memory section/page
descriptor cacheable attribute to be enabled.
Cache_disable() // module-wide |
|
Disables the 'type' cache(s)
Void Cache_disable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
Cache_enable() // module-wide |
|
Enables all cache(s)
Void Cache_enable(Bits16 type);
ARGUMENTS
type
bit mask of Cache type
Cache_inv() // module-wide |
|
Invalidate the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
in range are invalidated for all the 'type' caches
Void Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_invL1pAll() // module-wide |
|
Invalidate all of L1 program cache
Cache_wait() // module-wide |
|
Wait for a previous cache operation to complete
DETAILS
Wait for the cache wb/wbInv/inv operation to complete. A cache
operation is not truly complete until it has worked its way
through all buffering and all memory writes have landed in the
source memory.
Cache_wb() // module-wide |
|
Writes back a range of memory from all cache(s)
Void Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
DETAILS
Writes back the range of memory within the specified starting
address and byte count. The range of addresses operated on
gets quantized to whole cache lines in each cache. All lines
within the range are left valid in the 'type' caches and the data
within the range will be written back to the source memory.
Cache_wbAll() // module-wide |
|
Performs a global write back by set/way of one or more levels of cache.
The cache maintenance operations performed during this sequence are not
broadcast to other CPUs within the same shareability domain. Unless all
memory locations are regarded as non-cacheable on other CPUs, it is not
possible to prevent locations from being allocated into the cache by
other CPUs while this cache manintenance operation is in progress
DETAILS
Perform a global write back. There is no effect on program cache.
All data cache lines are left valid.
Cache_wbInv() // module-wide |
|
Writes back and invalidates the range of memory within the
specified starting address and byte count. The range of
addresses operated on gets quantized to whole cache lines in
each cache. All lines within the range are written back to the
source memory and then invalidated for all 'type' caches
Void Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait);
ARGUMENTS
blockPtr
start address of range to be invalidated
byteCnt
number of bytes to be invalidated
type
bit mask of Cache type
wait
wait until the operation is completed
Cache_wbInvAll() // module-wide |
|
Performs a global write back and invalidate by set/way of one or more
levels of cache. The cache maintenance operations performed during this
sequence are not broadcast to other CPUs within the same shareability
domain. Unless all memory locations are regarded as non-cacheable by
other CPUs, it is not possible to prevent locations from being
allocated into the cache by other CPUs while this cache manintenance
operation is in progress
DETAILS
Performs a global write back and invalidate. All cache lines
are written out to physical memory and then invalidated.
Module-Wide Built-Ins |
|
// Get this module's unique id
Bool Cache_Module_startupDone();
// Test if this module has completed startup
// The heap from which this module allocates memory
Bool Cache_Module_hasMask();
// Test whether this module has a diagnostics mask
Bits16 Cache_Module_getMask();
// Returns the diagnostics mask for this module
Void Cache_Module_setMask(Bits16 mask);
// Set the diagnostics mask for this module