1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
32
33 34 35
36
37 package ti.sysbios.family.arm.msp432.init;
38
39 import xdc.rov.ViewInfo;
40 import xdc.runtime.Assert;
41
42 /*!
43 * ======== Boot ========
44 * MSP432 device Boot Support.
45 *
46 * The Boot module supports boot initialization for MSP432 devices.
47 * A special boot init function is created based on the configuration
48 * settings for this module. This function is hooked into the
49 * xdc.runtime.Reset.fxns[] array and called very early at boot time.
50 *
51 * The code to support the boot module is placed in a separate section
52 * named `".text:.bootCodeSection"` to allow placement of this section in
53 * the linker .cmd file if necessary. This section is a subsection of the
54 * `".text"` section so this code will be placed into the .text section unless
55 * explicitly placed, either through
56 * `{@link xdc.cfg.Program#sectMap Program.sectMap}` or through a linker
57 * command file.
58 */
59 @Template("./Boot.xdt")
60 module Boot
61 {
62 /*! clock speed setting */
63 enum SpeedOpt {
64 SpeedOpt_Low = 0,
65 SpeedOpt_Medium = 1,
66 SpeedOpt_High = 2
67 };
68
69 metaonly struct ModuleView {
70 Bool configureClocks;
71 Bool disableWatchdog;
72 }
73
74 @Facet
75 metaonly config ViewInfo.Instance rovViewInfo =
76 ViewInfo.create({
77 viewMap: [
78 [
79 'Module',
80 {
81 type: ViewInfo.MODULE,
82 viewInitFxn: 'viewInitModule',
83 structName: 'ModuleView'
84 }
85 ],
86 ]
87 });
88
89 /*!
90 * Clock configuration flag, default is true.
91 *
92 * Set to false to disable clock configuration.
93 *
94 * Clock configuration will setup the clock system (CS), VCORE, and
95 * Flash wait states appropriately, for one of three different device
96 * speed options, as selected by `{@link #speedSelect}`.
97 *
98 * Clock configuration by the Boot module is only supported for
99 * MSP432P401x devices. If an attempt is made to enable this feature for
100 * newer MSP432 devices a build error will be thrown.
101 */
102 metaonly config Bool configureClocks;
103
104 /*!
105 * Clock speed selection, default is SpeedOpt_High.
106 *
107 * This enumeration is used to select one of three different speed options
108 * that will be configured when `{@link #configureClocks}` is set to
109 * "true".
110 *
111 * @p(code)
112 * SpeedOpt_High will configure:
113 * MCLK = 48MHz from DCO, HFXT, or external clock
114 * HSMCLK = 24MHz from DCO, HFXT, or external clock
115 * SMCLK = 12MHz from DCO, HFXT, or external clock
116 * ACLK = 32KHz from REFOCLK, LFXT, or external clock
117 * BCLK = 32KHz from REFOCLK, LFXT, or external clock
118 * VCORE = 1 (AM1_LDO mode)
119 * Flash BNK0 and BNK1 read wait states = 1
120 *
121 * SpeedOpt_Medium will configure:
122 * MCLK = 24MHz from DCO, HFXT, or external clock
123 * HSMCLK = 6MHz from DCO, HFXT, or external clock
124 * SMCLK = 6MHz from DCO, HFXT, or external clock
125 * ACLK = 32KHz from REFOCLK, LFXT, or external clock
126 * BCLK = 32KHz from REFOCLK, LFXT, or external clock
127 * VCORE = 1 (AM1_LDO mode)
128 * Flash BNK0 and BNK1 read wait states = 1
129 *
130 * SpeedOpt_Low will configure:
131 * MCLK = 12MHz from DCO, HFXT, or external clock
132 * HSMCLK = 3MHz from DCO, HFXT, or external clock
133 * SMCLK = 3MHz from DCO, HFXT, or external clock
134 * ACLK = 32KHz from REFOCLK, LFXT, or external clock
135 * BCLK = 32KHz from REFOCLK, LFXT, or external clock
136 * VCORE = 0 (AM0_LDO mode)
137 * Flash BNK0 and BNK1 read wait states = 0
138 * @p
139 */
140 metaonly config SpeedOpt speedSelect = SpeedOpt_High;
141
142 /*!
143 * Enable LF crystal (LFXT) flag, default is false.
144 *
145 * If an external 32768-Hz LF crystal is available, set this flag to
146 * true to startup and enable the LFXT, for use as the ACLK and BCLK
147 * clock sources.
148 */
149 config Bool enableLFXT = false;
150
151 /*!
152 * LF crystal bypass flag, default is false.
153 *
154 * As an alternative to LFXT-sourced clocks, an external 32768-Hz square
155 * wave can be applied to LFXIN, to be used as the ACLK and BCLK clock
156 * sources.
157 *
158 * To enable this mode, set Boot.enableLFXT to true to enable the LFXT
159 * pins, and set Boot.bypassLFXT to true to disable the LFXT oscillator.
160 */
161 config Bool bypassLFXT = false;
162
163 /*!
164 * Enable HF crystal (HFXT) flag, default is false.
165 *
166 * If an external 48-MHz HFXT crystal is available, set this flag to
167 * true to startup and enable the HFXT, for use as the MCLK, HSMCLK, and
168 * SMCLK clock sources.
169 */
170 config Bool enableHFXT = false;
171
172 /*!
173 * HF crystal bypass flag, default is false.
174 *
175 * As an alternative to HFXT-sourced clocks, an external 48-MHz square
176 * wave can be applied to HFXIN, to be used as the MCLK, HSMCLK, and SMCLK
177 * clock sources.
178 *
179 * To enable this bypass mode, set Boot.enableHFXT to true to enable the
180 * HFXT pins, and set Boot.bypassHFXT to true to disable the HFXT
181 * oscillator.
182 */
183 config Bool bypassHFXT = false;
184
185 /*!
186 * Watchdog disable configuration flag, default is true.
187 *
188 * Set to false to disable the disabling of the watchdog.
189 */
190 metaonly config Bool disableWatchdog = true;
191
192 /*!
193 * @_nodoc
194 * ======== registerFreqListener ========
195 * Register a module to be notified whenever the frequency changes.
196 *
197 * The registered module must have a function named 'fireFrequencyUpdate'
198 * which takes the new frequency as an argument.
199 */
200 function registerFreqListener();
201
202 internal:
203
204 205 206 207 208 209
210 Void init();
211
212 /*!
213 * computed cpu frequency based on clock settings
214 */
215 metaonly config UInt computedCpuFrequency;
216
217 };